Power semiconductor device, method for manufacturing power semiconductor device, and power conversion device

Abstract

The present disclosure aims to provide a trench gate type power semiconductor device that is not easily damaged even when stress is applied. A SiC-MOSFET (101) includes a SiC substrate (1), a drift layer (2) formed on the SiC substrate (1) and being a first conductivity type, a base region (3) formed on a surface layer of the drift layer (2) and being a second conductivity type different from the first conductivity type, a source region (4) selectively formed on a surface layer of the base region (3) and being the first conductivity type, a trench (19) that penetrates the base region (3) and the source region (4) and reaches the drift layer (2), a gate electrode (7) embedded in the trench (19) and having a V-shaped groove (7a) on an upper surface, and an oxide film (8) formed on an upper surface of the gate electrode (7) including the groove (7a).

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor device. Background Art

[0002] Semiconductor devices using silicon carbide (SiC) substrates (hereinafter referred to as "SiC semiconductor devices") have superior voltage and heat resistance compared to semiconductor devices using silicon (Si) substrates (hereinafter referred to as "Si semiconductor devices"). To achieve higher voltage resistance, lower losses, and operate in high-temperature environments, SiC semiconductor devices have traditionally been used in power semiconductor devices such as MOSFETs (metal-oxide-semiconductor field-effect transistors) and IGBTs (insulated gate bipolar transistors).

[0003] SiC has a higher dielectric breakdown electric field strength than Si. Therefore, SiC semiconductor devices can make the voltage-resistant layer (drift layer) thinner than Si semiconductor devices to achieve the same withstand voltage. In addition, SiC semiconductor devices can increase the impurity doping amount of the voltage-resistant layer compared to Si semiconductor devices. For these reasons, SiC semiconductor devices can obtain a significantly reduced on-resistance compared to Si semiconductor devices. For example, the on-resistance of a SiC-MOSFET with a withstand voltage of more than 1 kV and less than 1.2 kV is 5 mΩcm 2 Compared with Si-MOSFET or Si-IGBT with the same withstand voltage, this value is less than half.

[0004] In the future, it is expected that as manufacturing costs improve, process technology advances, and other performance improvements are made, the majority of Si-IGBTs used as inverter components will be replaced by SiC semiconductor devices. Currently, trench-gate SiC-MOSFETs and SiC-IGBTs are being developed to reduce the losses in SiC semiconductor devices during power-on.

[0005] However, in trench-gate SiC-MOSFETs or SiC-IGBTs, there is a problem in that a damaged layer is generated on the inner wall of the trench during etching for forming the trench.

[0006] Patent document 1 discloses a method for manufacturing a SiC-MOSFET that removes a damaged layer on the inner wall of a trench. According to the manufacturing method of patent document 1, a deposited film having a thickness on the surface of the semiconductor substrate that is thicker than the thickness of the inner wall of the trench is formed on the surface of the semiconductor substrate and the inner wall of the trench. Then, the portion of the deposited film covering the inner wall of the trench is removed to expose the inner wall of the trench. Next, after an oxide film is grown on the inner wall of the trench, the deposited film and the oxide film are removed. According to this method, by forming a deposited film on the surface of the semiconductor substrate, it is difficult to form an oxide film on the surface of the semiconductor substrate when the oxide film is grown on the inner wall of the trench. Therefore, the diffusion layer on the surface of the semiconductor substrate can be maintained.

[0007] Prior art literature

[0008] Patent Literature

[0009] Patent Document 1: Japanese Patent Application Laid-Open No. 2017-126630 Summary of the Invention

[0010] Problems to be solved by the invention

[0011] A power module includes a power semiconductor device and a power supply line connected to the power semiconductor device. When the power supply line is connected to a trench-gate power semiconductor device, there is a problem: stress applied from the line to the power semiconductor device during connection can damage the trench gate, causing the power module to cease functioning.

[0012] In SiC-MOSFETs manufactured using the manufacturing method of Patent Document 1, the gate electrode is uniformly formed within the trench. Therefore, when subjected to stress from the surrounding area, the gate electrode may be damaged, such as shifting between the gate electrode and the SiC substrate. This phenomenon is particularly significant for stress in a direction parallel to the trench gate.

[0013] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a trench-gate power semiconductor device that is not easily broken even when stress is applied.

[0014] Means for solving problems

[0015] The power semiconductor device disclosed herein comprises: a SiC substrate; a drift layer formed on the SiC substrate and having a first conductivity type; a first impurity region formed on a surface layer of the drift layer and having a second conductivity type different from the first conductivity type; a second impurity region selectively formed on a surface layer of the first impurity region and having the first conductivity type; a trench penetrating the first and second impurity regions and reaching the drift layer; a gate electrode embedded in the trench and having a V-shaped groove on its upper surface; and an oxide film formed on the upper surface of the gate electrode including the groove, the bottom of the V-shaped groove being deeper than the first impurity region.

[0016] In the disclosed method for manufacturing a power semiconductor device, a drift layer of a first conductivity type is formed on a SiC substrate, a first impurity region of a second conductivity type different from the first conductivity type is formed on the surface of the drift layer, a second impurity region of the first conductivity type is selectively formed on the surface of the first impurity region, a trench is formed penetrating the first and second impurity regions and reaching the drift layer, a gate electrode having a V-shaped groove on its upper surface is formed within the trench, and an oxide film is formed on the upper surface of the gate electrode including the groove.

[0017] Effects of the Invention

[0018] In the power semiconductor device disclosed herein, volume expansion occurs during the process of forming the oxide film on the surface of the gate electrode trench, thereby improving the bonding strength between the gate electrode and the trench via the gate insulating film. As a result, the gate electrode is less likely to break even when stress is applied. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a cross-sectional view of the SiC-MOSFET according to the first embodiment.

[0020] Figure 2 This is a flowchart showing the manufacturing process of the SiC-MOSFET according to the first embodiment.

[0021] Figure 3 This is a cross-sectional view during the manufacture of the SiC-MOSFET according to the first embodiment.

[0022] Figure 4 This is a cross-sectional view during the manufacture of the SiC-MOSFET according to the first embodiment.

[0023] Figure 5 This is a cross-sectional view during the manufacture of the SiC-MOSFET according to the first embodiment.

[0024] Figure 6 This is a cross-sectional view during the manufacture of the SiC-MOSFET according to the first embodiment.

[0025] Figure 7 This is a cross-sectional view during the manufacture of the SiC-MOSFET according to the first embodiment.

[0026] Figure 8 This is a cross-sectional view during the manufacture of the SiC-MOSFET according to the first embodiment.

[0027] Figure 9 This is a cross-sectional view during the manufacture of the SiC-MOSFET according to the first embodiment.

[0028] Figure 10This is a cross-sectional view during the manufacture of the SiC-MOSFET according to the first embodiment.

[0029] Figure 11 This is a cross-sectional view during the manufacture of the SiC-MOSFET according to the first embodiment.

[0030] Figure 12 This is a cross-sectional view during the manufacture of the SiC-MOSFET according to the first embodiment.

[0031] Figure 13 This is a cross-sectional view during the manufacture of the SiC-MOSFET according to the first embodiment.

[0032] Figure 14 This is an enlarged cross-sectional view of the trench gate and its surrounding area of ​​the SiC-MOSFET according to the first embodiment.

[0033] Figure 15 This is a microscope photograph showing a cross section of the SiC-MOSFET according to the first embodiment.

[0034] Figure 16 This is a top view of the SiC-MOSFET according to the first embodiment.

[0035] Figure 17 yes Figure 16 A-A' cross-sectional view.

[0036] Figure 18 This is a diagram showing a semiconductor module according to the first embodiment.

[0037] Figure 19 This is a diagram showing the relationship between the depth of the recess of the gate electrode and the leakage current.

[0038] Figure 20 This is a diagram showing the relationship between the angle of the side surface of the recess of the gate electrode and the leakage current.

[0039] Figure 21 This is a cross-sectional view of a SiC-MOSFET according to the second embodiment.

[0040] Figure 22 This is a cross-sectional view during the manufacture of the SiC-MOSFET according to the second embodiment.

[0041] Figure 23 This is a cross-sectional view during the manufacture of the SiC-MOSFET according to the second embodiment.

[0042] Figure 24 This is an enlarged cross-sectional view of the trench gate and its surrounding area of ​​the SiC-MOSFET according to the second embodiment.

[0043] Figure 25 This is a cross-sectional view of a SiC-MOSFET according to a third embodiment.

[0044] Figure 26 This is a flowchart showing the manufacturing process of the SiC-MOSFET according to the third embodiment.

[0045] Figure 27 This is a flowchart showing the plating process and the plating pre-process in the manufacturing process of the SiC-MOSFET according to the third embodiment.

[0046] Figure 28 This is a cross-sectional view during the manufacture of the semiconductor module according to the third embodiment.

[0047] Figure 29 This is a cross-sectional view of a semiconductor module according to a third embodiment.

[0048] Figure 30 This is a cross-sectional view of a SiC-MOSFET according to a first modified example of the third embodiment.

[0049] Figure 31 This is a cross-sectional view of a SiC-MOSFET according to a second modified example of the third embodiment.

[0050] Figure 32 This is a block diagram showing the configuration of a power conversion system according to a fourth embodiment. DETAILED DESCRIPTION

[0051] <A. Implementation Method 1>

[0052] A-1. Structure

[0053] Figure 1 : is a cross-sectional view showing the cell structure of the main part of SiC-MOSFET 101. SiC-MOSFET 101 is a power semiconductor device according to the first embodiment having a trench gate structure. Figure 1 5 unit structures are shown in FIG, but the number of units of SiC-MOSFET101 is not limited to this. Figure 1 The unit structures shown are continuous in any number in the transverse direction of the paper.

[0054] SiC-MOSFET 101 includes an n-type SiC substrate 1, a drift layer 2 made of n-type SiC, a p-type base region 3, an n-type source region 4, a p-type bottom base region 5, a gate insulating film 6, a gate electrode 7, an oxide film 8, an interlayer insulating film 9, a source electrode 10, and a drain electrode 11. Figure 1 In the figure, the main surface on the upper side of the SiC substrate 1 is referred to as the first main surface (hereinafter also referred to as the “front side”), and the main surface on the lower side of the SiC substrate 1 is referred to as the second main surface (hereinafter also referred to as the “back side”).

[0055] The drift layer 2 is epitaxially grown on the first principal surface of the SiC substrate 1. A base region 3 is selectively formed as a first impurity region on the surface of the drift layer 2. A source region 4 is selectively formed as a second impurity region on the surface of the base region 3. A trench 19 is formed from the surface of the source region 4 to a depth that penetrates the source region 4 and the base region 3 and reaches the drift layer 2. A bottom base region 5 is formed as a third impurity region in the drift layer 2 at the bottom of the trench 19. A gate insulating film 6 is formed on the inner wall of the trench 19. A gate electrode 7 is formed within the trench 19. The upper surface of the gate electrode 7 is covered with an oxide film 8. An interlayer insulating film 9 is formed on top of the oxide film 8 and on top of the source region 4. A source electrode 10 is formed on top of the base region 3, the source region 4, and the interlayer insulating film 9. A drain electrode 11 is formed on the second principal surface of the SiC substrate 1.

[0056] Furthermore, the bottom base region 5 is not limited to being provided in contact with the bottom of the trench 19; it may also be provided separately below the bottom of the trench 19 within the drift layer 2. Furthermore, the bottom base region 5 is not limited to covering the entire bottom of the trench 19; it may be provided so as to cover at least a portion of the bottom of the trench 19. For example, the bottom base region 5 may be periodically arranged at intervals along the extending direction of the trench 19, or may be provided so as to cover approximately half of the bottom of the trench 19 in a cross section perpendicular to the extending direction. Alternatively, the bottom base region 5 may be configured so as to extend in the width direction of the trench 19 to cover the entire bottom, thereby making the width of the bottom base region 5 greater than the width of the trench 19.

[0057] The bottom base region 5 is not limited to being provided along the extending direction of the trench 19 , and may be provided in plurality extending in a direction perpendicular to the extending direction of the trench 19 to periodically cover a portion of the bottom of the trench 19 in the extending direction.

[0058] The bottom base region 5 may be provided within the drift layer 2 and between adjacent trenches 19, parallel to the extending direction of the trenches 19. In this case, the bottom base region 5 is not limited to being provided linearly and continuously, but may be provided periodically at intervals in the extending direction of the trenches 19. The depth of the bottom base region 5 formed from the outermost layer of the drift layer 2 may be the same as the depth of the bottom of the trench 19, or may be shallower or deeper than the depth of the bottom of the trench 19.

[0059] A-2. Manufacturing Process

[0060] Figure 2 Flowchart showing the manufacturing process of SiC-MOSFET101. Figure 2 The manufacturing process of SiC-MOSFET101 is described in the following process. First, prepare n-type SiC substrate 1 (step S1). Then, Figure 3 As shown, a drift layer 2 composed of n-type SiC is formed as an epitaxial film on the front surface of a SiC substrate 1 .

[0061] Next, a mask (not shown) made of a resist or the like is formed on the drift layer 2, and p-type impurities are ion-implanted into the drift layer 2 from the opening of the mask. Figure 4 As shown, a p-type base region 3 is formed on the surface of the drift layer 2 (step S2). The p-type impurity is, for example, boron (B) or aluminum (Al).

[0062] Then, a mask (not shown) made of a resist or the like is formed on the base region 3, and n-type impurities are ion-implanted into the base region 3 from the opening of the mask. Figure 5 As shown, an n-type source region 4 is selectively formed on the surface layer of the base region 3 (step S3). Selectively forming the source region 4 on the surface layer of the base region 3 means that there are portions in the surface layer of the base region 3 where the source region 4 is formed and portions where the source region 4 is not formed. Examples of n-type impurities include phosphorus (P) and nitrogen (N).

[0063] Next, the SiC wafer is heat-treated at a high temperature using a heat treatment apparatus (not shown), thereby electrically activating the p-type impurities and n-type impurities implanted into the base region 3 and the source region 4 .

[0064] Next, a mask (not shown) made of a resist or the like is formed on the surface of the base region 3 and the source region 4. Then, dry etching using plasma or the like is performed. Figure 6 As shown, trench 19 is formed (step S4). If a resist mask thick enough to form trench 19 is not formed, an oxide film made of, for example, TEOS can be formed on the surfaces of base region 3 and source region 4 and dry-etched using the resist mask. This allows deep trench 19 to be formed.

[0065] Then, p-type impurities are ion-implanted into the bottom of the trench 19. Figure 7 As shown, a p-type bottom base region 5 is formed at the bottom of the trench 19. The bottom base region 5 serves to mitigate the electric field at the bottom of the trench gate. Here, the p-type impurity is, for example, boron (B) or aluminum (Al).

[0066] Next, to remove plasma damage caused during trench 19 formation, thermal oxidation is used to oxidize the inner walls of trench 19 and the surfaces of base region 3 and source region 4. The thicker the layer to be oxidized, the more plasma damage can be removed, but the thickness of base region 3 and source region 4 decreases accordingly. Therefore, the thickness of the layer to be oxidized is between 20 nm and 80 nm, and more preferably between 30 nm and 70 nm. The inventors confirmed that the aforementioned oxidation amount sufficiently removed plasma damage on the inner walls of trench 19 by measuring leakage current between gate electrode 7 and source electrode 10.

[0067] Afterwards, if Figure 8 As shown, a gate insulating film 6 is formed on the inner wall of the trench 19 by a deposition method such as chemical vapor growth or a thermal oxidation method (step S5). The gate insulating film 6 is formed on the side and bottom surfaces of the trench 19. The gate insulating film 6 on the bottom surface of the trench 19 has a thickness equal to or greater than that of the gate insulating film 6 on the side surfaces of the trench 19, preferably at least 10% thicker.

[0068] Then, if Figure 9 As shown in FIG. 1 , a gate electrode 7 made of polysilicon is formed on the gate insulating film 6. Then, as shown in FIG. Figure 10 As shown, the remaining gate electrode 7 outside the interior of the trench 19 is removed, and the gate electrode 7 is patterned (step S6). The patterning of the gate electrode 7 is preferably performed using isotropic etching. For example, if dry etching is used, etching using plasma generated by a gas containing sulfur hexafluoride (SF6) is preferably used, and if wet etching is used, etching using a mixed acid containing hydrofluoric acid and nitric acid is preferably used. Through these etching methods, a V-shaped groove 7a can be formed on the upper surface of the gate electrode 7.

[0069] Afterwards, if Figure 11 As shown, an oxide film 8 is formed on the upper surface of the gate electrode 7 including the V-shaped groove 7a by thermal oxidation. The oxidation temperature during the formation of the oxide film 8 is preferably 850°C to 1050°C, more preferably 900°C to 1000°C. The thickness of the oxide film 8 is preferably 10 nm to 40 nm, more preferably 20 nm to 35 nm. By forming the oxide film 8 by thermal oxidation, the polysilicon constituting the gate electrode 7 expands in volume when it is converted into a silicon oxide film. This improves the bonding strength between the gate electrode 7 and the trench 19 via the gate insulating film 6, as will be described in detail later.

[0070] Next, an interlayer insulating film 9 is formed on the base region 3, the source region 4 and the oxide film 8 using CVD (chemical vapor deposition). The interlayer insulating film 9 is then patterned by photolithography and etching. Figure 12As shown, only the interlayer insulating film 9 remains on the oxide film 8 and the source region 4 (step S7). By introducing impurities such as B (boron) or P (phosphorus), the corners of the interlayer insulating film 9 can also be rounded. The material of the interlayer insulating film 9 deposited by the CVD method is, for example, silicon nitride (Si x N y ) or silicon oxide (SiO 2 ). The thickness of the interlayer insulating film 9 is preferably not less than 0.5 μm and not more than 2.0 μm.

[0071] Afterwards, if Figure 13 As shown, a source electrode 10 is formed (step S8). The material of the source electrode 10 is, for example, aluminum, an aluminum alloy composed of aluminum and silicon, or nickel. A barrier metal composed of titanium or a titanium compound such as titanium nitride (TiN) may be appropriately formed between the base region 3 and the source region 4 and the source electrode 10.

[0072] Next, if necessary, the back surface of the SiC substrate 1 is ground with a grinding wheel to thin the SiC substrate 1 (step S9 ).

[0073] Afterwards, a nickel film with a thickness of about 600 nm is formed on the back of the SiC substrate 1 by sputtering or the like as the drain electrode 11 (step S10). In addition, if the outermost surface of the nickel film is oxidized, the wettability with the solder alloy deteriorates, and the bonding state of the semiconductor chip deteriorates. Therefore, it is also possible to form a metal that is difficult to oxidize, such as gold or silver, as a protective film on the surface of the nickel film, and use a laminated film consisting of the nickel film and the protective film as the drain electrode 11. Thus, the process is completed. Figure 1 SiC-MOSFET101 shown.

[0074] A-3. Function

[0075] Figure 14 This is an enlarged cross-sectional view of the trench gate of SiC-MOSFET101 and its surrounding structures. Figure 14 In the figure, the y-axis is taken in the thickness direction of the SiC-MOSFET 101, the z-axis is taken in the width direction of the groove 19, and the x-axis is taken in the direction perpendicular to the yz plane. A V-shaped groove 7a is formed on the upper surface of the gate electrode 7. The groove 7a is formed when the remaining portion of the gate electrode 7 is removed by isotropic etching. The angle of the side of the groove 7a relative to the thickness direction (y direction) of the SiC-MOSFET 101 is θ. Specifically, θ is Figure 14 The angle between the vertical direction (y direction) on the paper and the straight line drawn along the side of the groove 7a is defined as d. Specifically, d is the distance between the midpoint of two points on the upper surface of the gate electrode 7 adjacent to the groove 7a and the bottom of the groove 7a. The depth of the gate electrode 7 is defined as t. Specifically, t is the distance between the midpoint of two points on the upper surface of the gate electrode 7 adjacent to the groove 7a and the bottom of the gate electrode 7.

[0076] By adjusting the injection energy of n-type impurity ions when forming the source region 4, the side surface of the groove 19 connected to the source region 4 becomes a curved shape that bulges outward. The outer side surface of the gate electrode 7 also becomes a curved shape that bulges outward, that is, protrudes, along the shape of the side surface of the groove 19 and the portion facing the source region 4. In other words, the width of the portion of the gate electrode 7 facing the source region 4 increases from the upper surface of the gate electrode 7 toward the depth direction and then decreases again. In other words, the side surface of the gate electrode 7 has a convex portion in the portion facing the source region 4. In this portion, an anchoring effect in the y direction is generated between the gate electrode 7 and the side surface of the groove 19. Therefore, in the thickness direction ( Figure 14 When stress in the negative y-axis direction is applied to the gate electrode 7, the bonding strength between the gate electrode 7 and the trench 19 is significantly improved compared to the case where the outer side surface of the gate electrode 7 is a straight line.

[0077] Furthermore, the gate insulating film 6 on the side surfaces of the gate electrode 7 is formed thicker than the gate insulating film 6 on the bottom surface of the gate electrode 7. The inventors have experimentally confirmed that the amount of protrusion of the gate electrode 7 and the gate insulating film 6 toward the source region 4 increases, thereby improving the bonding strength between the gate electrode 7 and the trench 19.

[0078] Figure 15 This is a microscope photograph showing a cross section of SiC-MOSFET 101 . Figure 16 1 is a top view of SiC-MOSFET 101 . Figure 17 yes Figure 16 A-A' cross-sectional view. Figure 16 As shown, a termination region 12 is provided outside the source electrode 10 , and a termination protection film 13 is provided outside the termination region 12 . A portion of the upper surface of the SiC-MOSFET 101 serves as a gate connection portion 14 .

[0079] Figure 18 A semiconductor module 110 according to Embodiment 1 is shown. Semiconductor module 110 includes SiC-MOSFET 101, lead frames 15 and 17, wires 18, solder 16, and mold resin (not shown). First, lead frame 17 is connected to the front surface of SiC-MOSFET 101 via wires 18. Next, lead frame 15 is connected to the back surface of SiC-MOSFET 101 via solder 16. Afterwards, SiC-MOSFET 101 and lead frames 15 and 17 are sealed with mold resin, completing semiconductor module 110.

[0080] Figure 19The figure shows the relationship between the leakage current and d / t between the gate electrode 7 and the source electrode 10 after the semiconductor module 110 is assembled, when the load when connecting the wire 18 to the SiC-MOSFET 101 is intentionally increased. As described above, d represents the depth of the groove 7a of the gate electrode 7, and t represents the depth of the gate electrode 7. Figure 19 The depth d of the groove 7a is preferably not less than 10% and not more than 70% of the depth t of the gate electrode 7. According to the inventors' analysis, when d is less than 10% of t, the gate electrode 7 is deformed due to the stress when the wire 18 is connected to the SiC-MOSFET 101. Figure 14 Furthermore, it is found that when d exceeds 70% of t, the gate electrode 7 is destroyed starting from the groove 7a due to the stress when the wire 18 is connected to the SiC-MOSFET 101.

[0081] like Figure 18 As shown, the wire 18 is bonded to the upper surface of the SiC-MOSFET 101, that is, in the depth direction of the trench 19 ( Figure 14 The plane perpendicular to the y-axis direction) Figure 14 The direction of line 18 is the same as the depth direction of groove 19 ( Figure 14 y-axis direction) and the width direction of the groove 19 ( Figure 14 z-axis direction) of the plane ( Figure 14 When the yz plane of the line 18 is not parallel, Figure 14 Since a force in the x-axis direction acts on gate electrode 7, the effects of the trench gate structure characteristic of SiC-MOSFET 101 can be obtained. In particular, when the angle formed by line 18 and the depth direction of trench 19 is 60 degrees or less, the effects of the trench gate structure characteristic of SiC-MOSFET 101 can be significantly obtained.

[0082] Figure 20 The relationship between the leakage current and θ between the gate electrode 7 and the source electrode 10 after the semiconductor module 110 is assembled is shown. As described above, θ is the angle between the thickness direction (y direction) of the SiC-MOSFET 101 and the side surface of the groove 7a. Figure 20 , preferably θ is greater than 1 degree and less than 20 degrees. According to the inventor's analysis, it can be confirmed that when θ is less than 1 degree, due to the stress when the wire 18 is connected to the SiC-MOSFET 101, a crack on the gate electrode 7 starts from the groove 7a and moves toward Figure 14 The gate electrode 7 is developed below the paper and is damaged. In addition, it is known that when θ exceeds 20 degrees, the gate electrode 7 is subjected to the stress when the wire 18 is connected to the SiC-MOSFET 101. Figure 14The x-direction in the image is moved and thus destroyed.

[0083] A-4. Effects

[0084] In the above description, the conductivity type of each semiconductor layer of SiC-MOSFET 101 is explicitly set to n-type or p-type. However, the conductivity type of each semiconductor layer can also be reversed. In other words, in the above description, the conductivity type of SiC substrate 1, drift layer 2, and source region 4 is set to n-type, and the conductivity type of base region 3 and bottom base region 5 is set to p-type. However, these conductivity types can also be reversed.

[0085] As described above, the SiC-MOSFET 101 of the first embodiment includes a SiC substrate 1, a drift layer 2 of a first conductivity type formed on the SiC substrate 1, a base region 3, which is a first impurity region of a second conductivity type different from the first conductivity type, formed on the surface of the drift layer, a source region 4, which is a second impurity region of the first conductivity type, formed on the surface of the first impurity region, a trench 19 penetrating the first impurity region and a plurality of second impurity regions and reaching the drift layer 2, a gate electrode 7 embedded in the trench 19 and having a V-shaped groove 7a on its upper surface, and an oxide film 8 formed on the upper surface of the gate electrode 7 including the groove 7a. Therefore, during the formation of the oxide film 8 on the surface of the groove 7a of the gate electrode 7, volume expansion occurs, thereby improving the bonding strength between the gate electrode 7 and the trench 19 via the gate insulating film 6. As a result, the gate electrode 7 is less likely to be damaged even when stress is applied.

[0086] In the method for manufacturing a power semiconductor device according to the first embodiment, a drift layer 2 of a first conductivity type is formed on a SiC substrate 1. A first impurity region, or base region 3, of a second conductivity type different from the first conductivity type is formed on the surface of the drift layer 2. A second impurity region, or source region 4, of the first conductivity type is formed on the surface of the first impurity region. A trench 19 is formed that penetrates the first and second impurity regions and reaches the drift layer 2. A gate electrode 7 having a V-shaped groove 7a on its upper surface is formed within the trench 19. An oxide film 8 is formed on the upper surface of the gate electrode 7, including the groove 7a. Volume expansion occurs during the formation of the oxide film 8 on the surface of the groove 7a in the gate electrode 7, thereby improving the bonding strength between the gate electrode 7 and the trench 19 via the gate insulating film 6. As a result, the gate electrode 7 is less susceptible to damage even when stress is applied.

[0087] <B. Implementation Method 2>

[0088] B-1. Structure

[0089] Figure 211 is a cross-sectional view showing the cell structure of the main part of SiC-MOSFET 102. SiC-MOSFET 102 is a power semiconductor device according to Embodiment 2 having a trench gate structure. Figure 21 5 unit structures are shown in FIG, but the number of units of SiC-MOSFET102 is not limited to this. Figure 21 The unit structures shown are continuous in any number in the transverse direction of the paper.

[0090] In SiC-MOSFET 102, the depth of the base region 3 is not constant, and there are shallow and deep parts between two adjacent gate electrodes 7. The shallow part of the base region 3 is also called the first region, and the deep part is also called the second region. That is, the base region 3 has a first region and a second region that is deeper than the first region. Moreover, in a plan view, the source region 4 overlaps with the entire first region and a portion of the second region. Figure 21 As shown, the second region of the base region 3 is in contact with the bottom base region 5. Apart from the depth of the base region 3, the SiC-MOSFET 102 is identical to the SiC-MOSFET 101.

[0091] B-2. Manufacturing Process

[0092] The manufacturing process of SiC-MOSFET102 is as follows Figure 2 The steps of forming the base region 3 (step S2 ) and the source region 4 (step S3 ) are different from those in the first embodiment, and therefore will be described below.

[0093] A mask (not shown) made of a resist or the like is formed on the drift layer 2, and p-type impurities are ion-implanted into the drift layer 2 from the opening of the mask, thereby forming a p-type base region 3 on the surface of the drift layer 2 (step S2). Figure 22 As shown, two types of base regions 3 , a shallow base region 3 and a deep base region 3 , are formed.

[0094] Then, a mask (not shown) made of a resist or the like is formed over the base region 3, and n-type impurities are ion-implanted into the base region 3 through the openings of the mask, thereby selectively forming an n-type source region 4 on the surface of the base region 3 (step S3). Here, the source region 4 overlaps the entire shallow region and a portion of the deep region of the base region 3 when viewed from above. By forming the source region 4 over a large area so as to also overlap the deep region of the base region 3, the amount of electron injection is increased, thereby reducing the on-resistance.

[0095] Then, similarly to the first embodiment, the base region 3 and the source region 4 are activated to form a trench 19. Figure 23As shown, the bottom base region 5 is formed at the bottom of the trench 19. Then, the gate insulating film 6, the gate electrode 7, the interlayer insulating film 9, the source electrode 10 and the drain electrode 11 are formed in the same manner as in the first embodiment to complete the process. Figure 21 SiC-MOSFET 102 is shown.

[0096] B-3. ​​Effects

[0097] Figure 24 This is an enlarged cross-sectional view of the trench gate and its surrounding structure of the SiC-MOSFET 102. The trench gate structure of the SiC-MOSFET 102 can provide the following effects in addition to the effects of the trench gate structure of the SiC-MOSFET 101.

[0098] In SiC-MOSFET 102 of Embodiment 2, base region 3, serving as a first impurity region, includes a first region and a second region deeper than the first region. Furthermore, source region 4, serving as the second impurity region, overlaps the entire first region and a portion of the second region in a plan view. By forming source region 4 over a wide area so as to also overlap the deep region of base region 3, the amount of electron injection into SiC-MOSFET 102 is increased, reducing on-resistance.

[0099] Furthermore, in SiC-MOSFET 102, the second region of base region 3 is in contact with bottom base region 5, which serves as a third impurity region, on the left side of gate electrode 7. Thus, source electrode 10 and p-type bottom base region 5 are electrically connected via p-type base region 3. Therefore, even when a high electric field is applied to bottom base region 5 by a switch or the like, SiC-MOSFET 102 can reliably be turned on and off.

[0100] <C. Implementation Method 3>

[0101] <C-1. Structure>

[0102] Figure 25 1 is a cross-sectional view showing the cell structure of the main part of SiC-MOSFET 103. SiC-MOSFET 103 is a power semiconductor device according to the third embodiment having a trench gate structure. Figure 25 5 unit structures are shown in FIG, but the number of units of SiC-MOSFET103 is not limited thereto. In practice, Figure 25 The unit structures shown are continuous in any number in the transverse direction of the paper.

[0103] Figure 25 The SiC-MOSFET 103 shown in FIG. Figure 1The SiC-MOSFET 101 shown in FIG. 1 further includes a source electrode 20. However, the SiC-MOSFET 103 may also include a source electrode 20. Figure 21 In addition to the structure of the SiC-MOSFET 102 shown, the SiC-MOSFET 102 further includes a source electrode 20. The source electrode 20 is formed on the source electrode 10. To distinguish between the two, the source electrode 10 is also referred to as a first source electrode, and the source electrode 20 is also referred to as a second source electrode.

[0104] C-2. Manufacturing Process

[0105] Figure 26 Flowchart showing the manufacturing process of SiC-MOSFET103. Figure 2 The manufacturing process of the SiC-MOSFET 101 shown in the figure adds a plating pre-treatment (step S11 ) and a plating treatment (step S12 ).

[0106] Figure 27 is a more detailed representation Figure 26 Flowchart of steps S11 and S12 shown. Figure 26 Step S11 and Figure 27 Steps S21 to S24 are equivalent to, Figure 26 Step S12 and Figure 27 Step S25 is equivalent to step S26.

[0107] When source electrode 10 is made of aluminum alloy, even after undergoing conventional degreasing and pickling, a strong organic residue and oxide film remain on the upper surface of the aluminum alloy. Consequently, even after plating, sufficient metal diffusion between the aluminum alloy and the plating metal does not occur, preventing the formation of a strongly adherent plating layer. Therefore, in step S11, a plating pretreatment is performed on the upper surface of source electrode 10 prior to plating.

[0108] The plating pretreatment is as follows. First, in step S21, a surface activation treatment is performed. The surface activation treatment is performed, for example, using plasma. In particular, plasma cleaning can remove organic residues adhering to the upper surface of the source electrode 10 by plasma oxidation or plasma bombardment, thereby cleaning the upper surface of the source electrode 10. This organic residue cannot be removed by conventional plating pretreatment.

[0109] Next, a degreasing process is performed in step S22 . The degreasing process is performed to remove light organic contamination and an oxide film remaining on the upper surface of the source electrode 10 .

[0110] Then, pickling is performed in step S23. Pickling neutralizes the upper surface of source electrode 10 and roughens it by etching. Pickling improves the reactivity of the treatment solution in the subsequent steps and improves the adhesion of the plated film.

[0111] Next, zincate treatment is performed in step S24. When the source electrode 10 is made of an aluminum alloy, zincate treatment removes the aluminum oxide film on the upper surface of the aluminum alloy and simultaneously forms a zinc (Zn) coating. Specifically, when the aluminum alloy is immersed in an aqueous solution containing zinc dissolved in ions, the standard oxidation-reduction potential of zinc is higher than that of aluminum, causing aluminum to dissolve in the form of ions. The electrons generated at this time cause the zinc ions to accept electrons on the upper surface of the aluminum alloy, forming a zinc coating on the upper surface of the aluminum alloy. Furthermore, the aluminum oxide film is removed at this time.

[0112] The zincate treatment may be performed multiple times. For example, after the first zincate treatment, the zincate formed in the first zincate treatment is stripped off, and then a second zincate treatment is performed.

[0113] Steps S24 to S27 described above are plating pretreatments. Sufficient water rinsing time must be ensured between each step from S24 to S27 to prevent the treatment liquid or residue from the previous step from being carried over to the next step.

[0114] Then, in step S12, a plating process is performed as a wet film forming method. Specifically, an electroless Ni plating layer is first formed in step S25. When the aluminum alloy with a zinc coating is immersed in an electroless Ni plating solution, nickel is first precipitated on the upper surface of the aluminum alloy because the standard redox potential of zinc is lower than that of nickel.

[0115] Next, when the upper surface of the aluminum alloy is covered with nickel, nickel is automatically catalytically deposited under the action of the reducing agent contained in the electroless Ni plating solution. However, during this autocatalytic deposition, the components of the reducing agent are introduced into the electroless Ni plating film, and therefore, the electroless Ni plating film becomes an alloy. In addition, when the concentration of the reducing agent is high, the formed electroless Ni plating film becomes amorphous. In addition, since hypophosphorous acid is generally used as a reducing agent, phosphorus (P) is contained in the electroless Ni plating layer.

[0116] Under these conditions, an electroless Ni plating film having a thickness of 5 μm was formed on the upper surface of source electrode 10 .

[0117] Next, an electroless Au plating layer is formed in step S26. The substitutional electroless Au plating layer is formed on the upper surface of the electroless Ni plating layer, utilizing the substitution of nickel and Au by a complexing agent contained in the plating solution.

[0118] Since the electroless Au plating is a substitutional type, if the surface of the nickel is covered with Au, the reaction stops. Therefore, it is difficult to form the electroless Au plating to be thicker. The thickness of the electroless Au plating is at most 0.1 μm, and is generally around 0.05 μm. However, when used for welding, the thickness of the Au plating will not be too thin even if it is the above-mentioned value. The film composed of the electroless Ni plating and the electroless Au plating formed in this way is the source electrode 20.

[0119] Next, a semiconductor module including the SiC-MOSFET 103 will be described. Figure 28 : is a cross-sectional view showing the manufacturing process of a semiconductor module. Figure 28 As shown in FIG. 1 , the upper and lower surfaces of the SiC-MOSFET 103 are connected to the lead frame 27 using solder 26, respectively. Figure 29 As shown, SiC-MOSFET 103 and a portion of lead frame 27 are sealed with mold resin 22 so that the front end of lead frame 27 is exposed, thereby completing the semiconductor module.

[0120] <C-3. Modification>

[0121] Figure 30 1 is a cross-sectional view showing the cell structure of the main part of a SiC-MOSFET 103A, a power semiconductor device according to a first modification of the third embodiment having a trench gate structure. Figure 30 5 unit structures are shown in FIG, but the number of units of SiC-MOSFET103A is not limited thereto. In practice, Figure 30 The unit structures shown are continuous in any number in the transverse direction of the paper.

[0122] In the SiC-MOSFET 103 , the interlayer insulating film 9 is formed on all gate electrodes 7 via the oxide film 8 . In contrast, in the SiC-MOSFET 103A, the interlayer insulating film 9 is not formed on some gate electrodes 7 .

[0123] The SiC-MOSFET 103A is formed as follows. After the gate electrode 7 is formed, the interlayer insulating film 9 is formed on the base region 3, the source region 4, and the oxide film 8. Then, when the interlayer insulating film 9 is patterned by photolithography and etching, as shown in FIG. Figure 30 As shown, interlayer insulating film 9 remains only on a portion of gate electrode 7 and on source region 4 adjacent to this portion of gate electrode 7. In SiC-MOSFET 103A, only the gate electrode 7 on which interlayer insulating film 9 is formed is used for switching. Therefore, the conduction performance of SiC-MOSFET 103A can be controlled by patterning interlayer insulating film 9.

[0124] Figure 311 is a cross-sectional view showing the cell structure of the main part of a SiC-MOSFET 103B, a power semiconductor device according to a second modification of the third embodiment having a trench gate structure. Figure 31 5 unit structures are shown in FIG, but the number of units of SiC-MOSFET103B is not limited thereto. In practice, Figure 31 The unit structures shown are continuous in any number in the transverse direction of the paper.

[0125] The SiC-MOSFET 103B is obtained by adding a plated drain electrode 21 to the drain electrode 11 in the SiC-MOSFET 103A. In order to distinguish the two, the drain electrode 11 is also referred to as the first drain electrode and the drain electrode 21 is also referred to as the second drain electrode. <c-2>The SiC-MOSFET 103 is formed simultaneously with the source electrode 20 in the manufacturing process described above.

[0126] The source electrode 20 is thicker than the drain electrode 21. The thickness of the source electrode 20 is preferably at least 1.05 times the thickness of the drain electrode 21. When the temperature of the SiC-MOSFET 103 fluctuates due to intermittent power supply such as switching operations, the solder or wire that joins the SiC-MOSFET 103, or the expansion and contraction of the source electrodes 10 and 20 included in the SiC-MOSFET 103, generates compressive and tensile forces (hereinafter referred to as "expansion stress") between the SiC substrate 1 and drift layer 2 composed of SiC and the gate electrode 7 composed of polycrystalline silicon. However, by increasing the film thickness of the source electrode 20 as described above, the expansion and contraction stress acting on the front side of the SiC-MOSFET 103 becomes greater than that on the back side. Therefore, the expansion and contraction stress can be borne not by the bottom of the gate electrode 7, but by the upper portion of the gate electrode 7 and the trench 19, where the bonding strength is significantly improved.

[0127] <D. Implementation Method 4>

[0128] This embodiment applies the power semiconductor device of Embodiments 1-3 to a power conversion device. Application of the power semiconductor device of Embodiments 1-3 is not limited to a specific power conversion device. Below, as Embodiment 4, we describe a case where the power semiconductor device of Embodiments 1-3 is applied to a three-phase inverter.

[0129] Figure 32 This is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0130] Figure 32 The power conversion system shown includes a power supply 100, a power conversion device 200, and a load 300. Power supply 100 is a DC power supply that supplies DC power to power conversion device 200. Power supply 100 can be composed of various components, including, for example, a DC system, a solar cell, or a battery, or a rectifier circuit or AC / DC converter connected to an AC system. Alternatively, power supply 100 can be composed of a DC / DC converter that converts DC power output from the DC system into a specified power level.

[0131] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300. The power conversion device 200 converts the DC power supplied from the power source 100 into AC power and supplies the converted AC power to the load 300. Figure 32 As shown, the power conversion device 200 includes a main conversion circuit 201 and a control circuit 203. The main conversion circuit 201 converts input DC power into AC power and outputs the AC power. The control circuit 203 outputs a control signal to the main conversion circuit 201.

[0132] Load 300 is a three-phase electric motor driven by the AC power supplied from power conversion device 200. Load 300 is not limited to a specific application and may be a motor mounted on various electrical devices, for example, a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioners.

[0133] The following describes the details of the power conversion device 200. The main conversion circuit 201 includes a silicon carbide semiconductor device 202. The silicon carbide semiconductor device 202 comprises a switching element and a freewheeling diode. The main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power through the switching operation of the switching element, and supplies the converted AC power to the load 300. The specific circuit configuration of the main conversion circuit 201 varies. In this embodiment, the main conversion circuit 201 is a two-level three-phase full-bridge circuit, which can be composed of six switching elements and six freewheeling diodes connected in antiparallel with each switching element. The switching elements of the silicon carbide semiconductor device 202 constituting the main conversion circuit 201 employ the power semiconductor device of any of the above-described embodiments 1-3. The six switching elements are connected in series to form upper and lower arms, with each upper and lower arm constituting a phase (U phase, V phase, W phase) of the full-bridge circuit. Furthermore, the output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0134] In addition, the main conversion circuit 201 includes a drive circuit (not shown) that drives each switching element. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203 described later, a drive signal for turning the switching element into an on state and a drive signal for turning the switching element into an off state are output to the control electrode of each switching element. When the switching element is maintained in the on state, the drive signal is a voltage signal (on signal) that is greater than the threshold voltage of the switching element. When the switching element is maintained in the off state, the drive signal is a voltage signal (off signal) that is less than the threshold voltage of the switching element.

[0135] The control circuit 203 controls the switching elements of the main conversion circuit 201 to supply the desired power to the load 300. Specifically, the control circuit 203 calculates the time (on-time) for each switching element of the main conversion circuit 201 to be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by pulse width modulation (PWM) control, which modulates the on-time of the switching element according to the voltage to be output. In addition, the control circuit 203 outputs a control instruction (control signal) to the drive circuit of the main conversion circuit 201 so that at each point in time, an on signal is output to the switching element to be in the on state and an off signal is output to the switching element to be in the off state. In accordance with the control signal, the drive circuit outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0136] According to this embodiment, the silicon carbide semiconductor device 202 is used as at least one of the semiconductor devices constituting the main conversion circuit 201. This prevents dielectric breakdown caused by displacement of the gate electrode 7 even when stress is applied. This improves the reliability of the main conversion circuit 201 and, consequently, the power conversion device 200.

[0137] Furthermore, while this embodiment describes an example in which the present disclosure is applied to a two-level, three-phase inverter, the present disclosure is not limited thereto and can be applied to various power conversion devices. In this embodiment, the power conversion device is a two-level power conversion device, but a multi-level power conversion device such as a three-level power conversion device may also be used. Furthermore, when supplying power to a single-phase load, the present disclosure can also be applied to a single-phase inverter. Furthermore, when supplying power to a DC load, etc., the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0138] In addition, the power conversion device to which the present invention is applied is not limited to the case where the above-mentioned load is an electric motor. For example, it can also be used as a power supply device for any one of an electric discharge machine, a laser processing machine, an induction heating cooker, and a contactless power supply system, and can also be used as a power conditioner for a solar power generation system or a power storage system.

[0139] The present disclosure can freely combine the various embodiments within the scope of its disclosure, or appropriately modify or omit the various embodiments. The above description is illustrative in all respects and is not restrictive. Countless variations not illustrated can be envisioned without departing from the scope of this disclosure.

[0140] Description of Reference Numerals

[0141] 1SiC substrate; 2drift layer; 3base region; 4source region; 5bottom base region; 6gate insulating film; 7gate electrode; 7a-groove; 8oxide film; 9interlayer insulating film; 10source electrode; 11drain electrode; 12terminal region; 13terminal protection film; 14gate connection portion; 15, 17lead frames; 16solder; 18wire; 19trench; 100power supply; 110semiconductor module; 200power conversion device; 201main conversion circuit; 202silicon carbide semiconductor device; 203control circuit; 300load.

Claims

1. A power semiconductor device, wherein: have: SiC substrate; a drift layer formed on the SiC substrate and having a first conductivity type; a first impurity region formed in a surface layer of the drift layer and having a second conductivity type different from the first conductivity type; a second impurity region selectively formed on a surface layer of the first impurity region and having the first conductivity type; a trench penetrating the first impurity region and the second impurity region and reaching the drift layer; a gate electrode embedded in the trench and having a sharp V-shaped groove on its upper surface; as well as an oxide film formed on the upper surface of the gate electrode including the groove by a thermal oxidation method, The bottom of the V-shaped groove is deeper than the first impurity region.

2. The power semiconductor device according to claim 1, wherein The gate electrode is made of polysilicon, The oxide film is a silicon oxide film.

3. The power semiconductor device according to claim 1 or 2, wherein: When the height of the gate electrode is defined as the distance from the midpoint of two locations on the upper surface of the gate electrode adjacent to both ends of the groove to the bottom of the gate electrode, the depth of the groove is greater than or equal to 10% and less than or equal to 70% of the height of the gate electrode.

4. The power semiconductor device according to claim 1 or 2, wherein: An angle of a side surface of the groove of the gate electrode with respect to a thickness direction of the power semiconductor device is greater than or equal to 1 degree and less than or equal to 20 degrees.

5. The power semiconductor device according to claim 1 or 2, wherein: The side surface of the gate electrode has a protrusion at a position facing the second impurity region.

6. The power semiconductor device according to claim 1 or 2, wherein: The first impurity region includes a first region and a second region deeper than the first region. The second impurity region overlaps with the entire first region and a portion of the second region in a plan view.

7. The power semiconductor device according to claim 6, wherein: further comprising a third impurity region of the second conductivity type provided below the trench, The second region of the first impurity region is in contact with the third impurity region.

8. The power semiconductor device according to claim 1 or 2, wherein: The upper surface of the gate electrode other than the V-shaped groove is inclined downward from the end of the gate electrode to the boundary with the V-shaped groove, and its inclination angle relative to the width direction of the groove continuously decreases from the end of the gate electrode to the boundary with the V-shaped groove.

9. The power semiconductor device according to claim 5, wherein The side surface of the gate electrode includes a first side surface and a second side surface which is a side surface opposite to the first side surface. The first side surface of the gate electrode faces the second impurity region and has the convex portion. The second side surface of the gate electrode is in contact with the first impurity region and does not have the protrusion.

10. The power semiconductor device according to claim 1 or 2, wherein: further comprising an upper surface electrode covering the first impurity region and the second impurity region, The upper surface electrode comprises: a first upper surface electrode formed on upper surfaces of the first impurity region and the second impurity region; and A second upper surface electrode is formed on the first upper surface electrode.

11. A method for manufacturing a power semiconductor device, wherein: forming a first conductivity type drift layer on a SiC substrate, forming a first impurity region of a second conductivity type different from the first conductivity type on a surface layer of the drift layer; selectively forming a second impurity region of the first conductivity type on a surface layer of the first impurity region, forming a trench penetrating the first impurity region and the second impurity region and reaching the drift layer; A gate electrode having a sharp V-shaped groove on its upper surface is formed in the trench, and an oxide film is formed on the upper surface of the gate electrode including the groove by thermal oxidation.

12. A power conversion device, wherein: have: A conversion circuit comprising the power semiconductor device according to any one of claims 1 to 10, which converts input power and outputs the converted power; a drive circuit that outputs a drive signal for driving the power semiconductor device to the power semiconductor device; as well as A control circuit outputs a control signal for controlling the drive circuit to the drive circuit.

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