Pixel circuit and method for vision sensor

Abstract

A pixel circuit for use in an image sensor is provided. The pixel circuit includes a photosensitive element configured to generate a current signal in response to a brightness of light impinging on the photosensitive element, and a converter configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal. The pixel circuit further includes a capacitor electrically coupled in series to the converter and configured to receive the voltage signal from the converter, and an amplifier electrically coupled in series to the capacitor at an input and configured to generate an amplified signal at an output based on an output signal from the capacitor, wherein there is no feedback between the output and the input of the amplifier. In addition, the pixel circuit includes a reset device configured to reset the amplifier in response to a generation of a trigger signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 004,110, filed April 2, 2020, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure generally relates to the field of sensors and pixel circuitry for sensing. More specifically, but not limitingly, this disclosure relates to systems and methods for providing pixel circuitry and architectures, as well as for implementing and using vision sensors with pixel circuitry. The sensors and techniques disclosed herein can be used in a variety of applications and vision systems, such as security systems, autonomous vehicles, and other systems that benefit from rapid and efficient motion detection and / or motion event-driven data acquisition. Background Technology

[0004] Existing image sensors use multiple pixels, including semiconductor charge-coupled devices (CCDs), complementary metal-oxide-semiconductor (CMOS) sensors, N-type metal-oxide-semiconductor (NMOS) sensors, or other sensors, to capture digital images of a scene. However, conventional image sensors are slow at detecting fast motion because each frame is captured as a complete image of the scene. Furthermore, such image sensors generate a large amount of data, exponentially increasing the amount of processing required, for example, to sift out motion information from the captured images.

[0005] Many systems do not require the extensive detail provided by existing image sensors that capture complete images. For example, security and other surveillance systems may only be interested in motion data and not in the non-motion portions of the image. As another example, autonomous vehicles must process captured data quickly and efficiently to make decisions comparable to human perception time (typically around 100 milliseconds or less). Such efficiency has an upper limit when large amounts of data must be discarded (e.g., via post-processing) to obtain the situation-relevant portions of the captured data. Summary of the Invention

[0006] Embodiments of the present disclosure can provide a sensor comprising a plurality of pixels. Each pixel comprises: a photosensitive element configured to generate a current signal in response to a brightness of light impinging on the photosensitive element; a transducer configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal; a capacitor electrically coupled in series to the transducer and configured to receive the voltage signal from the transducer; an amplifier electrically coupled in series to the capacitor at an input and configured to generate an amplified signal at an output based on an output signal from the capacitor, wherein there is no feedback between the output and the input of the amplifier; and a reset device electrically coupled between the input and the output of the amplifier and configured to reset the amplifier in response to generating a trigger signal.

[0007] In some embodiments, the sensor comprises at least one time-contrast sensor, also referred to as a contrast detection sensor or a dynamic vision sensor. Further, the amplifier can have a defined gain, and in some embodiments, the amplifier comprises a control gain amplifier. In some embodiments, the gain of the amplifier can be controllable or adjustable, and in other embodiments, the gain of the amplifier is not controllable or adjustable. In some embodiments, the gain of the amplifier can be defined by a number of stacked transistors of the amplifier, which number is not adjustable. In other embodiments, the gain of the amplifier can be controlled by switching the stacked transistors on or off. In some embodiments, the gain of the amplifier can be controlled by switching the amplifier stage on or off, as disclosed herein.

[0008] As disclosed herein, embodiments of the amplifier can comprise a control gain amplifier. The control gain amplifier can comprise a plurality of stacked transistors. In some embodiments, the plurality of stacked transistors comprises a transistor, and a gate of the transistor is electrically coupled to a drain or a source of the transistor. One or more of such transistors can be used to implement the plurality of stacked transistors.

[0009] In some embodiments, the open loop gain of the amplifier is associated with a value related to a number of stacked transistors. As an example, in some embodiments, the gain of the amplifier is less than 10. In other embodiments, the gain is equal to or greater than 10. In other embodiments, the gain of the amplifier is equal to or greater than 20 and equal to or less than 40. In yet other embodiments, the gain of the amplifier is less than 100. Further, in some embodiments, the amplifier is implemented as a multi-stage amplifier, as disclosed herein.

[0010] In some embodiments, the pixel further comprises a comparator electrically coupled to the output of the amplifier and configured to generate the trigger signal upon a match condition of the amplified signal. In some embodiments, the condition comprises an amplitude of the amplified signal being greater than or equal to a threshold value.

[0011] In some embodiments, the reset device includes a switch. As disclosed herein, the reset device can be configured to reset the voltage between the input and the output of the amplifier by closing the switch. The reset device can be further configured to reset the amplifier by setting the voltage between the input and the output of the amplifier to zero.

[0012] In some embodiments, the pixel further includes a comparator electrically coupled to the output of the amplifier and configured to generate a trigger signal upon a match condition of the amplified signal. In some embodiments, the comparator is configured to output the trigger signal to an external readout system. The external readout system can be configured to send an acknowledgement signal to the pixel in response to the trigger signal. In some embodiments, the reset device can be configured to reset the amplifier in response to receipt of the acknowledgement signal. In other embodiments, the reset device can be configured to reset the amplifier after providing the trigger signal as output to the external readout system. That is, the pixel does not need to receive an acknowledgement signal from the external readout system to reset itself.

[0013] According to embodiments of the disclosure, each pixel can further include: another capacitor electrically coupled in series between the output of the amplifier and the input of the comparator; and another reset device electrically coupled between the input of the comparator and a reference signal and configured to set the reference signal as the input of the comparator. In some embodiments, the other reset device includes another switch. In some embodiments, the other reset device is further configured to set the reference signal as the input of the comparator by closing the other switch. In some embodiments, the reset device includes a switch different from the other switch of the other reset device.

[0014] In some embodiments, the reference signal includes a reference voltage.

[0015] According to embodiments of the disclosure, each pixel can further include a delay circuit electrically coupled between the switch and the other switch and configured to set a time delay between operating the switch and the other switch (e.g., a time delay between operating the first switch and the second switch). As will be appreciated from the disclosure, the number of switches is not limited to the examples provided herein.

[0016] Embodiments of the present disclosure can also provide a pixel circuit for use in a vision sensor. The pixel circuit can include a photosensitive element configured to generate a current signal in response to a brightness of light impinging on the photosensitive element; a transducer configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal; a capacitor electrically coupled in series to the transducer and configured to receive the voltage signal from the transducer; an amplifier electrically coupled in series to the first capacitor at an input and configured to generate an amplified signal at an output based on an output signal from the capacitor, wherein there is no feedback between the output and the input of the amplifier; and a reset device electrically coupled between the input and the output of the amplifier and configured to reset the amplifier upon generation of a trigger signal.

[0017] Embodiments of the present disclosure can also provide a method for controlling a sensor having a plurality of pixels. The method includes receiving a current signal in response to light impinging on a photosensitive element; converting the current signal to a voltage signal based on the current signal; generating, by a capacitor, a decoupled voltage signal based on the voltage signal, wherein the decoupled voltage signal is decoupled from the current signal; generating, by an amplifier, an amplified signal based on the decoupled voltage signal, wherein there is no capacitive feedback between the amplified signal and the decoupled voltage signal; generating a trigger signal when the amplified signal matches a condition; and resetting the amplifier upon generation of the trigger signal. BRIEF DESCRIPTION OF DRAWINGS

[0018] The accompanying drawings, which constitute a part of this specification, illustrate various embodiments and together with the description help to explain the principles and features of the disclosed embodiments. In the drawings:

[0019] FIG. 1A is a schematic representation of an exemplary superpixel according to embodiments of the present disclosure.

[0020] FIG. 1B is a schematic representation of another exemplary superpixel according to embodiments of the present disclosure.

[0021] FIG. 1C is a schematic representation of yet another exemplary superpixel according to embodiments of the present disclosure.

[0022] FIG. 1D is a schematic representation of still another exemplary superpixel according to embodiments of the present disclosure.

[0023] FIG. 2 is a schematic representation of an exemplary pixel circuit according to embodiments of the present disclosure.

[0024] FIG. 3 is a schematic representation of another exemplary pixel circuit according to embodiments of the present disclosure.

[0025] FIG. 4A is a schematic representation of an exemplary amplifier according to embodiments of the present disclosure.

[0026] FIG. 4B is a schematic representation of another exemplary amplifier according to embodiments of the present disclosure.

[0027] FIG. 4C is a schematic representation of an exemplary amplifier with adjustable open loop gain according to embodiments of the present disclosure.

[0028] FIG. 4D is a schematic representation of yet another exemplary amplifier with adjustable open loop gain according to embodiments of the present disclosure.

[0029] FIG. 4E is a schematic representation of an exemplary amplifier with adjustable amplifier stage according to embodiments of the present disclosure.

[0030] FIG. 5 is a schematic representation of an exemplary pixel circuit according to embodiments of the present disclosure. FIG. 3 is an example signal timing diagram for a pixel circuit of

[0031] FIG. 6 is a flowchart of an exemplary method for controlling an image sensor according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0032] The disclosed embodiments relate to systems and methods for visual sensing, including asynchronous time-based sensing. The disclosed embodiments also relate to pixels and pixel circuits, as well as implementing and using visual sensors having such pixels and pixel circuits. Advantageously, exemplary embodiments can provide fast and efficient sensing. Other advantages of the present embodiments include the ability to optimally use advanced semiconductor manufacturing process technology to implement visual sensors with competitive pixel size. Furthermore, embodiments of the present disclosure can be implemented and used in a variety of applications and vision systems, such as security systems, autonomous vehicles, and other systems that benefit from fast and efficient motion or event detection. Although embodiments of the present disclosure are generally described with reference to vision systems, it should be understood that such systems can be part of a camera, lidar, or other sensor system.

[0033] In existing image or video processing systems, an image sensor can acquire and process visual information in order to reconstruct an image. An image or video acquisition and processing system can include an array of photosensors, each of which can acquire visual information in order to reconstruct an image representation of a visual scene. This process can repeat at a predetermined rate.

[0034] Event-based vision sensors can detect temporal contrast exceeding a preset relative threshold on a single pixel basis to follow the temporal evolution of relative light changes (contrast detection, CD; temporal contrast, TC) and define sampling points of absolute intensity frameless pixel-level measurements (exposure measurements, EM). Vision sensors are increasingly popular in high-speed low-power machine vision applications due to the temporal precision of recorded data, the inherent suppression of temporal redundancies leading to reduced post-processing costs, and the wide in-scene dynamic range operation. Information about temporal contrast (TC) can be encoded in the form of "events": data packets containing the X, Y coordinates of the original pixel, a timestamp, and the polarity of the contrast. To benefit the most from the ability of single pixels to sample visual information with high temporal precision, early time stamping and high readout throughput can be critical to preserving event times.

[0035] In some embodiments, for real-time artificial vision (also known as "computer vision" or "machine vision"), a vision acquisition and processing system can be configured to acquire and process only data representing changes in current visual information relative to previously acquired visual information. Such sensors or vision systems can not generate frames of images. Such vision sensors can include, for example, temporal contrast (TC) sensors, also known as contrast detection (CD) sensors, or dynamic vision sensors (DVS). Such sensors are referred to as "event-based vision sensors" or generally as "vision sensors" in this disclosure.

[0036] For example, a TC sensor does not record images in frames like existing image systems. Instead, each pixel of a TC sensor can determine the time derivative of the light it senses. In some embodiments, optionally, the pixel can also perform some processing on the time derivative. When the time derivative exceeds a preset threshold, the pixel can generate an "event" by outputting a signal. Through a short delay, the pixel can further transmit data related to the event. In some embodiments, the transmitted data can include the location (e.g., x and y coordinates) of the pixel within the TC sensor (e.g., having a two-dimensional matrix of pixels). In some embodiments, the transmitted data can include a sign bit representing the polarity (e.g., positive or negative) of the time evolution of the light intensity sensed by the pixel. In some embodiments, the transmitted data can include a timestamp of the occurrence of the event. In some embodiments, the transmitted data of a pixel can include a stream of (x, y, s) values, where x and y represent the coordinates of the pixel and s represents the polarity. The value of s can represent the relative change in light intensity detected by the pixel, where the value of s can represent the magnitude of the change and the sign of s can represent the direction of the change (e.g., increasing or decreasing). In some embodiments, the pixel circuitry of a TC sensor can operate asynchronously, where the pixel circuitry of a TC sensor is typically not quantized to a time base (e.g., not clocked). In other embodiments, the pixel circuitry of a TC sensor can operate synchronously, where the pixel circuitry of a TC sensor is quantized to a time base (e.g., clocked).

[0037] As noted above, a vision sensor can include a temporal contrast (TC) sensor, also referred to as a contrast detection (CD) sensor, or a dynamic vision sensor (DVS). A vision sensor can be implemented in many different ways, including with or without an exposure measurement (EM) and with or without other operations or components, including an analog-to-digital converter (ADC). The number of components can also vary (e.g., one versus multiple EMs), and the location of the components can also vary (e.g., in the pixel versus external). Furthermore, the components can operate asynchronously or synchronously, or have a combination of both. The specific arrangement and type of operations will typically depend on the application and requirements of the vision sensor.

[0038] Embodiments of the present invention provide pixel circuitry and features that can be advantageously used in any vision sensor. As an example and not a limitation, a vision sensor implemented with a TC sensor having a two-dimensional matrix of pixels can incorporate embodiments of the present invention and their related features. As yet another example, a vision sensor using superpixels can incorporate embodiments of the present invention and their related features. Reference is made to the following FIGS. 1A-1D An example superpixel is described. It should be understood that the following description of a superpixel is merely exemplary, and other forms of vision sensors can be used with embodiments of the present invention. Indeed, as noted above, embodiments of the present invention can be advantageously incorporated into any type of vision sensor.

[0039] FIG. 1A is a schematic representation of an exemplary super-pixel 100A according to embodiments of the present disclosure. In some embodiments, a super-pixel can be larger or include more components than a regular “pixel” because a super-pixel can include two or more light-sensitive elements (e.g., elements 101 and 103), as well as a condition detector 105, an ADC 109, and control and communication logic such as 111, 113.

[0040] A light-sensitive element can include a photodiode (e.g., a p-n junction or a PIN structure) or any other element configured to convert light into an electrical signal. Each photodiode (e.g., element 101 or element 103) can generate an electrical current (e.g., I ph ) based on the intensity of light impinging on the photodiode. For example, the electrical current I ph is generated in proportion to the intensity of light impinging on the photodiode.

[0041] As shown in the example of FIG. 1A , a super-pixel includes a synchronous unit 100a and an asynchronous unit 100b. The asynchronous unit 100b can include a light-sensitive element 101 (PD CD , e.g., a photodiode), and the synchronous unit 100a can include at least one light-sensitive element 103 (PD EM , e.g., a photodiode).

[0042] The asynchronous unit 100b can also include a condition detector 105 (CD). As shown in the example of FIG. 1A , the detector 105 is electrically connected to the first light-sensitive element 101 (PD CD ) and is configured to generate a trigger signal (labeled “set” in the example of FIG. 1A ) when the analog signal brightness of light impinging on the first light-sensitive element 101 matches a condition. For example, the condition can include whether the analog signal exceeds a threshold (e.g., a voltage level or a current level). The analog signal can include a voltage signal or a current signal.

[0043] The synchronous unit 100a can include an exposure measurement sub-pixel 107. The exposure measurement sub-pixel 107 can be configured to generate an analog measurement based on the brightness of light impinging on the second light-sensitive element 103 (PD EM ). Although depicted as a voltage signal V FD in FIG. 1A , the analog measurement can instead include a current signal. The synchronous unit 100a can also include an ADC 109 for converting the analog measurement to digital data (labeled “digital” in FIG. 1AIn the example, the analog-to-digital converter (ADC) 109 is labeled "digital pixel data". The combination of the exposure measurement sub-pixel 107 and the ADC 109 can be referred to as the "exposure measurement circuit". Therefore, the exposure measurement circuit can be electrically connected to the second photosensitive element 103 (PD). EM It is configured to convert an analog signal based on the brightness of light striking the second photosensitive element 103 into a digital signal. Unlike the asynchronous unit 100b, which outputs based on conditions detected by the condition detector CD, the synchronous unit 100a can be clock-controlled, for example, such that digital data is output from the ADC only according to the clock cycle. In some embodiments, the exposure measurement sub-pixel 107 can also be clock-controlled, such that digital data from the second photosensitive element 103 (PD) is output only according to the clock cycle. EM The signal is converted into an analog signal.

[0044] like FIG. 1A Furthermore, it is shown that after a condition is detected, the condition detector 105 (CD) can transmit the signal (in...) FIG. 1A In the example marked "Settings", the settings are sent to control logic 111, which forms part of asynchronous unit 100b. Control logic 111 can trigger a switch (not shown) and / or logic gate 113 (in...). FIG. 1A In the example, it is depicted as an "or" gate to enable the ADC 109 (or to "power it on"), as shown in [the example]. FIG. 1A (As depicted in the example). As used herein, "enabled" can refer to activation, enabling the ADC 109 to perform conversions using incoming ADC control signals, ramp codes, etc. Therefore, ADC control signals, ramp codes, etc., can be continuously input into the ADC 109 for use after being enabled.

[0045] The combination of control logic 111 and switches (not shown) and / or logic gates 113 can be referred to as a "logic circuit". Therefore, the logic circuit can be electrically connected to detector 105 and exposure measurement circuitry, and is configured to respond to a trigger signal (in... FIG. 1A In the example, the exposure measurement circuit (or specifically, the ADC 109 of the exposure measurement circuit) is enabled (labeled "Setting") and disabled when a digital signal (labeled "Digital Pixel Data") is read from the exposure measurement circuit. In some embodiments, the logic circuit may temporarily enable the exposure measurement circuit (or specifically, the ADC 109 of the exposure measurement circuit) such that the exposure measurement circuit (or specifically, the ADC 109 of the exposure measurement circuit) is automatically disabled after the digital signal is output.

[0046] Therefore, after reading the digital data to an external readout system (not shown), the ADC 109 can generate a reset signal (in... FIG. 1Athe example of FIG. 1 1 1 is labeled "clear"). Thus, the control logic 1 1 1 can trigger a switch (not shown) and / or logic gate 1 13 to disable the ADC 109 (or to "power down" it, as in the example of FIG. 1 1 1 ). As used herein, "disable" can refer to de-activate such that the ADC 109 performs a conversion using the incoming ADC control signals, ramp codes, etc. However, after being disabled, the ADC control signals, ramp codes, etc. can still be input into the ADC 109. FIG. 1A

[0047] In some embodiments, the logic circuit of the control logic 1 1 1 can temporarily enable the sync cell 100a (or particularly, the ADC 109 of the sync cell 100a) such that the sync cell 100a (or particularly, the ADC 109 of the sync cell 100a) is automatically disabled after outputting the digital signal. For example, the reset signal (labeled "clear" in the example of FIG. 1 1 1 ) can be sent from the ADC 109 to the logic circuit of the control logic 1 1 1 after being enabled by the logic circuit in response to the trigger signal (labeled "set" in the example of FIG. 1 1 1 ) such that the logic circuit is ready to receive a new "set" signal from the condition detector 105. FIG. 1A FIG. 1A

[0048] As shown in the example of FIG. 1 1 1, the condition detector 105 (CD) can be coupled to the control logic 1 1 1. The condition detector 105 (CD) can be configured to detect a condition (e.g., a change in the intensity of the light received by the exposure measurement sub-pixel 107) and generate a trigger signal (labeled "trigger" in the example of FIG. 1 1 1 ) to the control logic 1 1 1. The control logic 1 1 1 can be configured to receive the trigger signal and generate a reset signal (labeled "clear" in the example of FIG. 1 1 1 ) to the ADC 109. The reset signal can be used to reset the ADC 109 such that the ADC 109 is ready to perform a conversion. FIG. 1A Further shown, the condition detector 105 (CD) can communicate a trigger signal to an external readout system (shown as "Req" in the example of FIG. 1 1 1 ). The condition detector 105 (CD) can receive an acknowledgement signal (shown as "Ack" in the example of FIG. 1 1 1 ) which is then used to reset the condition detector 105 (CD) such that the condition can be detected again and a trigger generated. In some embodiments, the external readout system can also send control signals to the exposure measurement sub-pixel 107 and / or the ADC 109. All communications with the external readout system can be managed by a protocol such as an address event representation (AER) protocol and / or can be managed by a clock cycle. Thus, the external readout system can comprise an event readout system configured to read data from the super-pixel asynchronously, and / or can comprise a clocked readout system configured to read data from the super-pixel during a predetermined clock cycle. FIG. 1A FIG. 1A As shown in the example of FIG. 1 1 1, the condition detector 105 (CD) can be coupled to the control logic 1 1 1. The condition detector 105 (CD) can be configured to detect a condition (e.g., a change in the intensity of the light received by the exposure measurement sub-pixel 107) and generate a trigger signal (labeled "trigger" in the example of FIG. 1 1 1 ) to the control logic 1 1 1. The control logic 1 1 1 can be configured to receive the trigger signal and generate a reset signal (labeled "clear" in the example of FIG. 1 1 1 ) to the ADC 109. The reset signal can be used to reset the ADC 109 such that the ADC 109 is ready to perform a conversion.

[0049] As shown in the example of FIG. 1 1 1, the condition detector 105 (CD) can be coupled to the control logic 1 1 1. The condition detector 105 (CD) can be configured to detect a condition (e.g., a change in the intensity of the light received by the exposure measurement sub-pixel 107) and generate a trigger signal (labeled "trigger" in the example of FIG. 1 1 1 ) to the control logic 1 1 1. The control logic 1 1 1 can be configured to receive the trigger signal and generate a reset signal (labeled "clear" in the example of FIG. 1 1 1 ) to the ADC 109. The reset signal can be used to reset the ADC 109 such that the ADC 109 is ready to perform a conversion. FIG. 1B ​​​​Further shown, external control can also be provided to the switch (not shown) and / or logic gate 113 (or to control logic 111) to activate the readout. For example, if the superpixel 100A does not return a readout after a threshold number of clock cycles (e.g., if the condition is not met after a threshold number of clock cycles), the external readout system can send a control signal to force a readout. Additionally or alternatively, the external readout system can operate in a standard frame mode such that the superpixel or at least a group of superpixels (e.g., superpixel 100A) are triggered to capture a full or partial frame regardless of whether the condition is detected.

[0050] FIG. 1B is another exemplary superpixel 100B according to embodiments of the present disclosure. FIG. 1A The superpixel 100B of FIG. 1B functions similarly to the superpixel 100A of EM ) and an OR gate 113 in the control circuit. Thus, by using an external control signal applied to the switch 115, the ADC 109 can be disabled whenever the FIG. 1C The superpixel 100B of

[0051] FIG. 1C depicts yet another exemplary superpixel 100C according to embodiments of the present disclosure. FIG. 1A The superpixel 100C of FIG. 1C functions similarly to the superpixel 100A of FIG. 1C although depicted as having three exposure measurement subpixels, the embodiment depicted in FIG. 1D may be implemented with any number of subpixels paired with an ADC 109. Thus, Embodiments of the present disclosure can allow for more accurate data to be captured, for example, by first averaging, summing, or otherwise combining measurements from multiple exposure measurement subpixels before converting the combined measurements to a digital signal. Additionally or alternatively, measurements from multiple exposure measurement subpixels can be converted to a digital signal in sequence to achieve higher resolution.

[0052] FIG. 1D depicts yet another exemplary superpixel 100D according to embodiments of the present disclosure. FIG. 1C The superpixel 100D of FIG. 3The superpixel 100C functions similarly, but also includes latch 115. Latch 115 may include, for example, a switch (e.g., one or more transistors configured to act as switches), one or more bits of static random access memory (SRAM), etc. Although depicted separately from ADC 109, in some embodiments, latch 115 may include at least one of the n-bit latches disposed in ADC 109 (e.g., as described below regarding...). FIG. 1D (As described in A's ADC 300).

[0053] In one implementation, the trigger signal (in) FIG. 1D (In the example marked "Setting") can cause control logic 111 to activate during the first cycle N-1. In response, control logic 111 can send an enable signal to ADC 109 (in... FIG. 1D (In the example, labeled "Power On"). In response, ADC 109 may begin conversion of analog signals from one or more exposure measurement sub-pixels (e.g., sub-pixels 107a, 107b, and 107c) in the second cycle N. Additionally, ADC 109 may set latch 115 and send a signal to control logic 111 at or before the start of cycle N (in... FIG. 1D (In the example marked "clear"), this makes control logic 111 ready to generate a new trigger signal at any time during cycle N. Therefore, a new exposure / transition becomes possible in the third cycle N+1, as depicted in the example of Figure 12 and explained further below. Latch 115 is further connected to the readout system (e.g., via...). FIG. 1D The "digital pixel data" bus depicted in the diagram is used to signal the readout system to perform readout at the end of cycle N. Therefore, when the readout system extracts the digital signal from the ADC 109 at the end of cycle N, the latch 115 can be cleared by the ADC 109.

[0054] In another implementation, control logic 111 can activate latch 115 instead of sending a "power-up" signal to ADC 109. In such implementations, at the beginning of each cycle, ADC 109 can poll the state of latch 115 to determine whether to perform a conversion in that cycle. In implementations where ADC 109 is disabled instead of continuously operating, if latch 115 is not activated at the beginning of a cycle, ADC 109 can be disabled for that cycle. If ADC 109 polls latch 115 and latch 115 is enabled, ADC 109 can clear latch 115 and begin a conversion of the analog signal from one or more exposure measurement sub-pixels (e.g., sub-pixels 107a, 107b, and 107c). In such implementations, ADC 109 can further set an internal status bit to notify the readout system to perform a readout at the end of the cycle. After readout, ADC 109 can disable itself and again poll latch 115 at the beginning of the next cycle to determine whether to re-enable for another cycle. Alternatively, ADC 109 can poll latch 115 before disabling to determine whether to remain enabled for another conversion or to disable.

[0055] In another implementation (not depicted in FIG. 1), latch 115 can be external to super-pixel 100D. In such implementations, super-pixel 100D can not include control logic 111. Instead, detector 105 can activate latch 115 in response to a condition being met, and ADC 109 can continuously perform a conversion at each cycle. Thus, the readout system can use latch 115 to determine whether to perform a readout at the end of each cycle. Otherwise, the conversion performed by ADC 109 can be deleted without a readout. Although such implementations use additional power at each ADC cycle, super-pixel 100D can be made smaller by eliminating control logic 111 and using a smaller array of external latches, such as latch 115. FIG. 1D In implementations where latch 115 is external to super-pixel 100D, latch 115 can be connected to super-pixel 100D using at least one of a direct wired connection or one or more arbiters. For example, latch 115 can form part of an external latch array, such that one or more arbiters can associate a memory address of latch 115 with an address of a corresponding super-pixel (e.g., super-pixel 100D).

[0056] Although depicted as having three exposure measurement sub-pixels (e.g., sub-pixels 107a, 107b, and 107c), the implementations depicted in FIG. 1 can be implemented with any number of sub-pixels paired with ADC 109, e.g., one sub-pixel, two sub-pixels, four sub-pixels, etc.

[0057] FIG. 1A Although depicted as having three exposure measurement sub-pixels (e.g., sub-pixels 107a, 107b, and 107c), the implementations depicted in FIG. 1 can be implemented with any number of sub-pixels paired with ADC 109, e.g., one sub-pixel, two sub-pixels, four sub-pixels, etc.​

[0058] FIG. 1B 、 FIG. 1C 、 FIG. 1D and FIGS. 1A-1D Exemplary superpixels 100A, 100B, 100C, and 100D of FIGS. 1A-1D can be arranged in one or more arrays to form one or more vision sensors, respectively. For example, a vision sensor can include a plurality of superpixels arranged in one or more rows and one or more columns with respective row and column clock circuitry to read out digital data from the ADCs to an external readout system. In another example, superpixels can be arranged in a star pattern with clock circuitry for each node of the star to read out digital data from the ADCs to an external readout system.

[0059] Existing pixel circuits for vision sensors can be implemented with a switched capacitor amplifier for amplifying a detected signal. A switched capacitor amplifier can include a high gain amplifier (e.g., with a gain of hundreds or thousands) electrically connected to a first capacitor at an input of the high gain amplifier and a feedback loop between the input and output of the high gain amplifier, where the feedback loop includes a second capacitor. The gain of such a switched capacitor amplifier will generally depend on the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor. To achieve a desired amplification gain (e.g., where the magnitude is approximately 20), the first capacitor must be designed to have a much larger (e.g., 20 times) capacitance than the second capacitor, which itself must be designed according to minimum size fabrication rules. Overall, this switched capacitor amplifier arrangement results in a large requirement for capacitor size, limiting the possibility of shrinking the area consumed by such a pixel circuit in an integrated circuit chip implementation.

[0060] For the fabrication of sensors, it would be advantageous to minimize the size of the capacitors in each pixel circuit. However, due to the size limitations of the first capacitor in the above approach, the switched capacitor amplifier can not be shrunk further. Thus, the area consumed by the pixel circuit can be too large to further increase the pixel density in a vision sensor. Some existing solutions replace the switched capacitor amplifier and use a complex feedback loop. However, this approach requires a large number of components, which also sets a limit on the size and scalability of the pixel array. Furthermore, existing solutions can have complex biasing requirements at the preamplifier stage, which can limit the dynamic range of the amplifier.

[0061] Embodiments of the present disclosure provide for pixel circuitry that allows for optimal use of advanced semiconductor fabrication process technology to implement a vision sensor with competitive pixel size. This can greatly improve pixel circuitry scalability and reduce circuit complexity. The inventive pixel circuitry disclosed herein uses a feedback-free configuration and an amplifier with a defined gain (which can be adjustable or non-adjustable), example embodiments of which are provided in the following description.

[0062] The following embodiments of pixel circuitry using a feedback-free configuration and a defined gain amplifier can be applied to any vision sensor. FIGS. 1A-1D The circuitry described in the Background section provides an example of such a vision sensor, but does not place any limitations on the type of vision sensor in which embodiments of the present disclosure can be implemented. Thus, as explained above, embodiments of the present disclosure can be applied to any vision sensor, regardless of whether such a vision sensor uses superpixels (e.g., as in FIG. 2 the Background section). Furthermore, embodiments of the present disclosure can be applied to any vision sensor, regardless of whether such a vision sensor performs exposure measurement, whether such a vision sensor is synchronously or asynchronously operated, or whether such a vision sensor uses an ADC or other component.

[0063] FIGS. 1A-1D is a schematic representation of an example pixel circuit 200 in accordance with embodiments of the present disclosure. In some embodiments, as a non-limiting example, pixel circuit 200 can be implemented as part of a superpixel as shown and described in FIG. 2 the Background section. Like pixel circuit 100A, pixel circuit 200 can be used in a vision sensor (e.g., a time-contrast sensor).

[0064] Pixel circuit 200 can output data when a change in light intensity is detected by a photodetector. As FIG. 2 shown, pixel circuit 200 includes a light-sensitive element (e.g., a photodiode, labeled “PD”) that generates a current signal (labeled “I ph ”) in response to the brightness of light impinging thereon. Pixel circuit 200 also includes a converter (e.g., a current-voltage converter, labeled “I / V”) that receives I ph from the PD and generates a voltage signal (labeled “V ph ”) based on (e.g., proportional to or in a logarithmic relationship with) the current signal I PR ”. Pixel circuit 200 also includes a capacitor (labeled C c ”) electrically coupled in series to I / V that receives V PR from I / V. Pixel circuit 200 also includes an amplifier, e.g., electrically coupled in series to capacitor C ca control gain amplifier (labeled "CG amp"). The CG amp generates an amplified signal at an output (labeled "output") based on the output signal from the C c Although a control gain amplifier is shown and described in FIG. 2 , it will be understood from the present disclosure that this is a non-limiting example. In some embodiments, the gain of the amplifier can be controllable or adjustable, and in other embodiments, the gain of the amplifier is not controllable or adjustable. In some embodiments, the gain of the amplifier can be defined by the number of stacked transistors of the amplifier, which number is not adjustable. In other embodiments, the gain of the amplifier can be controlled by turning on or off the stacked transistors. In some embodiments, the gain of the amplifier can be controlled by turning on or off the amplifier stage, as further disclosed herein.

[0065] The pixel circuit 200 can also include one or more comparators. For example, in FIG. 2 , two comparators are shown, labeled "comp 1" and "comp 2". Each comparator is electrically coupled to the output of the CG amp ("output"). Each comparator generates a trigger signal upon a match condition of the amplified signal. In some embodiments, the condition can include the amplitude of the amplified signal generated by the CG amp being greater than or equal to a threshold value. For example, comp 1 or comp 2 can compare the amplified signal to a threshold value and generate a trigger signal with a polarity (e.g., positive or negative) when the amplified signal is greater than or equal to the threshold value. In some embodiments, the threshold value can be preset to represent a minimum change required to define a detected event. When comp 1 or comp 2 outputs a trigger signal, the trigger signal can represent that the change in light intensity detected by the PD is beyond the minimum change required to be defined as a detected event. In some embodiments, comp 1 or comp 2 can output the trigger signal to an external readout system (not shown in FIG. 2 ).

[0066] It is noted that although the pixel circuit 200 in FIG. 2 includes comp 1 and comp 2, in some embodiments, comp 1 and comp 2 can be external to the pixel circuit 200. That is, such a pixel circuit can not include comparators. For example, multiple such pixel circuits can be provided that share one or more comparators external to the pixel circuits.

[0067] The pixel circuit 200 also includes a reset device (labeled "SI" in FIG. 2 ) electrically coupled between the input and the output of the CG amp. The reset device SI can reset the CG amp in response to generating a trigger signal. As FIG. 2As shown, S1 may include a switch. The voltage between the input ("input") and output ("output") of the CGamp can be reset by closing the switch of the reset device S1. In some embodiments, S1 can reset the CGamp by setting the voltage between the input and output of the CGamp to zero. In some embodiments, when comp1 or comp2 outputs a trigger signal to an external readout system, the external readout system can send an acknowledgment signal to the pixel circuit 200 in response to receiving the trigger signal. After receiving the acknowledgment signal, the pixel circuit 200 can generate a reset signal (in... FIG. 2 The pixel circuit 200 generates a reset (marked as "reset") to close the switch of the reset device S1 and reset the control gain amplifier CG amp. After resetting CG amp, the pixel circuit 200 is ready to detect new events. In some embodiments, the pixel circuit 200 may generate a reset to close the switch of the reset device S1 and reset the control gain amplifier CG amp when comp1 or comp2 reads out a system output trigger signal, regardless of the reception of an acknowledgment signal. For example, the pixel circuit 200 may generate a reset substantially at the same time as comp1 or comp2 outputs a trigger signal or within a predetermined time period after comp1 or comp2 outputs a trigger signal.

[0068] like FIG. 3 As shown, the pixel circuit 200 has no feedback (and capacitive feedback) between the output and input of the control gain amplifier CG amp (i.e., no capacitor is placed and connected between the output and input of the amplifier). Therefore, V PR The amplification does not depend on any feedback configuration or capacitance ratio required by existing solutions as described above. Instead, the CG amp is designed to be an amplifier with well-controlled and well-matched gain (e.g., where the amplitude is approximately 20), while allowing for optimal use of advanced semiconductor manufacturing process techniques to realize visual sensors with competitive pixel sizes.

[0069] exist FIG. 3 In the middle, before the control gain amplifier CG amp is reset, capacitor C c Based on I ph The instantaneous value (e.g., proportional to or logarithmically related to it) is used to store charge. C c V can PR Decoupling from the input of CG amp allows for independence from I ph The value of capacitor C is used to set the operating point of CG amp. c Since the gain is independent of the CG amp, the capacitor can be configured to have a much smaller size than capacitors in existing solutions (such as those mentioned above). In this way, the overall size of the pixel circuit 200 can be greatly reduced, and the pixel density of the vision sensor can be greatly increased.

[0070] In some implementations, the amplified signal generated by the control gain amplifier CG amp can be adjusted to suppress charge injection effects that can be caused by parasitic parameters (e.g., stray capacitance) associated with, for example, transistors or interconnect lines, before being provided as input to the comparators (e.g., comp 1 or comp 2). To this end, in some implementations, another capacitor can be disposed between the output of the CG amp and the input of the comparators, as described below with reference to FIG. 3 Further described.

[0071] FIG. 3 is a schematic representation of an exemplary pixel circuit 300 according to implementations of the present disclosure. The pixel circuit 300 can be similar to the pixel circuit 200 described above. However, in comparison to the pixel circuit 200, the pixel circuit 300 includes another capacitor C x . The capacitance of C x may be arbitrary. In some implementations, the capacitance of C x may be configured to be small, thus reducing its size.

[0072] Additionally, the pixel circuit 300 also includes another reset device S2. As FIG. 3 shown, S2 includes a switch that is electrically coupled between inc and a reference signal (e.g., a reference voltage signal (labeled as "vref" in FIG. 5 ). In some implementations, S1 and S2 can be implemented differently (e.g., with different switches). When the CG amp is reset, S2 can electrically switch to reset inc to vref. For example, if the reset device S2 is a switch, the switch of S2 can close to reset inc to vref. In some implementations, vref can be configured to accommodate the input requirements of the comparators comp 1 and comp 2.

[0073] By including C x and S2, the voltage headroom and dynamic range of the pixel circuit 300 can be optimized. Additionally, the design of the pixel circuit 300 can reduce the charge injection effects at the input of the CG amp caused by S1, especially in the case where S1 is a single CMOS transistor.

[0074] In some implementations, to better suppress the charge injection effects into the amplifier input node, S1 can be electrically reset before S2. To do so, the pixel circuit 300 can include a delay circuit electrically coupled between the reset devices S1 and S2 (e.g., in FIGS. 4A-4Blabeled "delay"). The delay circuit can be set to a time delay between delivering the switch signal to S1 and S2. In some embodiments, for each reset switch operation, S1 can be turned off (and thus complete its reset operation) shortly before S2. An example of this sequence is described below with reference to FIGS. 4C-4D Further described.

[0075] In some embodiments, the CG amp can be an amplifier configured to have a particular gain. For example, the particular gain can be a negative gain (e.g., -1, -5, -10, -20, -30, etc.). In some embodiments, the gain of the CG amp can change during operation. In some embodiments, the CG amp can be implemented using multiple stacked transistors and / or multiple stages of a series-connected circuit to achieve higher gain. Example embodiments of a CG amp are further described below.

[0076] FIGS. 4A-4D schematic representations of exemplary amplifiers 400A and 400B in accordance with embodiments of the disclosure are shown. FIGS. 4A-4D schematic representations of exemplary amplifiers 400C and 400D in accordance with embodiments of the disclosure having adjustable open-loop gain are shown. As shown, the amplifiers 400A-400D include multiple stacked transistors represented by M1, M2, M3, and M4. In FIG. 4A In the amplifiers 400A and 400C, M2 and M3 can be NMOS type transistors and M2 and M4 can be PMOS type transistors. In the amplifiers 400B and 400D, M2 and M3 can be PMOS type transistors and M1 and M4 can be NMOS type transistors. FIG. 4A

[0077] In the amplifiers 400A and 400C, M2 and M3 can be NMOS type transistors and M2 and M4 can be PMOS type transistors. In the amplifiers 400B and 400D, M2 and M3 can be PMOS type transistors and M1 and M4 can be NMOS type transistors.

[0077] In the amplifiers 400A and 400C, M2 and M3 can be NMOS type transistors and M2 and M4 can be PMOS type transistors. In the amplifiers 400B and 400D, M2 and M3 can be PMOS type transistors and M1 and M4 can be NMOS type transistors. FIG. 4A In the amplifiers 400A and 400C, M2 and M3 can be NMOS type transistors and M2 and M4 can be PMOS type transistors. In the amplifiers 400B and 400D, M2 and M3 can be PMOS type transistors and M1 and M4 can be NMOS type transistors. FIG. 4B In the amplifiers 400A and 400C, M2 and M3 can be NMOS type transistors and M2 and M4 can be PMOS type transistors. In the amplifiers 400B and 400D, M2 and M3 can be PMOS type transistors and M1 and M4 can be NMOS type transistors. FIG. 4BIn this embodiment, amplifier 400A has a gain of 3. In some embodiments, higher open-loop gain can be achieved by using more stacked diode-connected transistors or by connecting multiple stages of an amplifier similar to amplifier 400A in series. The open-loop gain of amplifier 400A can be configured to any value as described above. In some embodiments, the open-loop gain of amplifier 400A can have an amplitude less than 100 (e.g., less than 90, 80, 70, etc.). For example, in some embodiments, the amplifier gain amplitude is greater than or equal to 20 and less than or equal to 40. As yet another example, in some embodiments, the amplifier gain amplitude is less than 10. In other embodiments, the amplifier gain amplitude is equal to or greater than 10. In still other embodiments, the amplifier gain amplitude is 1 or less.

[0078] exist FIG. 4B In the exemplary controlled-gain amplifier 400B, a bias voltage (labeled "bias") can be used to adjust the input voltage level (labeled "input") of amplifier 400B. For example, the input voltage level can be adjusted to be equal to the output voltage (labeled "output") at the operating point of amplifier 400B. In some embodiments, similar to amplifier 400A, the open-loop gain of amplifier 400B may be associated with the number of stacked transistors. For example, in FIGS. 4A-4B In this amplifier, there are four stacked transistors. The gain of the amplifier 400B is one less than the number of stacked transistors (i.e., in...). FIGS. 4C-4D In this embodiment, amplifier 400B has a gain of 3. In some embodiments, higher open-loop gain can be achieved by using more stacked diode-connected transistors or by connecting multiple stages of an amplifier similar to amplifier 400B in series. The open-loop gain of amplifier 400B can be configured to any value as described above. In some embodiments, the open-loop gain of amplifier 400B can have an amplitude less than 100 (e.g., less than 90, 80, 70, etc.). For example, in some embodiments, the amplifier gain amplitude is greater than or equal to 20 and less than or equal to 40. As yet another example, in some embodiments, the amplifier gain amplitude is less than 10. In other embodiments, the amplifier gain amplitude is equal to or greater than 10. In still other embodiments, the amplifier gain amplitude is 1 or less.

[0079] exist FIG. 4C In this embodiment, the gain of amplifiers 400A and 400B can be defined by the number of stacked transistors, which is not adjustable. In some implementations, the gain of the amplifier can be adjustable, and the circuitry can include switches arranged between the stacked transistors, such that the gain can be controlled or adjusted by turning one or more of the stacked transistors or amplifier stages on or off. FIG. 4DAmplifiers 400C and 400D are shown with adjustable open-loop gain.

[0080] As FIG. 4E shown, amplifier 400C can be similar to amplifier 400A except for the addition of switch SI electrically coupling the gate of M3 and the gate of M2. Further, as FIG. 4E shown, amplifier 400D can be similar to amplifier 400B except for the addition of switch SI electrically coupling the gate of M3 and the gate of M2. When SI is open, amplifiers 400C and 400D can function the same as amplifiers 400A and 400B, respectively. When SI is closed, M3 can be shorted and bypassed in both amplifiers 400C and 400D, where the number of stacked transistors of amplifiers 400C and 400D can be reduced by one, respectively. Thus, the open-loop gain of amplifiers 400C and 400D can be reduced by 1 (i.e., from 3 to 2) when SI is closed. By controlling opening and closing of SI, the stacked transistors of amplifiers 400C and 400D can be turned on or off, and thus the open-loop gain of amplifiers 400C and 400D can be adjustable. It is noted that other embodiments and designs of switches can be used in addition to SI in amplifiers 400C and 400D. For example, more than one switch can be used. As yet another example, a switch can turn on or off more than one transistor. By designing different switches, the open-loop gain of an amplifier can be controlled or adjusted in any way suitable for an application.

[0081] FIG. 4E is a schematic representation of an exemplary amplifier 400E with adjustable amplifier stages according to embodiments of the present disclosure. In FIG. 4A amplifier 400E includes three amplifier stages: amplifier stage 1 (with input "input 1" and output "output 1"), amplifier stage 2 (with input "input 2" and output "output 2"), and amplifier stage 3 (with input "input 3" and output "output 3") electrically coupled in series between their respective inputs "input" and outputs "output." In some embodiments, one or more of amplifier stage 1, amplifier stage 2, and amplifier stage 3 can be any of amplifiers 400A-400D. As FIG. 4BAs shown, amplifier 400E includes two switches SI and S2. The gain of amplifier 400E (i.e., the gain between the input and the output) can be adjusted by controlling the opening and closing of SI and S2. For example, if S2 is closed (connecting output 3 and the output) and SI is open, then all of amplifier stage 1, amplifier stage 2, and amplifier stage 3 are switched in series between the input and the output, and the gain of amplifier 400E is the product of the gains of amplifier stage 1, amplifier stage 2, and amplifier stage 3. As another example, if S2 is open and SI is closed (connecting output 1 and the output), then amplifier stage 2 and amplifier stage 3 are shorted and bypassed, leaving only amplifier stage 1 to function between the input and the output in amplifier 400E. In this case, the gain of amplifier 400E is adjusted to equal the gain of amplifier stage 1.

[0082] By using the design of FIG. 4C or FIG. 4D a high-precision gain of amplifier 400A or 400B can be achieved. For example, amplifier 400A (or amplifier 400B) has a gain of three (e.g., -3) in amplitude. If, for example, a gain of negative four is needed, this can be achieved by stacking another transistor to amplifier 400A (or amplifier 400B). By using the design of FIGS. 4A-4E or FIGS. 4A-4E amplifiers 400C or 400D with adjustable or controllable gain can be achieved. For example, when SI is open, amplifier 400C (or amplifier 400D) has a gain of three (e.g., -3) in amplitude. If, for example, a gain of negative two is needed, this can be achieved by closing S2. In some embodiments, a higher-amplitude gain can be achieved by connecting several amplifier stages (such as amplifier 400E) in series. For example, amplifier stage 1, amplifier stage 2, and amplifier stage 3 of amplifier 400E can have gains of 2, 4, 3, respectively, and if S2 is closed and SI is open, then amplifier 400E can have a total gain of 24. Also, as shown in FIG. 5 amplifiers 400A-400E do not use capacitors or any other capacitive components. FIG. 3 The design of allows for a great scalability of the circuit, as they are generally easier to scale down the size of the transistors with manufacturing technology in the semiconductor manufacturing process compared to capacitors.

[0083] It should be noted that other designs of amplifiers can be used in addition to exemplary amplifiers 400A-400E. As will be appreciated, embodiments of the present disclosure are not limited to these examples, and other embodiments of amplifiers can be implemented in view of the present disclosure.

[0084] FIG. 5 is an example signal timing diagram of a pixel circuit according to embodiments of the present disclosure. FIG. 3 is an example signal timing diagram of a pixel circuit according to embodiments of the present disclosure.FIG. 5 The waveforms of signals in pixel circuit 300 are shown during operation phases (e.g., for event detection) and reset phases (e.g., for resetting the pixel circuit to prepare for the next event detection).

[0085] During the operational phase, if given FIG. 3 of FIG. 3 As shown, I ph The change in V begins at time T1 in response to the brightness of the light striking the PD, which causes V to... PR The voltage at the input of the CG amp (marked as "V") 输入 The voltage at the output of the CG amp (marked as "V") 输出 The voltage at inc (marked as "V") and inc inc ") Change. Assume FIG. 5 comp1 in the middle has a threshold TH comp1 If V inc Exceeding TH at time T2 comp1 Then comp1 can generate a trigger signal V indicating that the change in brightness detected by the PD satisfies the definition of an event. 接通 .

[0086] During the reset phase, as given FIG. 3 of FIG. 5 As shown, S1 can receive a reset signal at time T3. FIG. 3 The "reset" function in the text. FIG. 6 The middle mark is "V" 重设S1 Once V is received 重设S1 S1 can be used as an electric switch to turn V 输入 Set to V 输出 S2 can also receive a reset signal (marked as "V") at time T3. 重设S2 Once V is received 重设S2 S2 can be used as an electric switch to turn V inc Set as FIG. 6 The vref is shown. At T3, comp1 can stop outputting the trigger signal, where V 接通 The setting is reset to 0. At time T4, S1 can be electrically disconnected (i.e., disconnected) to complete the reset of CG amp. At time T5, S2 can be electrically disconnected (i.e., disconnected) to complete C x Resetting and inc.

[0087] FIGS. 2-3This is a flowchart of an exemplary method 600 for controlling a sensor according to embodiments of the present disclosure. In some embodiments, the sensor may be at least one of a time-comparison (TC) sensor. The sensor may include pixel circuitry (e.g., pixel circuitry 200 or 300). In some embodiments, pixel circuitry may be used to perform... FIGS. 2-3 Method 600.

[0088] At step 602, the pixel circuit responds to light impacting the photosensitive element (e.g., FIGS. 2-3 The current signal is received on the PD (e.g., in the PD). FIGS. 2-3 I in ph For example, a current signal can be received from the PD of pixel circuit 200 or 300.

[0089] At step 604, the pixel circuit converts the current signal into a voltage signal (e.g., FIG. 5 V in PR A voltage signal can be generated based on a current signal (e.g., proportional to or logarithmically related to it). For example, the current signal can be converted by a current-to-voltage converter (I / V) of pixel circuits 200 or 300.

[0090] At step 606, the pixel circuit passes through the first capacitor (e.g., FIGS. 4A-4E C in c Generate decoupled voltage signals based on voltage signals (e.g., FIG. 5 V in 输入 Voltage signals can be decoupled from current signals.

[0091] At step 608, the pixel circuit passes through an amplifier (e.g., FIG. 5 The control gain amplifier CG amp in, or FIG. 3 The exemplary amplifiers 400A to 400E in the example generate the amplified signal based on the decoupled voltage signal (e.g., ​ V in 输出 There is no capacitive feedback between the amplified signal and the decoupled voltage signal.

[0092] At step 610, when the amplified signal matches the condition, the pixel circuit generates a trigger signal (e.g., ​ V in 接通 For example, the trigger signal may be generated by one or more comparators in the pixel circuit (e.g., comp1 and comp2 of pixel circuit 200 or 300). In some embodiments, the condition may be that the amplitude of the amplified signal is greater than or equal to a threshold (e.g., ​ TH in comp1 In some implementations, the pixel circuit can also read out the system output trigger signal to the outside.

[0093] At step 612, the pixel circuit resets the amplifier when the trigger signal is generated. For example, the pixel circuit can close a switch (e.g., first switch SI of pixel circuit 200 or 300) electrically coupled between an input (e.g., input of pixel circuit 200 or 300) and an output (e.g., output of pixel circuit 200 or 300) of the amplifier (e.g., CG amp). In some embodiments, the pixel circuit can receive a confirmation signal from an external readout system after outputting the trigger signal and then reset the amplifier.

[0094] In some embodiments, the method 600 can further include resetting another switch (e.g., second switch S2 of pixel circuit 200 or 300) electrically coupled between a reference signal (e.g., vref in pixel circuit 300) and an input (e.g., inc of comp 1 and comp2 of pixel circuit 300) of a comparator used to generate the trigger signal, where another capacitor is electrically coupled in series between the amplifier (e.g., CG amp) and the input of the comparator. ​

[0095] Further, in some embodiments, the method 600 can include turning off the other switch (e.g., S2) later than turning off the switch (e.g., SI) after resetting the amplifier. For example, the pixel circuit can use a delay circuit (e.g., delay of pixel circuit 300) electrically coupled between SI and S2 to set a time delay between switching the first switch SI and the second switch S2.

[0096] The foregoing description has been presented for purposes of illustration. The foregoing description is not exhaustive and does not limit the precise form or implementation of the disclosed embodiments. Modifications and variations are possible in light of the above disclosure. For example, the described implementations include hardware, but systems and methods according to the present disclosure can be implemented in hardware and software. Additionally, although certain components have been described as being coupled, such components can be integrated or distributed in any suitable manner.

[0097] Additionally, although illustrative embodiments have been described herein, the scope includes any and all embodiments having equivalent elements, modifications, omissions, combinations (e.g., of aspects across various embodiments), variations and / or alterations of the disclosed embodiments. Elements of the claims should not be limited to the examples described in the specification or in the examples of the application, which will be construed as non-exhaustive, and the examples of the application will be interpreted as non-exhaustive. Moreover, the steps of the disclosed methods can be modified in any suitable manner, including reordering steps and / or inserting or deleting steps.

[0098] ​The features and advantages of the present disclosure will be apparent from the detailed description, and thus, it is intended that all systems and methods falling within the true spirit and scope of the present disclosure be covered by the appended claims. As used herein, the indefinite articles "a" and "an" mean "one or more" unless otherwise indicated in the given context. Similarly, the use of the conjunctive "and" or "or" does not necessarily denote the mutually exclusive disjunction of the terms unless expressly indicated in the given context. Furthermore, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the present disclosure to the exact construction and operation illustrated and described, and accordingly, all suitable modifications and equivalents should be considered as falling within the scope of the present disclosure.

[0099] Other embodiments will be apparent to those skilled in the art from consideration of the specification and practice of the embodiments disclosed herein. The specification and examples are intended to be exemplary only and the scope and spirit of the disclosed embodiments are indicated by the appended claims.

Claims

1. An event-based vision sensor comprising a plurality of pixels, each pixel comprising: a photosensitive element configured to generate a current signal in response to a luminance of light impinging on the photosensitive element; a transducer configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal; a capacitor electrically coupled in series to the transducer and configured to receive the voltage signal from the transducer; an open loop amplifier electrically coupled in series to the capacitor at an input and configured to generate an amplified signal at an output based on an output signal from the capacitor, wherein there is no feedback between the output and the input of the open loop amplifier, and wherein the open loop amplifier comprises a plurality of transistors stacked to provide an open loop gain of control of the open loop amplifier, wherein a first transistor of the plurality of transistors is configured to receive the output signal from the capacitor, a second transistor of the plurality of transistors is configured to receive a bias voltage at its gate that sets an operating point of the open loop amplifier, the first and second transistors are of the same polarity, and wherein each transistor of the plurality of transistors other than the first and second transistors is in diode configuration; and a reset device electrically coupled between the input and the output of the open loop amplifier and configured to reset the open loop amplifier in response to generating a trigger signal.

2. The event-based vision sensor of claim 1, wherein a gate of each transistor of the plurality of transistors stacked other than the first and second transistors is electrically coupled to a drain of that transistor, and an open loop gain of the amplifier is associated with a number of transistors in the plurality of transistors stacked.

3. The event-based vision sensor of claim 1, wherein an open loop gain of the open loop amplifier is adjustable.

4. The event-based vision sensor of claim 3, wherein the open loop gain of the amplifier is adjustable by switching one or more transistors of the plurality of transistors stacked on or off.

5. The event-based vision sensor of claim 1, wherein each pixel further comprises: a comparator electrically coupled to the output of the open loop amplifier and configured to generate the trigger signal when the amplified signal matches a condition, and wherein the condition comprises an amplitude of the amplified signal being greater than or equal to a threshold value.

6. The event-based vision sensor of claim 5, wherein the comparator is further configured to output the trigger signal to an external readout system.

7. The event-based vision sensor of claim 6, wherein the external readout system is configured to send a confirmation signal to the pixel in response to the trigger signal, and the reset device is further configured to reset the open loop amplifier in response to the confirmation signal.

8. The event-based vision sensor of claim 6, wherein the reset device is further configured to reset the open-loop amplifier after the comparator outputs the trigger signal and without regard to receipt of an acknowledgement signal from the external readout system.

9. The event-based vision sensor of claim 5, further comprising: another capacitor directly electrically coupled in series between the output of the amplifier and an input of the comparator; and another reset device electrically coupled to the input of the comparator and configured to set a reference signal to the input of the comparator.

10. The event-based vision sensor of claim 9, wherein the another reset device is further configured to set the reference signal to the input of the comparator by activating the another reset device.

11. The event-based vision sensor of claim 10, wherein, a closed switch to activate another reset device.

12. The event-based vision sensor of claim 9, further comprising: a delay circuit electrically coupled between the reset device and the another reset device and configured to set a time delay between operating the reset device and the another reset device.

13. The event-based vision sensor of claim 9, wherein the reference signal comprises a reference voltage.

14. The event-based vision sensor of claim 1, wherein there is no capacitor between the input and the output of the open-loop amplifier.

15. The event-based vision sensor of claim 1, wherein the sensor comprises at least one time-contrast sensor.

16. The event-based vision sensor of claim 1, wherein a magnitude of an open-loop gain of the open-loop amplifier is less than 100.

17. The event-based vision sensor of claim 1, wherein the reset device is further configured to reset the open-loop amplifier by setting a voltage between the input and the output of the amplifier to zero.

18. The event-based vision sensor of claim 9, wherein the reset device is further configured to reset the amplified signal to the reference signal decoupled from the open-loop amplifier.

19. The event-based vision sensor of claim 1, wherein, the plurality of transistors of the stack are connected between a supply voltage and ground.

20. A pixel circuit for an event-based vision sensor, the pixel circuit comprising: a photosensitive element configured to generate a current signal in response to a luminance of light impinging on the photosensitive element; a converter configured to receive the current signal from the photosensitive element and generate a voltage signal based on the received current signal; a capacitor electrically coupled in series to the converter and configured to receive the voltage signal from the converter; an open loop amplifier electrically coupled in series to the capacitor at an input and configured to generate an amplified signal at an output based on an output signal from the capacitor, wherein there is no feedback between the output and the input of the amplifier, and wherein the open loop amplifier comprises a plurality of transistors stacked to provide an open loop gain of control of the open loop amplifier, wherein a first transistor of the plurality of transistors is configured to receive the output signal from the capacitor, a second transistor of the plurality of transistors is configured to receive a bias voltage at its gate that sets an operating point of the open loop amplifier, the first and second transistors are of the same polarity, and wherein each transistor of the plurality of transistors other than the first and second transistors is in diode connection; and a reset device electrically coupled between the input and the output of the open loop amplifier and configured to reset the open loop amplifier when a trigger signal is generated.

21. The pixel circuit of claim 20, wherein there is no capacitive feedback between the output and the input of the open loop amplifier.

22. The pixel circuit of claim 20, further comprising a comparator electrically coupled to the output of the open loop amplifier and configured to generate the trigger signal when the amplified signal matches a condition.

23. The pixel circuit of claim 20, wherein, a gate of each transistor of the plurality of transistors stacked other than the first and second transistors is electrically coupled to a drain of the transistor, and an open loop gain of the open loop amplifier is associated with a number of transistors in the plurality of transistors stacked.

24. The pixel circuit of claim 21, wherein, the plurality of transistors stacked are connected between a supply voltage and ground.

25. A method for controlling an event-based vision sensor comprising a plurality of pixels, comprising: receiving a current signal in response to light impinging on a photosensitive element; converting the current signal to a voltage signal; generating a decoupled voltage signal from a capacitor based on the voltage signal, wherein the decoupled voltage signal is decoupled from the current signal; generating an amplified signal from an open loop amplifier based on the decoupled voltage signal, wherein there is no capacitive feedback between the amplified signal and the decoupled voltage signal; generating a trigger signal when the amplified signal matches a condition, and wherein the open loop amplifier comprises a plurality of transistors stacked to provide an open loop gain of control of the open loop amplifier, wherein a first transistor of the plurality of transistors is configured to receive the output signal from the capacitor, a second transistor of the plurality of transistors is configured to receive a bias voltage at its gate that sets an operating point of the open loop amplifier, the first and second transistors are of the same polarity, and wherein each transistor of the plurality of transistors other than the first and second transistors is in diode connection; and resetting the amplifier when the trigger signal is generated.

26. The method of claim 25, wherein a gate of each transistor of the plurality of transistors stacked other than the first transistor and the second transistor is electrically coupled to a drain of that transistor, and wherein an open loop gain of the open loop amplifier is associated with a number of transistors of the plurality of transistors stacked.

27. The method of claim 26, wherein the open loop gain of the open loop amplifier is adjustable.

28. The method of claim 27, further comprising: adjusting the open loop gain of the open loop amplifier.

29. The method of claim 25, further comprising: outputting the trigger signal to an external readout system.

30. The method of claim 29, further comprising: receiving an acknowledgement signal from the external readout system after outputting the trigger signal; and resetting the amplifier.

31. The method of claim 29, further comprising: resetting the open loop amplifier after outputting the trigger signal and without regard to receipt of an acknowledgement signal from the external readout system.

32. The method of claim 25, wherein resetting the open loop amplifier comprises: resetting the amplified signal to a reference signal decoupled from the open loop amplifier.

33. The method of claim 32, wherein resetting the amplified signal to the reference signal comprises: activating a reset device electrically coupled between the reference signal and an input of a comparator used to generate the trigger signal, wherein another capacitor is directly electrically coupled in series between the open loop amplifier and the input of the comparator.

34. The method of claim 33, further comprising: setting a time delay between operating the reset device and another reset device using a delay circuit electrically coupled between the reset device and the another reset device.

35. The method of claim 32, wherein the reference signal comprises a reference voltage.

36. The method of claim 25, wherein the sensor comprises at least one time contrast sensor.

37. The method of claim 25, wherein a magnitude of the open loop gain of the amplifier is less than 100.

38. The method of claim 25, wherein generating the trigger signal when the amplified signal matches the condition comprises: generating the trigger signal when a magnitude of the amplified signal is greater than or equal to a threshold value.

39. The method of claim 25, wherein resetting the open loop amplifier comprises activating a reset device electrically coupled between an input and an output of the open loop amplifier.

40. The method of claim 25, wherein resetting the open loop amplifier comprises setting a voltage between an input and an output of the open loop amplifier to zero.

41. The method of claim 25, wherein, the plurality of transistors stacked is connected between a supply voltage and ground.

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