Display device, its working method, and electronic device

Abstract

The invention name of the present disclosure is "display device, its working method, and electronic device". A display device capable of displaying a high-brightness image is provided. One aspect of the present invention is a display device including a pixel provided with a display element and a storage circuit electrically connected to a first wiring and a second wiring. First, a reference potential is supplied to the first wiring. Next, a first image signal is stored in the storage circuit through the second wiring. Then, a second image signal is supplied to the storage circuit through the first wiring, thereby adding the second image signal to the first image signal. Then, the display element displays an image in which an image corresponding to the first image signal and an image corresponding to the second image signal overlap.

Description

Technical Field

[0001] One aspect of the present invention relates to a display device, a method of operating the same, and an electronic device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in this specification or the like relates to an object, a method, or a manufacturing method. In addition, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Thus, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification may include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, an imaging device, a method of operating these devices, or a manufacturing method of these devices.

[0003] Note that in this specification or the like, a semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of a semiconductor device. In addition, a storage device, a display device, an imaging device, and an electronic device sometimes include a semiconductor device. Background Art

[0004] Techniques for forming transistors using metal oxides formed on a substrate have received attention. For example, Patent Documents 1 and 2 disclose techniques for using transistors using zinc oxide and In-Ga-Zn-based oxides as switching elements of pixels of a display device.

[0005] In addition, Patent Document 3 discloses a storage device having a structure in which a transistor with an extremely low off-state current is used for a storage cell.

[0006] [References]

[0007] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861

[0009] [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055

[0010] [Patent Document 3] Japanese Patent Application Laid-Open No. 2011-119674 Summary of the Invention

[0011] When displaying a high-brightness image in a display device including an EL (Electro Luminescence) element or the like, the source driver needs to generate a high-potential image signal and supply the high-potential image signal to pixels including the EL element or the like. However, due to the withstand voltage of the source driver or the like, the height of the potential of the image signal that the source driver can generate is limited. In addition, when the source driver generates a high-potential image signal, the power consumption of the display device increases.

[0012] One of the objects of one aspect of the present invention is to provide a display device capable of displaying an image corresponding to an image signal having a potential higher than the potential that the source driver can output. In addition, one of the objects of one aspect of the present invention is to provide a display device capable of displaying a high-brightness image. In addition, one of the objects of one aspect of the present invention is to provide a high dynamic range display device. In addition, one of the objects of one aspect of the present invention is to provide a low-power display device. In addition, one of the objects of one aspect of the present invention is to provide a display device capable of displaying an image having a brightness corresponding to the illuminance of external light. In addition, one of the objects of one aspect of the present invention is to provide a display device capable of displaying an image with high visibility. In addition, one of the objects of one aspect of the present invention is to provide a highly reliable display device. In addition, one of the objects of one aspect of the present invention is to provide a novel display device or the like. In addition, one of the objects of one aspect of the present invention is to provide a method of operating the above display device. In addition, one of the objects of one aspect of the present invention is to provide a novel semiconductor device or the like.

[0013] Note that the description of these objects does not preclude the existence of other objects. In addition, one aspect of the present invention does not need to achieve all of the above objects. In addition, objects other than these objects are obvious from the description of the specification, drawings, claims, etc., and objects other than the above can be derived from the description of the specification, drawings, claims, etc.

[0014] One aspect of the present invention is a display device including pixels and a circuit. Each pixel includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, a second capacitor, and a display element. One of the source and drain of the first transistor is electrically connected to one electrode of the first capacitor. The other of the source and drain of the first transistor is electrically connected to a first wiring. One of the source and drain of the second transistor is electrically connected to the other electrode of the first capacitor. The other of the source and drain of the second transistor is electrically connected to a second wiring. One electrode of the first capacitor is electrically connected to the gate of the third transistor. The gate of the third transistor is electrically connected to one electrode of the second capacitor. One of the source and drain of the third transistor is electrically connected to the other electrode of the second capacitor. The other electrode of the second capacitor is electrically connected to one of the source and drain of the fourth transistor. The other of the source and drain of the fourth transistor is electrically connected to one electrode of the display element. The circuit is electrically connected to the first wiring and the second wiring. The circuit has a function of supplying a first image signal to the first wiring. The circuit has a function of supplying a reference potential to the second wiring. The circuit has a function of supplying a second image signal to the second wiring.

[0015] In addition, in the above aspect, the reference potential may also be a potential corresponding to the height of the illuminance of external light.

[0016] In addition, in the above aspect, the higher the illuminance of external light, the smaller the reference potential may be.

[0017] In addition, in the above aspect, the reference potential may also be a negative potential.

[0018] In addition, in the above aspect, the capacitance value of the first capacitor may also be larger than that of the second capacitor.

[0019] In addition, in the above aspect, the display element may also be an organic EL element.

[0020] In addition, in the above aspect, the first transistor may include a metal oxide in the channel formation region, and the metal oxide contains In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0021] In addition, an electronic device including a camera and a display device according to one aspect of the present invention is also one aspect of the present invention.

[0022] In addition, one aspect of the present invention is a method of operating a display device including pixels each having a display element and a storage circuit electrically connected to a first wiring and a second wiring. A reference potential is supplied to the first wiring. A first image signal is stored in the storage circuit through the second wiring. A second image signal is supplied to the storage circuit through the first wiring, thereby adding the second image signal to the first image signal. An image in which an image corresponding to the first image signal and an image corresponding to the second image signal are overlapped is displayed by the display element.

[0023] In addition, in the above aspect, the reference potential may also be a potential corresponding to the height of the illuminance of external light.

[0024] In addition, in the above aspect, the higher the illuminance of external light, the smaller the reference potential may be.

[0025] In addition, in the above aspect, the reference potential may also be a negative potential.

[0026] According to one aspect of the present invention, a display device capable of displaying an image signal corresponding to a potential higher than the potential that a source driver can output can be provided. In addition, according to one aspect of the present invention, a display device capable of displaying a high-brightness image can be provided. In addition, according to one aspect of the present invention, a high-dynamic-range display device can be provided. In addition, according to one aspect of the present invention, a low-power display device can be provided. In addition, according to one aspect of the present invention, a display device capable of displaying an image having a brightness corresponding to the illuminance of external light can be provided. In addition, according to one aspect of the present invention, a display device capable of displaying an image with high visibility can be provided. In addition, according to one aspect of the present invention, a highly reliable display device can be provided. In addition, according to one aspect of the present invention, a novel display device or the like can be provided. In addition, according to one aspect of the present invention, a method of operating the above display device can be provided. In addition, according to one aspect of the present invention, a novel semiconductor device or the like can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a diagram illustrating a structural example of a pixel circuit;

[0028] Figure 2A and Figure 2B is a timing chart illustrating an operation example of the pixel circuit;

[0029] Figure 3A1 , Figure 3A2 , Figure 3B1 and Figure 3B2 are diagrams illustrating operation examples of the pixel circuit;

[0030] Figure 4 is a diagram illustrating an operation example of the display device;

[0031] Figure 5 is a block diagram illustrating a structural example of a display device;

[0032] Figures 6A to 6E is a diagram illustrating a pixel;

[0033] Figure 7A and Figure 7B is a diagram illustrating a structural example of a pixel circuit;

[0034] Figure 8 is a diagram illustrating a structural example of a pixel circuit;

[0035] Figure 9A and Figure 9B is a diagram illustrating a structural example of a display device;

[0036] Figure 10A and Figure 10B is a diagram illustrating a structural example of a touch screen;

[0037] Figure 11A and Figure 11B is a diagram illustrating a structural example of a display device;

[0038] Figure 12A1 , Figure 12A2 , Figure 12B1 , Figure 12B2 , Figure 12C1 and Figure 12C2 is a diagram illustrating a structural example of a transistor;

[0039] Figures 13A1 to 13A3 , Figure 13B1 , Figure 13B2 , Figure 13C1 and Figure 13C2 is a diagram illustrating a structural example of a transistor;

[0040] Figures 14A to 14F is a diagram illustrating an example of an electronic device;

[0041] Figure 15 is a cross-sectional view showing a structural example of DOSRAM;

[0042] Figure 16 is a graph illustrating the relationship between gamma values and grayscale;

[0043] Figure 17 is a diagram illustrating a display result. Detailed implementation manners

[0044] The embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and those of ordinary skill in the art can easily understand the fact that its modes and details can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the following embodiments. Note that in the structure of the invention described below, the same reference numerals are used in different drawings to represent the same parts or parts having the same functions, and the repeated description thereof is sometimes omitted. Note that the shading of the same constituent elements is sometimes appropriately omitted or changed in different drawings.

[0045] In this specification and the like, ordinal numbers such as "first", "second", "third", etc. are sometimes attached to avoid confusion of constituent elements. In this case, the ordinal numbers are not attached for the purpose of limiting in terms of number or order.

[0046] In this specification and the like, "electrically connected" includes the case of connection through "an element having a certain electric action". Here, there is no particular limitation on the "element having a certain electric action" as long as it can transmit and receive electric signals between the connection objects. For example, the "element having a certain electric action" includes not only electrodes and wirings, but also switching elements such as transistors, resistors, coils, capacitors, and other elements having various functions.

[0047] (Embodiment 1)

[0048] In the present embodiment, a display device according to one mode of the present invention will be described with reference to the accompanying drawings.

[0049] One mode of the present invention is a display device that has a function of supplying a first image signal to a pixel and adding a second image signal to the first image signal. Here, the first image signal and the second image signal can be generated by a circuit provided outside the pixel, such as a source driver. A storage circuit is provided in each pixel, and the storage circuit holds the first image signal.

[0050] Then, the second image signal is added to the storage circuit holding the first image signal, and the added image signal is supplied to the display element. Therefore, in the display element, an image corresponding to the first image signal and an image corresponding to the second image signal can be overlapped and displayed. Thus, the display device can display an image corresponding to an image signal having a potential higher than the potential that the source driver or the like can generate. Thus, compared with the case of displaying an image corresponding to only one image signal without adding an image signal, the display device can display an image with higher brightness, and thus the dynamic range of the display device can be improved. In addition, since the potential of the image signal generated by the source driver or the like can be reduced, the power consumption of the display device can be reduced.

[0051] In the present specification and the like, the "first image signal" and the "second image signal" may be appropriately swapped as needed.

[0052] [Structural example of pixel circuit]

[0053] Figure 1 The pixel 10a of a display device applicable to one mode of the present invention will be described. The pixel 10a includes a transistor 102, transistors 111, 112, 114, a capacitor 103, a capacitor 113, and an EL element 104.

[0054] One of the source and drain of the transistor 111 is electrically connected to one electrode of the capacitor 113. One of the source and drain of the transistor 114 is electrically connected to the other electrode of the capacitor 113. One electrode of the capacitor 113 is electrically connected to the gate of the transistor 112. The gate of the transistor 112 is electrically connected to one electrode of the capacitor 103. One of the source and drain of the transistor 112 is electrically connected to the other electrode of the capacitor 103. The other electrode of the capacitor 103 is electrically connected to one of the source and drain of the transistor 102. The other of the source and drain of the transistor 102 is electrically connected to one electrode of the EL element 104.

[0055] Here, the wiring connecting one of the source and drain of the transistor 111, one electrode of the capacitor 113, the gate of the transistor 112, and one electrode of the capacitor 103 is referred to as the node NM. In addition, the wiring connecting the other of the source and drain of the transistor 102 and one electrode of the EL element 104 is referred to as the node NA.

[0056] The gate of the transistor 111 is electrically connected to the wiring 121. The gate of the transistor 114 is electrically connected to the wiring 122. The gate of the transistor 102 is electrically connected to the wiring 126. The other of the source and drain of the transistor 111 is electrically connected to the wiring 124. The other of the source and drain of the transistor 114 is electrically connected to the wiring 125.

[0057] The other of the source and drain of the transistor 112 is electrically connected to the power supply line 128 (high potential). The other electrode of the EL element 104 is electrically connected to the common wiring 129. Note that any potential can be supplied to the common wiring 129.

[0058] The wirings 121, 122, and 126 are used as scan lines for controlling the operation of the transistors. The wiring 124 is used as a signal line for supplying the image signal S1. The wiring 125 is used as a signal line for supplying the image signal S2. Note that the image signal S1 and the image signal S2 can be set by a circuit such as a source driver outside the pixel 10a ( Figure 1is not shown in the figure).

[0059] The transistor 111, the transistor 112, the capacitor 113, and the transistor 114 constitute the memory circuit MEM. Note that the transistor 114 may not be included in the memory circuit MEM.

[0060] The node NM is a storage node. By turning on the transistor 111, the signal supplied to the wiring 124 can be written into the node NM. When a transistor with a very low off-state current is used as the transistor 111, the potential of the node NM can be maintained for a long period. As such a transistor, for example, a transistor using a metal oxide for the channel formation region (hereinafter referred to as an OS transistor) can be used.

[0061] Note that, in addition to the transistor 111, the OS transistor can also be applied to other transistors constituting the pixel. Further, as the transistor 111, a transistor containing Si in the channel formation region (hereinafter referred to as an Si transistor) can also be used. Alternatively, an OS transistor can be used as part of the transistors constituting the pixel, and an Si transistor can be used as other transistors. Examples of the above Si transistor include: a transistor containing amorphous silicon, a transistor containing crystalline silicon (typically, low-temperature polycrystalline silicon), a transistor containing single-crystalline silicon, and the like.

[0062] When an EL element is used as a display element, a silicon substrate can be used, and a region where the Si transistor and the OS transistor overlap with each other can be formed. Thereby, even when the number of transistors is large, the pixel density can be increased.

[0063] As the semiconductor material for the OS transistor, a metal oxide having a bandgap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more can be used. Typically, an oxide semiconductor containing indium, etc. can be used. For example, CAAC-OS or CAC-OS mentioned later can be used. The atoms constituting the crystal in CAAC-OS are stable and are suitable for transistors that emphasize reliability. CAC-OS exhibits high mobility characteristics and is suitable for transistors that operate at high speed.

[0064] The OS transistor has a large bandgap and exhibits an extremely low off-state current characteristic. Different from the Si transistor, the OS transistor does not undergo impact ionization, avalanche breakdown, short-channel effect, etc., and thus a highly reliable circuit can be formed.

[0065] As the semiconductor layer in the OS transistor, for example, an oxide film represented by “In-M-Zn” containing indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium) can be adopted.

[0066] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn type oxide, the atomic number ratio of the metal elements in the sputtering target preferably used to form the In-M-Zn oxide film satisfies In≥M and Zn≥M. The atomic number ratio of the metal elements in such a sputtering target is preferably In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. Note that the atomic number ratio of the semiconductor layer formed may vary within the range of ±40% of the atomic number ratio of the metal elements in the above sputtering target.

[0067] As the semiconductor layer, an oxide semiconductor with a low carrier density can be used. For example, as the semiconductor layer, an oxide semiconductor with a carrier density of 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less, more preferably 1×10 13 / cm 3 or less, further preferably 1×10 11 / cm 3 or less, and even more preferably less than 1×10 10 / cm 3 , and an oxide semiconductor of 1×10 -9 / cm 3 or more. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Since the defect energy level density of this oxide semiconductor is low, it can be said that it is an oxide semiconductor with stable characteristics.

[0068] Note that the present invention is not limited to the above description, and materials with appropriate compositions can be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.) of the required transistors. In addition, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic number ratio of metal elements to oxygen, interatomic distance, density, etc. of the semiconductor layer to obtain the required semiconductor characteristics of the transistor.

[0069] When the oxide semiconductor constituting the semiconductor layer contains silicon or carbon, which is one of the Group 14 elements, oxygen defects increase, and the semiconductor layer becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0070] In addition, sometimes carriers are generated when alkali metals and alkaline earth metals are bonded to an oxide semiconductor, increasing the off-state current of the transistor. Therefore, the concentration of alkali metals or alkaline earth metals in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0071] In addition, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, electrons are generated as carriers, increasing the carrier density and making it easy to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have a normally-on characteristic. Therefore, the nitrogen concentration in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is preferably 5×10 18 atoms / cm 3 or less.

[0072] In addition, the semiconductor layer may also have a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having a c-axis oriented crystal, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single crystal structures, the amorphous structure has the highest density of defect states, while CAAC-OS has the lowest density of defect states.

[0073] The oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and no crystalline component. Or, the oxide film having an amorphous structure is, for example, a completely amorphous structure and has no crystalline part.

[0074] In addition, the semiconductor layer may also be a mixed film of two or more of a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a region having CAAC-OS, and a region having a single crystal structure. The mixed film sometimes has, for example, a single-layer structure or a stacked structure including two or more of the above regions.

[0075] The configuration of CAC (Cloud-Aligned Composite)-OS in one mode of the non-single crystal semiconductor layer will be described below.

[0076] CAC-OS refers to a structure in which elements contained in an oxide semiconductor are unevenly distributed, where the size of the material containing the unevenly distributed elements is 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or an approximate size. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal element are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less or an approximate size is also referred to as a mosaic or patch state.

[0077] The oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition, it may also contain one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, etc.

[0078] For example, CAC-OS in In-Ga-Zn oxide (in CAC-OS, In-Ga-Zn oxide can be particularly referred to as CAC-IGZO) means that the material is divided into indium oxide (hereinafter, referred to as InO X1 (X1 is a real number greater than 0)) or indium zinc oxide (hereinafter, referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0)) and gallium oxide (hereinafter, referred to as GaO X3 (X3 is a real number greater than 0)) or gallium zinc oxide (hereinafter, referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0)) and the like to form a mosaic state, and the mosaic InO X1 or In X2 Zn Y2 O Z2 is uniformly distributed in the film (hereinafter, also referred to as a cloud state).

[0079] In other words, CAC-OS is a composite oxide semiconductor having a structure in which regions mainly composed of GaO X3 and regions mainly composed of In X2 Zn Y2 O Z2 or InO X1 are mixed together. In this specification, for example, when the atomic ratio of In to element M in the first region is greater than the atomic ratio of In to element M in the second region, the In concentration in the first region is higher than that in the second region.

[0080] Note that IGZO is a general term and sometimes refers to a compound containing In, Ga, Zn, and O. As a typical example, InGaO 3 (ZnO) m1 (where m1 is a natural number) or In (1+x0) Ga (1-x0) O 3 (ZnO) m0 (-1 ≤ x0 ≤ 1, and m0 is an arbitrary number) represents a crystalline compound.

[0081] The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystalline structure in which multiple IGZO nanocrystals have a c-axis orientation and are connected in a non-oriented manner on the a-b plane.

[0082] On the other hand, CAC-OS is related to the material composition of the oxide semiconductor. CAC-OS refers to the following composition: in a material composition containing In, Ga, Zn, and O, nanoparticle-like regions mainly composed of Ga are observed in some parts and nanoparticle-like regions mainly composed of In are observed in some parts, and they are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary factor.

[0083] CAC-OS does not include a stacked structure of two or more films with different compositions. For example, it does not include a structure composed of two layers of a film mainly composed of In and a film mainly composed of Ga.

[0084] Note that sometimes a clear boundary between a region mainly composed of GaO X3 and a region mainly composed of In X2 Zn Y2 O Z2 or InO X1 cannot be observed.

[0085] When one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, etc. are included in CAC-OS to replace gallium, CAC-OS refers to the following composition: nanoparticle-like regions mainly composed of the metal element are observed in some parts and nanoparticle-like regions mainly composed of In are observed in some parts, and they are randomly dispersed in a mosaic pattern.

[0086] CAC-OS can be formed, for example, by sputtering under the condition of not intentionally heating the substrate. When forming CAC-OS by sputtering, as the film-forming gas, one or more selected from inert gases (typically argon), oxygen gas, and nitrogen gas can be used. Additionally, the lower the flow ratio of oxygen gas in the total flow rate of the film-forming gas during film formation, the better. For example, the flow ratio of oxygen gas is set to be 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0087] CAC-OS has the following characteristics: When measured by θ / 2θ scanning using the Out-of-plane method, one of the X-ray diffraction (XRD: X-ray diffraction) measurement methods, no distinct peak is observed. That is, according to X-ray diffraction measurement, it can be known that there is no orientation in the a-b plane direction and the c-axis direction in the measurement region.

[0088] In addition, in the electron diffraction pattern of CAC-OS obtained by irradiating an electron beam with a beam diameter of 1 nm (also called a nano-beam), a bright annular region and multiple bright spots within this annular region are observed. Thus, from the electron diffraction pattern, it can be known that the crystal structure of CAC-OS has an nc (nano-crystal) structure with no orientation in the plane direction and the cross-section direction.

[0089] In addition, for example, in the CAC-OS of In-Ga-Zn oxide, according to the EDX surface analysis image (EDX-mapping) obtained by energy dispersive X-ray spectroscopy (EDX), it can be confirmed that there are regions mainly composed of GaO X3 and regions mainly composed of In X2 Zn Y2 O Z2 or InO X1 which are unevenly distributed and mixed.

[0090] The structure of CAC-OS is different from that of the IGZO compound in which metal elements are uniformly distributed, and it has properties different from those of the IGZO compound. In other words, CAC-OS has regions mainly composed of GaO X3 etc. and regions mainly composed of In X2 Zn Y2 O Z2 or InO X1 which are separated from each other and the regions mainly composed of each element have a mosaic-like structure.

[0091] Here, In X2 Zn Y2 OZ2 or InO X1 The conductivity of the region mainly composed of is higher than that of the region mainly composed of GaO X3 and so on. In other words, when carriers flow through the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 as the main component, it exhibits the conductivity of an oxide semiconductor. Therefore, when the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 is distributed in the oxide semiconductor in a cloud-like shape, a high field-effect mobility (μ) can be achieved.

[0092] On the other hand, the insulation of the region mainly composed of GaO X3 and so on is higher than that of the region mainly composed of In X2 Zn Y2 O Z2 or InO X1 as the main component. In other words, when the region mainly composed of GaO X3 and so on is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0093] Therefore, when CAC-OS is used for semiconductor elements, through the complementary action due to the insulation caused by GaO X3 and so on and the conductivity due to In X2 Zn Y2 O Z2 or InO X1 a high on-state current (I on ) and a high field-effect mobility (μ) can be achieved.

[0094] In addition, the semiconductor element using CAC-OS has high reliability. Therefore, CAC-OS is suitable for constituent materials of various display devices and the like.

[0095] In pixel 10a, the image signal S1 written to node NM is capacitively coupled with the image signal S2 supplied by wiring 125. The capacitively coupled image signal can be output to node NA. Transistor 114 has the function of selecting a pixel. Transistor 102 is used as a switch for controlling the light emission of EL element 104.

[0096] For example, when the potential of image signal S1 is greater than the threshold voltage (V th) When the image signal S2 is written, the transistor 112 becomes conductive before the image signal S2 is written, causing the EL element 104 to emit light. Therefore, it is preferable to provide the transistor 102 and turn on the transistor 102 to cause the EL element 104 to emit light after the potential of the node NM is fixed.

[0097] That is, as long as the image signal S1 is stored in the node NM, the image signal S2 can be added to the image signal S1. Due to the withstand voltage of the source driver or the like that generates the image signal, there is an upper limit to the potential of the image signal. Then, by adding the two image signals together, the display device can display an image corresponding to an image signal having a potential higher than the potential that the source driver or the like can output. Thus, compared with the case of displaying an image corresponding to only one image signal without adding an image signal, the display device can display an image with higher brightness, thereby improving the dynamic range of the display device. In addition, since the potential of the image signal generated by the source driver or the like can be reduced, the power consumption of the display device can be reduced.

[0098] [Operation example of pixel circuit]

[0099] Using Figure 2A 、 Figure 2B The operation example of the pixel 10a will be described in detail with reference to the timing chart shown. In the following description, the high potential is represented by the potential VDD and the low potential is represented by the potential VSS. Here, for example, the ground potential can be used as the potential VSS. In addition, as the potential V S1 of the image signal S1 supplied to the wiring 124, a positive potential or a negative potential can be used, but here, the case where the height of the potential V S1 is above the potential VSS will be described.

[0100] First, using Figure 2A The operation of writing the image signal S1 to the node NM will be described.

[0101] At time T1, the potentials of the wirings 121, 122, and 126 are set to the potential VSS. In addition, the potential of the wiring 125 is set to a potential lower than the potential VSS, that is, the potential V ol . As the potential V ol , for example, a negative potential can be adopted. Note that in this specification or the like, the potential V ol is sometimes referred to as a reference potential.

[0102] At time T2, the potential of the wiring 122 is set to the potential VDD. As a result, the transistor 114 becomes conductive, and the potential of the other electrode of the capacitor 113 becomes the potential V ol . In addition, the potential of the node NM becomes the potential V ol ' corresponding to the potential V ol . Here, the potential Vol Varies according to the ratio of the capacitance value of capacitor 113 to the capacitance value of capacitor 103.

[0103] At time T3, the potential of wiring 121 is set to potential VDD. As a result, transistor 111 becomes conductive and the potential V of wiring 124 S1 is written to node NM.

[0104] At time T4, the potential of wiring 121 is set to potential VSS. As a result, transistor 111 becomes non-conductive and potential V is maintained in node NM S1 .

[0105] At time T5, the potential of wiring 122 is set to potential VSS. As a result, transistor 114 becomes non-conductive and the writing operation of image signal S1 ends.

[0106] Next, Figure 2B the operation of adding image signal S2 and the operation of causing EL element 104 to emit light are described. The potential of image signal S2 is referred to as potential V S2 . Note that as the potential V of image signal S2 supplied to wiring 125 S2 either a positive potential or a negative potential can be used, but here the case where the level of image signal S2 is above potential VSS is described.

[0107] At time T11, the potential of wiring 122 is set to potential VDD. As a result, transistor 114 becomes conductive and the potential V of node NM NM becomes the value represented by the following formula. Here, C 1 represents the capacitance value of capacitor 113, and C 2 represents the capacitance value of capacitor 103.

[0108] [Equation 1]

[0109]

[0110] In other words, potential V NM depends on the ratio C 1 of capacitance value C 2 to capacitance value C 1 / C 2 , and does not depend on the value itself of capacitance value C 1 and the value itself of capacitance value C 2 . Here, when potential V ol is set to a negative potential, Equation 1 can be changed as follows.

[0111] [Equation 2]

[0112]

[0113] Thus, the larger C 1 / C 2 is, the larger the potential V NM becomes. Additionally, when the capacitance value C 2 is small enough to be negligible compared to the capacitance value C 1 , the potential V NM is expressed by the following formula. Note that in this case, the potential V ol ' is equal to the potential V ol .

[0114] [Formula 3]

[0115] V NM = V s1 + V s2 - V ol (3)

[0116] In other words, the potential V NM becomes the potential corresponding to the sum of the potential V S1 and the potential V S2 . Thus, C 1 / C 2 is preferably large. For example, C 1 / C 2 is preferably greater than 1, more preferably 2 or more, and even more preferably 3 or more. However, when C 1 / C 2 is too large, the capacitance value C 2 with respect to the pixel area of the pixel 10a becomes small and the capacitance value C 2 cannot be sufficiently ensured. Therefore, C 1 / C 2 is preferably 10 or less, more preferably 5 or less.

[0117] Note that due to parasitic capacitances such as the gate capacitance of the transistor 112, the potential V NM is sometimes less than the calculated values of the above Formulas 1 to 3.

[0118] At time T12, the potential of the wiring 122 is set to the potential VSS. Thus, the transistor 114 becomes non-conductive, and the potential of the node NM is determined.

[0119] When the potential of the wiring 126 is set to the potential VDD at time T13, the transistor 102 becomes conductive, and the potential of the node NA becomes the potential corresponding to the potential of the node NM. Thus, the EL element 104 emits light.

[0120] The above is an example of the operation of the pixel 10a. Thus, it can be said that: One aspect of the present invention is a method of operating a display device, in which the potential V of the wiring 125 is set to a reference potentialol After that, the image signal S1 is written to the node NM, and then the image signal S2 is appended and the EL element 104 is caused to emit light.

[0121] Note that the operations shown in each case once Figure 2A and the operation shown in Figure 2B can be performed alternately, but one aspect of the present invention is not limited thereto. For example, by using an OS transistor as the transistor 111, the potential of the node NM can be maintained for a long period of time, so after performing the operation shown in Figure 2A once, the operation shown in Figure 2B can be performed multiple times.

[0122] Here, as shown in Equation 1 and the like, the potential of the node NM when the image signal S2 is appended at the time T11 shown in Figure 2B is determined by the potential V ol . Since the smaller the potential V ol , the larger the potential V NM , the higher the emission luminance of the EL element 104. In other words, in the display device according to one aspect of the present invention, the smaller the potential V ol , the higher-brightness image can be displayed. Thus, the potential V ol is preferably changed according to the illuminance of external light, for example. For example, it is preferable to provide an illuminance sensor in the display device according to one aspect of the present invention to detect the illuminance of external light.

[0123] Figure 3A1 shows the situation outdoors during the daytime on a sunny day, Figure 3B1 and shows the situation outdoors at night. Figure 3A1 , Figure 3B1 The display device 200 shown is a display device according to one aspect of the present invention.

[0124] Figure 3A2 shows Figure 3A1 the potential of the wiring 125 of the display device 200 from time T1 to time T2 in the environment shown in Figure 2A . Figure 3B2 shows Figure 3B1 the potential of the wiring 125 of the display device 200 from time T1 to time T2 in the environment shown in Figure 2A . Here, the potential V Figure 3A2 shown is referred to as the potential V ol and is called the potential V ol [1], and the potential V Figure 3B2 shown is referred to as the potential V ol and is called the potential V ol [2].

[0125] Figure 3A1 The illuminance of the external light in the environment shown in is higher than that in Figure 3B1The illuminance of external light in the environment shown. Thus, in Figure 3A1 the environment shown, it is preferable to make the potential V ol less than Figure 3B1 the potential V in the environment shown ol and display an image with higher brightness on the display device 200. Thus, the visibility of the image displayed by the display device 200 can be improved. In addition, in Figure 3B1 the environment shown, by reducing the brightness of the image displayed by the display device 200, the power consumption of the display device 200 can be reduced.

[0126] Note that the image corresponding to the image signal S1 and the image corresponding to the image signal S2 can also be different. Figure 4 It shows a case where the image P1 corresponding to the image signal S1 is an image including pictures and characters, and the image P2 corresponding to the image signal S2 is an image including only characters. In this case, by overlapping the image P1 and the image P2, the brightness of the characters can be increased, for example, the characters can be emphasized. In addition, as Figure 2A , Figure 2B shown, when rewriting the potential V S1 of the image signal S1, it is necessary to rewrite the potential V S2 of the image signal S2. On the other hand, when rewriting the potential V S2 of the image signal S2, as long as the charge written to the node NM at the time T3 shown in Figure 2A is held at the node NM and does not leak from the transistor 111 or the like, it is not necessary to rewrite the potential V S1 of the image signal S1. Thus, in Figure 4 the case shown, by adjusting the value of the potential V S2 , the brightness of the characters can be adjusted.

[0127] Here, as described above, when rewriting the potential V S1 of the image signal S1, it is necessary to rewrite the potential V S2 of the image signal S2, but when rewriting the potential V S2 of the image signal S2, it is not necessary to rewrite the potential V S1 of the image signal S1. Thus, the rewriting frequency of the image P1 is preferably lower than the rewriting frequency of the image P2. Note that the image P1 is not limited to an image including pictures and characters, and the image P2 is not limited to an image including only characters.

[0128] [Structural example of display device]

[0129] Figure 5A block diagram showing a structural example of a display device according to one aspect of the present invention. The display device includes a pixel array in which pixels 10 are arranged in a matrix, a gate driver 12, a source driver 13, an illuminance sensor 14, and a demultiplexer 15. As the pixel 10, the above-described pixel 10a can be used. The number of demultiplexers 15 can be, for example, the same as the number of columns of the pixels 10 provided on the pixel array. In addition, the source driver 13 and the demultiplexer 15 can be collectively referred to as a source driver. In other words, the demultiplexer 15 can also be included in the source driver.

[0130] As the gate driver 12 and the source driver 13, for example, a shift register circuit can be used. The gate driver 12 is electrically connected to the pixels 10 through wirings 121, 122, and 126. The illuminance sensor 14 is electrically connected to the source driver 13. The source driver 13 is electrically connected to the input terminals of the demultiplexer 15. The first output terminal of the demultiplexer 15 is electrically connected to the pixels 10 through the wiring 124. The second output terminal of the demultiplexer 15 is electrically connected to the pixels 10 through the wiring 125.

[0131] The gate driver 12 is a circuit having a function of generating a signal for controlling the operation of the transistors included in the pixels 10. The source driver 13 is a circuit having a function of generating an image signal S1 and an image signal S2. In addition, the source driver 13 is a circuit having a function of generating a reference potential V ol of. In addition, the potential V ol can also be generated by a circuit other than the source driver.

[0132] The demultiplexer 15 is a circuit having a function of supplying the image signal S1 to the wiring 124 and supplying the image signal S2 to the wiring 125. In addition, when the source driver 13 has a function of generating the potential V ol , the demultiplexer 15 has a function of supplying the potential V ol to the wiring 125.

[0133] The illuminance sensor 14 is a circuit having a function of detecting the illuminance of external light. As described above, in the display device according to one aspect of the present invention, the potential V ol can be changed according to the illuminance of external light. Thus, the illuminance of external light is detected by the illuminance sensor 14, and information about the detected illuminance is supplied to the source driver 13, and the source driver 13 can generate a potential V ol corresponding to the illuminance of external light. When the source driver 13 does not have a function of generating the potential V ol , a structure in which the illuminance sensor 14 is not electrically connected to the source driver 13 can be adopted.

[0134] In addition, the illuminance sensor 14 may include a photoelectric conversion element. As the photoelectric conversion element, for example, a photoelectric conversion element using a photoelectric conversion layer of silicon and a photoelectric conversion element using a photoelectric conversion layer of a selenium-based material can be used.

[0135] The photoelectric conversion element using a selenium-based material has a high external quantum efficiency for visible light. This photoelectric conversion element can utilize avalanche multiplication to increase the amount of electron amplification relative to the incident light quantity. In addition, since the selenium-based material has a high light absorption coefficient, for example, the photoelectric conversion layer can be manufactured as a thin film, so it is advantageous from the manufacturing viewpoint to use a selenium-based material. The thin film of the selenium-based material can be formed by a vacuum evaporation method, a sputtering method, or the like.

[0136] As the selenium-based material, crystalline selenium such as single crystal selenium and polycrystalline selenium, amorphous selenium, a compound of copper, indium, and selenium (CIS), or a compound of copper, indium, gallium, and selenium (CIGS) can be used.

[0137] Figures 6A to 6E Describe the colors emitted by the pixel 10 provided in the display device according to one embodiment of the present invention. As Figure 6A shown, a pixel 10 that emits red (R), a pixel 10 that emits green (G), and a pixel 10 that emits blue (B) can be provided in the display device according to one embodiment of the present invention. Or, as Figure 6B shown, a pixel 10 that emits cyan (C), a pixel 10 that emits magenta (M), and a pixel 10 that emits yellow (Y) can be provided in the display device according to one embodiment of the present invention.

[0138] In addition, as Figure 6C shown, a pixel 10 that emits red (R), a pixel 10 that emits green (G), a pixel 10 that emits blue (B), and a pixel 10 that emits white (W) can be provided in the display device according to one embodiment of the present invention. Or, as Figure 6D shown, a pixel 10 that emits red (R), a pixel 10 that emits green (G), a pixel 10 that emits blue (B), and a pixel 10 that emits yellow (Y) can be provided in the display device according to one embodiment of the present invention. Or, as Figure 6E shown, a pixel 10 that emits cyan (C), a pixel 10 that emits magenta (M), a pixel 10 that emits yellow (Y), and a pixel 10 that emits white (W) can be provided in the display device according to one embodiment of the present invention.

[0139] As Figure 6C , Figure 6EAs shown, by disposing pixels 10 that emit white in a display device according to one embodiment of the present invention, the brightness of the displayed image can be increased. Further, as shown in Figure 6D etc., by increasing the types of colors emitted by pixels 10, the reproducibility of intermediate colors can be improved, and thus the display quality can be enhanced.

[0140] [Modified Examples of Pixel Circuits]

[0141] Next, modified examples of pixel 10 will be described. Pixel 10 may also adopt the structure of pixel 10b shown in Figure 7A Pixel 10b is a structure of pixel 10a in which transistor 102 is omitted.

[0142] As described above, transistor 102 is provided to solve the problem that occurs when the potential of the signal written to node NM is equal to or higher than the threshold voltage (V th ) of transistor 112. Note that when the signal written to node NM is limited to a value lower than V th , transistor 102 can be omitted.

[0143] Further, pixel 10 may adopt the structure of pixel 10c shown in Figure 7B Pixel 10c has a structure in which a back gate is provided in each transistor. By electrically connecting this back gate to the front gate, the on-state current can be increased. Further, a constant potential different from that of the front gate may be provided to the back gate. By adopting this structure, the threshold voltage of the transistor can be controlled. Although a structure in which a back gate is provided in all transistors is shown in Figure 7B , transistors without a back gate may also be included. Further, the structure in which a transistor has a back gate may be used for other pixel circuits in the present embodiment.

[0144] Further, pixel 10 may also have the structure of pixel 10d shown in Figure 8 Pixel 10d has a structure in which transistor 105 and wiring 130 are added to pixel 10a.

[0145] One of the source and drain of transistor 105 is electrically connected to one of the source and drain of transistor 112. The other of the source and drain of transistor 105 is electrically connected to wiring 130. The gate of transistor 105 is electrically connected to wiring 122.

[0146] Wiring 130 is used as a power supply line. When an image signal S1 is written to pixel 10d and when an image signal S2 is written to pixel 10d, by supplying a specific potential, for example, a low potential, from wiring 130 to the other electrode of capacitor 103 through transistor 105, the writing of the image signal can be stably performed.

[0147] This embodiment can be implemented in appropriate combination with the structures described in other embodiments and the like.

[0148] (Embodiment 2)

[0149] This embodiment describes a structural example of a display device using an EL element.

[0150] In Figure 9A , a sealant 4005 is provided so as to surround a display portion 215 provided on a first substrate 4001, and the display portion 215 is sealed by the sealant 4005 and a second substrate 4006.

[0151] The display portion 215 is provided with a pixel array including the pixels shown in Embodiment 1.

[0152] In Figure 9A , a scan line driving circuit 221, a signal line driving circuit 231, a signal line driving circuit 232, and a common line driving circuit 241 all include a plurality of integrated circuits 4042 provided on a printed circuit board 4041. The integrated circuits 4042 are formed of single crystal semiconductors or polycrystalline semiconductors. The signal line driving circuit 231 and the signal line driving circuit 232 have the functions of the source driver shown in Embodiment 1. The scan line driving circuit 221 has the functions of the gate driver shown in Embodiment 1. The common line driving circuit 241 has the function of supplying a predetermined potential to the common wiring shown in Embodiment 1.

[0153] Various signals and potentials are supplied to the scan line driving circuit 221, the common line driving circuit 241, the signal line driving circuit 231, and the signal line driving circuit 232 through an FPC (Flexible Printed Circuit).

[0154] The integrated circuits 4042 included in the scan line driving circuit 221 and the common line driving circuit 241 have the function of supplying selection signals to the display portion 215. The integrated circuits 4042 included in the signal line driving circuit 231 and the signal line driving circuit 232 have the function of supplying image data to the display portion 215. The integrated circuits 4042 are mounted in a region different from the region surrounded by the sealant 4005 on the first substrate 4001.

[0155] Note that there is no particular limitation on the connection method of the integrated circuits 4042, and methods such as wire bonding, COG (Chip On Glass), TCP (Tape Carrier Package), and COF (Chip On Film) can be used.

[0156] Figure 9BAn example of mounting the integrated circuit 4042 included in the signal line driving circuit 231 and the signal line driving circuit 232 using the COG method is shown. In addition, by forming a part or the whole of the driving circuit on the substrate on which the display unit 215 is formed, a system-on-panel can be formed.

[0157] Figure 9B An example of forming the scan line driving circuit 221 and the common line driving circuit 241 on the substrate on which the display unit 215 is formed is shown. By simultaneously forming the driving circuit and the pixel circuit in the display unit 215, the number of components can be reduced. Thereby, the productivity can be improved.

[0158] In addition, in Figure 9B a sealant 4005 is provided so as to surround the display unit 215, the scan line driving circuit 221, and the common line driving circuit 241 provided on the first substrate 4001. A second substrate 4006 is provided on the display unit 215, the scan line driving circuit 221, and the common line driving circuit 241. Thus, the display unit 215, the scan line driving circuit 221, and the common line driving circuit 241 are sealed together with the display element by the first substrate 4001, the sealant 4005, and the second substrate 4006.

[0159] Although Figure 9B an example of separately forming the signal line driving circuit 231 and the signal line driving circuit 232 and mounting them on the first substrate 4001 is shown, one aspect of the present invention is not limited to this structure, and a scan line driving circuit can be separately formed and mounted, or a part of the signal line driving circuit or a part of the scan line driving circuit can be separately formed and mounted.

[0160] In addition, a display device sometimes includes a panel in which a display element is in a sealed state and a module in which an IC including a controller is mounted in the panel.

[0161] The display unit and the scan line driving circuit provided on the first substrate include a plurality of transistors. As such a transistor, for example, the transistors shown below can be applied.

[0162] The structures of the transistors included in the peripheral driving circuit and the transistors included in the pixel circuit of the display unit can have the same structure or different structures. The transistors included in the peripheral driving circuit can all have the same structure, or two or more structures can be combined. Similarly, the transistors included in the pixel circuit can all have the same structure, or two or more structures can be combined.

[0163] In addition, an input device 4200 can be provided on the second substrate 4006. Figure 9A and Figure 9BThe structure of the input device 4200 provided for the display device shown can be used as a touch screen.

[0164] There is no particular limitation on the sensing element (also referred to as a sensing component) included in the touch screen of one aspect of the present invention. Various sensors capable of detecting the approach or contact of a detection object such as a finger or a stylus can also be used as the detection element.

[0165] For example, as a sensor aspect, various aspects such as a capacitive type, a resistive film type, a surface acoustic wave type, an infrared type, an optical type, and a pressure-sensitive type can be utilized.

[0166] In the present embodiment, a touch screen including a capacitive sensing element is described as an example.

[0167] As the capacitive type, there are a surface capacitive type, a projected capacitive type, etc. In addition, as the projected capacitive type, there are a self-capacitive type, a mutual-capacitive type, etc. The mutual-capacitive type is preferably used because multi-point sensing can be performed simultaneously.

[0168] The touch screen of one aspect of the present invention can adopt various structures such as a structure in which a separately manufactured display device and a detection element are bonded, a structure in which electrodes constituting the detection element are provided on one or both of a substrate supporting the display element and a counter substrate, etc.

[0169] Figure 10A and Figure 10B Shows an example of a touch screen. Figure 10A Is a perspective view of the touch screen 4210. Figure 10B Is a perspective schematic view of the input device 4200. Note that, for clarity, only typical components are shown.

[0170] The touch screen 4210 has a structure in which a separately manufactured display device and a sensing element are bonded.

[0171] The touch screen 4210 includes an input device 4200 and a display device that are overlapped and arranged.

[0172] The input device 4200 includes a substrate 4263, electrodes 4227, electrodes 4228, a plurality of wirings 4237, a plurality of wirings 4238, and a plurality of wirings 4239. For example, the electrode 4227 can be electrically connected to the wiring 4237 or the wiring 4239. In addition, the electrode 4228 can be electrically connected to the wiring 4238. The FPC 4272 can be electrically connected to the plurality of wirings 4237, the plurality of wirings 4238, and the plurality of wirings 4239, respectively. The FPC 4272 can be provided with an IC 4273.

[0173] A touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. When a touch sensor is provided between the first substrate 4001 and the second substrate 4006, an optical touch sensor using a photoelectric conversion element may be used in addition to the capacitive touch sensor.

[0174] Figure 11A is a cross-sectional view along the dotted line N1-N2 in Figure 9B and shows a structural example of a light-emitting display device adopting a top-emission structure using a color filter application method. Figure 11A The shown display device includes an electrode 4015, and the electrode 4015 is electrically connected to the terminal of the FPC 4018 through an anisotropic conductive layer 4019. In Figure 11A the electrode 4015 is electrically connected to the wiring 4014 in the opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.

[0175] The electrode 4015 and the first electrode layer 4030 are formed using the same conductive layer, and the wiring 4014 and the source electrodes and drain electrodes of the transistors 4010 and 4011 are formed using the same conductive layer.

[0176] In addition, the display unit 215 and the scan line driver circuit 221 provided on the first substrate 4001 include a plurality of transistors. In Figure 11A the transistors 4010 in the display unit 215 and the transistor 4011 in the scan line driver circuit 221 are shown. Although Figure 11A the bottom gate type transistors are shown as the transistors 4010 and 4011 in

[0177] In Figure 11A an insulating layer 4112 is provided on the transistors 4010 and 4011. In addition, a partition wall 4510 is formed on the insulating layer 4112.

[0178] In addition, the transistors 4010 and 4011 are provided on the insulating layer 4102. In addition, the transistors 4010 and 4011 include an electrode 4017 formed on the insulating layer 4111. The electrode 4017 can be used as a back gate electrode.

[0179] In addition, Figure 11A the shown display device includes a capacitor 4020. The capacitor 4020 includes an electrode 4021 formed in the same process as the gate electrode of the transistor 4010 and an electrode formed in the same process as the source electrode and drain electrode of the transistor 4010. The electrodes overlap each other with the insulating layer 4103 therebetween.

[0180] Generally, the capacitance of the capacitor provided in the pixel section of the display device is set in consideration of the leakage current of the transistor provided in the pixel section or the like so that it can hold electric charge for a specified period. The capacitance of the capacitor may be set in consideration of the off-state current of the transistor or the like.

[0181] The transistor 4010 provided in the display section 215 is electrically connected to the display element.

[0182] In addition, Figure 11A The insulating layers shown as the insulating layer 4111 and the insulating layer 4103 are insulating layers through which impurity elements hardly permeate. By sandwiching the semiconductor layer of the transistor with the insulating layer 4111 and the insulating layer 4103, the intrusion of impurities from the outside can be prevented.

[0183] As the display element included in the display device, a light-emitting element using electroluminescence (also referred to as an EL element) can be applied. The EL element has a layer containing a light-emitting compound (also referred to as an EL layer) between a pair of electrodes. When a potential difference higher than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side, and electrons are injected into the EL layer from the cathode side. The injected electrons and holes recombine in the EL layer, and thereby, the light-emitting compound contained in the EL layer emits light.

[0184] EL elements are classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0185] In an organic EL element, by applying a voltage, electrons are injected into the EL layer from one electrode, and holes are injected into the EL layer from the other electrode. Through the recombination of these carriers (electrons and holes), the light-emitting organic compound forms an excited state and emits light when returning from this excited state to the ground state. Due to this mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0186] The EL layer may further include a substance with high hole injection property, a substance with high hole transport property, a hole blocking material, a substance with high electron transport property, a substance with high electron injection property, or a bipolar substance (a substance with high electron transport property and high hole transport property) in addition to the light-emitting compound.

[0187] The EL layer can be formed by methods such as vapor deposition (including vacuum vapor deposition), transfer printing, printing, inkjet, coating, etc.

[0188] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements according to their element structures. The dispersed inorganic EL element includes a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and its light-emitting mechanism is donor-acceptor recombination type luminescence using donor levels and acceptor levels. The thin-film inorganic EL element has a structure in which the light-emitting layer is sandwiched between dielectric layers, and the dielectric layers sandwiching the light-emitting layer are sandwiched between electrodes, and its light-emitting mechanism is local type luminescence using inner shell electron transitions of metal ions. Note that an organic EL element is described here as a light-emitting element.

[0189] In order to extract light emission, at least one of a pair of electrodes of the light-emitting element is made transparent. A transistor and a light-emitting element are formed on a substrate. As the light-emitting element, a top emission structure that extracts light emission from the surface on the side opposite to the substrate; a bottom emission structure that extracts light emission from the surface on the substrate side; and a double-sided emission structure that extracts light emission from both surfaces can be adopted.

[0190] Figure 11A This is an example of a light-emitting display device (also referred to as an "EL display device") that uses a light-emitting element as a display element. The light-emitting element 4513 used as the display element is electrically connected to the transistor 4010 provided in the display unit 215. The light-emitting element 4513 can be an element that emits white light. Although the light-emitting element 4513 has a stacked structure of a first electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031, it is not limited to this structure. The structure of the light-emitting element 4513 can be appropriately changed according to the direction of light extraction from the light-emitting element 4513 and the like.

[0191] The partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. It is particularly preferable to use a photosensitive resin material to form the partition wall 4510 in such a manner as to include an opening portion on the first electrode layer 4030, and the side surface of the opening portion has an inclined surface with a continuous curvature.

[0192] The light-emitting layer 4511 can be constituted by one layer or a stack of multiple layers.

[0193] The light-emitting layer 4511 can also contain an inorganic compound such as a quantum dot. For example, by using a quantum dot for the light-emitting layer, it can also be used as a light-emitting material.

[0194] To prevent the intrusion of oxygen, hydrogen, moisture, carbon dioxide, etc. into the light-emitting element 4513, a protective layer may also be formed on the second electrode layer 4031. As the protective layer, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride, DLC (Diamond Like Carbon), etc. can be used. In addition, a filler 4514 is provided in the space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005 and is sealed. Thus, in order not to be exposed to external gases, it is preferable to use a protective film (adhesive film, ultraviolet curable resin film, etc.) with high airtightness and less outgassing and a covering material for encapsulation (enclosure).

[0195] As the filler 4514, in addition to inert gases such as nitrogen or argon, ultraviolet curable resins or thermosetting resins can also be used. For example, PVC (polyvinyl chloride), acrylic resins, polyimides, epoxy resins, silicone resins, PVB (polyvinyl butyral), or EVA (ethylene-vinyl acetate) etc. can be used. The filler 4514 may also contain a desiccant.

[0196] As the sealant 4005, glass materials such as glass powder or curable resins that cure at room temperature such as two-component mixed resins, photocurable resins, thermosetting resins, etc. can be used. The sealant 4005 may also contain a desiccant.

[0197] In addition, Figure 11A The shown display device includes a coloring layer 4301 and a light-shielding layer 4302. The coloring layer 4301 includes a region overlapping the light-emitting element 4513 with the filler 4514 interposed therebetween, and the light-shielding layer 4302 includes a region overlapping the partition wall 4510 with the filler 4514 interposed therebetween.

[0198] The coloring layer 4301 is a colored layer that transmits light in a specific wavelength region. For example, color filters that transmit red, green, blue, cyan, magenta, or yellow light can be used. As materials that can be used for the coloring layer 4301, metal materials, resin materials, pigments, or resin materials containing dyes, etc. can be cited.

[0199] The coloring layer 4301 is provided between adjacent light-shielding layers 4302. The light-shielding layer 4302 has the function of blocking the light emitted from the light-emitting element 4513 and suppressing color mixing between adjacent light-emitting elements 4513. Here, by arranging the coloring layer 4301 such that the end portion thereof overlaps the light-shielding layer 4302, light leakage can be suppressed. As the light-shielding layer 4302, a material that blocks the light emitted from the light-emitting element 4513 can be used. For example, a black matrix can be formed using a metal material or a resin material containing a pigment or a dye, etc.

[0200] In addition, if necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), etc. may be appropriately provided on the light-emitting surface of the light-emitting element. In addition, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment can be performed, which is a treatment for reducing reflected glare by diffusely reflecting light using irregularities on the surface.

[0201] By making the light-emitting element have a microcavity structure, light with high color purity can be extracted.

[0202] Regarding the first electrode layer (also referred to as a pixel electrode layer) and the second electrode layer (also referred to as a common electrode layer, a counter electrode layer, etc.) to which a voltage is applied to the display element, it is sufficient to select the light transmittance and reflectance according to the direction of the extracted light, the location where the electrode layer is provided, and the pattern structure of the electrode layer.

[0203] As the first electrode layer 4030 and the second electrode layer 4031, a light-transmissive conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can be used.

[0204] In addition, the first electrode layer 4030 and the second electrode layer 4031 can be formed of one or more of metals such as tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), their alloys, and their metal nitrides.

[0205] In addition, the first electrode layer 4030 and the second electrode layer 4031 can be formed of a conductive composition containing a conductive polymer (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or a copolymer or its derivatives composed of two or more of aniline, pyrrole, and thiophene can be cited.

[0206] In addition, since transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably composed of a non-linear element.

[0207] As Figure 11A shown, by adopting a color filter method in which a light-emitting element 4513 having a white emission color is combined with a coloring layer, the productivity of a display device according to one embodiment of the present invention can be improved.

[0208] Figure 11B is at Figure 9BThe cross-sectional view of the part indicated by the dotted line N1-N2 in the middle is different from Figure 11A the display device shown in Figure 11B The display device does not include color filters and adopts a separate coating method. In the display device with the separate coating method, the emission color of the light-emitting element 4513 can be white, red, green, blue, cyan, magenta, yellow, etc. according to the material constituting the light-emitting layer 4511.

[0209] By adopting the separate coating method as shown in Figure 11B it is possible to extract light with high color purity. In addition, by providing color filters, even in a display device using the separate coating method, it is possible to extract light with higher color purity.

[0210] In addition, the display device according to one embodiment of the present invention can also adopt a color conversion method or a quantum dot method, etc.

[0211] This embodiment can be implemented by appropriately combining the structures described in other embodiments, etc.

[0212] (Embodiment 3)

[0213] In this embodiment, an example of a transistor that can be used in place of each transistor shown in the above embodiment will be described with reference to the drawings.

[0214] A display device according to one embodiment of the present invention can be manufactured using various types of transistors such as bottom-gate transistors and top-gate transistors. Therefore, it is possible to easily replace the material of the semiconductor layer or the transistor structure used according to the existing production line.

[0215] [Bottom-gate transistor]

[0216] Figure 12A1 is a cross-sectional view of a channel protection type transistor 810 which is a kind of bottom-gate transistor. In Figure 12A1 the transistor 810 is formed on the substrate 771. In addition, the transistor 810 includes an electrode 746 on the substrate 771 with an insulating layer 772 interposed therebetween. Further, a semiconductor layer 742 is included on the electrode 746 with an insulating layer 726 interposed therebetween. The electrode 746 can be used as a gate electrode. The insulating layer 726 can be used as a gate insulating layer.

[0217] In addition, an insulating layer 741 is included on the channel formation region of the semiconductor layer 742. Further, an electrode 744a and an electrode 744b are included on the insulating layer 726 in contact with a part of the semiconductor layer 742. The electrode 744a can be used as one of the source electrode and the drain electrode. The electrode 744b is used as the other of the source electrode and the drain electrode. A part of the electrode 744a and a part of the electrode 744b are formed on the insulating layer 741.

[0218] The insulating layer 741 is used as a channel protection layer. By providing the insulating layer 741 over the channel formation region, it is possible to prevent the semiconductor layer 742 from being exposed when forming the electrodes 744a and 744b. As a result, it is possible to prevent the channel formation region of the semiconductor layer 742 from being etched when forming the electrodes 744a and 744b. According to one aspect of the present invention, a transistor with good electrical characteristics can be achieved.

[0219] In addition, the transistor 810 includes an insulating layer 728 over the electrodes 744a, the electrodes 744b, and the insulating layer 741, and includes an insulating layer 729 over the insulating layer 728.

[0220] When an oxide semiconductor is used for the semiconductor layer 742, a material capable of extracting oxygen from a part of the semiconductor layer 742 to generate oxygen defects is preferably used for at least the portions of the electrodes 744a and 744b that are in contact with the semiconductor layer 742. The carrier concentration in the region where oxygen defects are generated in the semiconductor layer 742 increases, and this region is n-type doped to become an n-type region (n + -type layer). Therefore, this region can be used as a source region or a drain region. When an oxide semiconductor is used for the semiconductor layer 742, examples of materials capable of extracting oxygen from the semiconductor layer 742 to generate oxygen defects include tungsten, titanium, and the like.

[0221] By forming a source region and a drain region in the semiconductor layer 742, the contact resistance between the electrodes 744a and 744b and the semiconductor layer 742 can be reduced. As a result, the electrical characteristics of the transistor, such as the field-effect mobility and the threshold voltage, can be improved.

[0222] When a semiconductor such as silicon is used for the semiconductor layer 742, a layer that functions as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b. The layer that functions as an n-type semiconductor or a p-type semiconductor can be used as a source region or a drain region of the transistor.

[0223] The insulating layer 729 is preferably formed using a material having a function of preventing impurities from diffusing into the transistor from the outside or suppressing the diffusion of impurities. In addition, the insulating layer 729 can be omitted as needed.

[0224] Figure 12A2 The difference between the illustrated transistor 811 and the transistor 810 is that the transistor 811 includes an electrode 723 that can be used as a back gate electrode over the insulating layer 729. The electrode 723 can be formed using the same material and method as the electrode 746.

[0225] Generally speaking, the back gate electrode is formed using a conductive layer and is arranged in a manner that the channel formation region of the semiconductor layer is sandwiched by the gate electrode and the back gate electrode. Therefore, the back gate electrode can have the same function as the gate electrode. The potential of the back gate electrode can be equal to that of the gate electrode, or it can be a ground potential (GND potential) or an arbitrary potential. In addition, by independently changing the potential of the back gate electrode without being linked to the gate electrode, the threshold voltage of the transistor can be changed.

[0226] The electrode 746 and the electrode 723 can both be used as gate electrodes. Therefore, the insulating layer 726, the insulating layer 741, the insulating layer 728, and the insulating layer 729 can all be used as gate insulating layers. Alternatively, the electrode 723 may be provided between the insulating layer 728 and the insulating layer 729.

[0227] Note that when one of the electrode 746 and the electrode 723 is referred to as a "gate electrode", the other is referred to as a "back gate electrode". For example, in the transistor 811, when the electrode 723 is referred to as a "gate electrode", the electrode 746 is referred to as a "back gate electrode". In addition, when the electrode 723 is used as a "gate electrode", the transistor 811 can be said to be a top gate transistor. In addition, one of the electrode 746 and the electrode 723 is sometimes referred to as a "first gate electrode", and the other is sometimes referred to as a "second gate electrode".

[0228] By providing the electrode 746 and the electrode 723 across the semiconductor layer 742 and setting the potential of the electrode 746 and the electrode 723 to be the same, the region through which the carriers flow in the semiconductor layer 742 is further expanded in the thickness direction, so the amount of carrier movement increases. As a result, the on-state current of the transistor 811 increases, and the field effect mobility also increases.

[0229] Therefore, the transistor 811 has a large on-state current relative to the occupied area. That is, the occupied area of ​​the transistor 811 can be reduced relative to the required on-state current. According to one embodiment of the present invention, the occupied area of ​​the transistor can be reduced.

[0230] In addition, since the gate electrode and the back gate electrode are formed using a conductive layer, they have a function of preventing the electric field generated outside the transistor from affecting the semiconductor layer forming the channel (especially the electric field shielding function against static electricity, etc.). In addition, when the back gate electrode is formed larger than the semiconductor layer so as to cover the semiconductor layer with the back gate electrode, the electric field shielding function can be improved.

[0231] In addition, by forming the back gate electrode using a light-shielding conductive film, light can be prevented from entering the semiconductor layer from the back gate electrode side, thereby preventing light degradation of the semiconductor layer and preventing degradation of electrical characteristics such as threshold voltage drift of the transistor.

[0232] According to one aspect of the present invention, a highly reliable transistor can be realized. In addition, a display device or the like with high reliability can be realized.

[0233] Figure 12B1 A cross-sectional view of a channel protection type transistor 820, which is one of the bottom gate type transistors, is shown. The transistor 820 has substantially the same structure as the transistor 810, except that an insulating layer 741 covers the end of the semiconductor layer 742. In addition, in the opening formed by selectively removing the portion of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 is electrically connected to the electrode 744a. In addition, in another opening formed by selectively removing the portion of the insulating layer 741 overlapping the semiconductor layer 742, the semiconductor layer 742 is electrically connected to the electrode 744b. The region of the insulating layer 741 overlapping the channel formation region can be used as a channel protection layer.

[0234] Figure 12B2 The shown transistor 821 is different from the transistor 820 in that the transistor 821 includes an electrode 723 on the insulating layer 729 that can be used as a back gate electrode.

[0235] By providing the insulating layer 729, it is possible to prevent the semiconductor layer 742 from being exposed when forming the electrode 744a and the electrode 744b. Therefore, it is possible to prevent the semiconductor layer 742 from being thinned when forming the electrode 744a and the electrode 744b.

[0236] In addition, compared with the transistors 810 and 811, the distances between the electrode 744a and the electrode 746 and between the electrode 744b and the electrode 746 of the transistors 820 and 821 are longer. Therefore, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. In addition, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one aspect of the present invention, a transistor with good electrical characteristics can be provided.

[0237] Figure 12C1 The shown transistor 825 is a channel etching type transistor, which is one of the bottom gate type transistors. In the transistor 825, the electrodes 744a and 744b are formed without using the insulating layer 741. Therefore, a part of the semiconductor layer 742 exposed when forming the electrodes 744a and 744b is sometimes etched. On the other hand, since the insulating layer 741 is not provided, the productivity of the transistor can be improved.

[0238] Figure 12C2 The shown transistor 826 is different from the transistor 825 in that the transistor 826 has an electrode 723 on the insulating layer 729 that can be used as a back gate electrode.

[0239] [Top gate type transistor]

[0240] Figure 13A1 The illustrated transistor 842 is one of the top-gate type transistors. The transistor 842 forms the electrode 744a and the electrode 744b after forming the insulating layer 729. The electrode 744a and the electrode 744b are electrically connected to the semiconductor layer 742 in the openings formed in the insulating layer 728 and the insulating layer 729.

[0241] In addition, a part of the insulating layer 726 that does not overlap with the electrode 746 is removed, and as Figure 13A3 shown, impurities 755 are introduced into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask, whereby an impurity region can be formed in the semiconductor layer 742 in a self-alignment manner. The transistor 842 includes a region where the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration in the region of the semiconductor layer 742 into which the impurities 755 are introduced through the insulating layer 726 is lower than the region where the impurities 755 are not introduced through the insulating layer 726. An LDD (Lightly Doped Drain) region is formed in the region of the semiconductor layer 742 that does not overlap with the electrode 746.

[0242] Figure 13A2 The illustrated transistor 843 is different from the transistor 842 in that the transistor 843 includes an electrode 723 formed on the substrate 771. The electrode 723 has a region laminated with the semiconductor layer 742 with the insulating layer 772 therebetween. The electrode 723 can be used as a back gate electrode.

[0243] In addition, as Figure 13B1 shown for the transistor 844 and Figure 13B2 shown for the transistor 845, the insulating layer 726 in the region that does not overlap with the electrode 746 can also be completely removed. In addition, as Figure 13C1 shown for the transistor 846 and Figure 13C2 shown for the transistor 847, the insulating layer 726 may not be removed.

[0244] In the transistors 843 to 847, impurities 755 can also be introduced into the semiconductor layer 742 using the electrode 746 as a mask after forming the electrode 746, whereby an impurity region is formed in the semiconductor layer 742 in a self-aligned manner. According to one aspect of the present invention, a transistor with good electrical characteristics can be achieved.

[0245] This embodiment can be implemented by appropriately combining with the structures described in other embodiments and the like.

[0246] (Embodiment 4)

[0247] Examples of electronic devices that can use a display device according to one embodiment of the present invention include display devices, personal computers, image storage devices and image reproduction devices having a recording medium, mobile phones, game machines including portable game machines, portable data terminals, e-book readers, imaging devices such as video cameras or digital cameras, goggle-type displays (head-mounted displays), navigation systems, audio reproduction devices (car audio systems, digital audio players, etc.), copiers, fax machines, printers, multifunction printers, automated teller machines (ATMs), and vending machines. Figures 14A to 14F Specific examples of these electronic devices are shown.

[0248] Figure 14A This is a television set that includes a housing 971, a display unit 973, operation keys 974, speakers 975, a communication connection terminal 976, a photoelectric sensor 977, etc. The display unit 973 is provided with a touch sensor and can perform input operations. By using a display device according to one embodiment of the present invention for the display unit 973, the display unit 973 can display high-brightness images, thereby improving the dynamic range.

[0249] Figure 14B This is an information processing terminal that includes a housing 901, a display unit 902, a display unit 903, a sensor 904, etc. The display unit 902 and the display unit 903 are formed of a single display panel and are flexible. In addition, the housing 901 is also flexible, so that the information processing terminal can be folded and used as shown in the drawings, and the information processing terminal can be used in a flat shape like a tablet terminal. The sensor 904 can detect the shape of the housing 901. For example, when the housing 901 is bent, the display of the display unit 902 and the display unit 903 can be switched. By using a display device according to one embodiment of the present invention for the display unit 902 and the display unit 903, the display unit 902 and the display unit 903 can display high-brightness images, thereby improving the dynamic range.

[0250] Figure 14C This is an example of a mobile phone that includes a housing 951, a display unit 952, operation buttons 953, an external connection port 954, speakers 955, a microphone 956, a camera 957, etc. The mobile phone includes a touch sensor in the display unit 952. All operations such as making a call or inputting text can be performed by touching the display unit 952 with a finger or a stylus. In addition, the housing 951 and the display unit 952 are flexible and can be used in a bent manner as shown in the figure. By using a display device according to one embodiment of the present invention for the display unit 952, the display unit 952 can display high-brightness images, thereby improving the dynamic range.

[0251] Figure 14Dis a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, etc. Data can be input or output by using the touch screen function of the display unit 912. By using the display device of one embodiment of the present invention for the display unit 912, the display unit 912 can display a high-brightness image, thereby improving the dynamic range.

[0252] Figure 14E is a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a display unit 965, operation keys 966, a speaker 967, a zoom button 968, a lens 969, etc. By using the display device of one embodiment of the present invention for the display unit 965, the display unit 965 can display a high-brightness image, thereby improving the dynamic range.

[0253] Figure 14F is a digital signage, which has a structure in which a large display unit 922 is installed on the side of a column 921. By using the display device of one embodiment of the present invention for the display unit 922, the display unit 922 can display a high-brightness image, thereby improving the dynamic range.

[0254] This embodiment can be implemented by appropriately combining the structures described in other embodiments and the like.

[0255] (Embodiment 5)

[0256] In this embodiment, a semiconductor device that can be used for a storage device such as the image storage device illustrated in the above embodiments will be described.

[0257] In this embodiment, as an example of a storage device using an oxide semiconductor, DOSRAM (registered trademark) will be described. "DOSRAM" is derived from Dynamic Oxide Semiconductor Random Access Memory. DOSRAM refers to the following storage device: the storage unit is a 1T1C (one transistor and one capacitor) type unit; the writing transistor is a transistor using an oxide semiconductor.

[0258] Refer to Figure 15 An example of the stacked structure of DOSRAM1000 will be described. In DOSRAM1000, a read amplifier unit 1002 for reading data is stacked with a cell array unit 1003 for storing data.

[0259] As Figure 15As shown, the sense amplifier section 1002 is provided with bit lines BL, Si transistors Ta10, and Ta11. The Si transistors Ta10 and Ta11 include semiconductor layers in a single crystal silicon wafer. The Si transistors Ta10 and Ta11 constitute a sense amplifier and are electrically connected to the bit lines BL.

[0260] The cell array section 1003 includes a plurality of memory cells 1001. The memory cells 1001 include transistors Tw1 and capacitors C1. In the cell array section 1003, two transistors Tw1 share a semiconductor layer. The semiconductor layer is electrically connected to the bit line BL through a conductor (not shown).

[0261] Figure 15 The stacked structure shown can be used for various semiconductor devices formed by stacking a plurality of circuits including transistor groups.

[0262] Figure 15 The metal oxides, insulators, conductors, etc. in can be single-layer or stacked. When manufacturing these layers, various film formation methods such as sputtering method, molecular beam epitaxy (MBE: Molecular Beam Epitaxy) method, pulsed laser ablation (PLA: Pulsed Laser Ablation) method, chemical vapor deposition method (CVD method), atomic layer deposition method (ALD method), etc. can be used. The CVD method includes plasma CVD method, thermal CVD method, metalorganic CVD method, etc.

[0263] Here, the semiconductor layer of the transistor Tw1 is made of a metal oxide (oxide semiconductor). Here, an example in which the semiconductor layer is composed of three metal oxide layers is shown. The semiconductor layer is preferably made of a metal oxide containing In, Ga, and Zn.

[0264] Here, by adding an element that forms oxygen defects or an element that bonds to oxygen defects to the metal oxide, the carrier density of the metal oxide may increase and it may be made low-resistance. For example, by selectively making the semiconductor layer using the metal oxide low-resistance, a source region or a drain region can be provided in the semiconductor layer.

[0265] In addition, as elements for making the metal oxide low-resistance, typically boron or phosphorus. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, noble gases, etc. can also be used. Typical examples of noble gases are helium, neon, argon, krypton, and xenon, etc. The concentration of this element can be measured using secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), etc.

[0266] In particular, boron and phosphorus can use the devices of the amorphous silicon or low-temperature polycrystalline silicon production line, so they are preferred. Existing settings can be used, whereby equipment investment can be reduced.

[0267] For example, a transistor including a semiconductor layer selectively made to have a low resistance can be formed using a dummy gate. Specifically, a dummy gate is provided on the semiconductor layer, and this dummy gate is used as a mask to add an element that makes the semiconductor layer have a low resistance to the semiconductor layer. That is, this element is added to the region of the semiconductor layer that does not overlap with the dummy gate, thereby forming a region with a low resistance. As a method for adding this element, an ion implantation method in which ionized source gas is mass-separated and added, an ion doping method in which ionized source gas is not mass-separated and added, and a plasma immersion ion implantation method, etc. can be used.

[0268] As conductive materials for conductors, there are the following materials: semiconductors typified by polysilicon doped with impurity elements such as phosphorus; silicides such as nickel silicide; metals such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium; or metal nitrides (tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride) etc. having the above metals as components. In addition, conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be used.

[0269] As insulating materials that can be used for insulators, there are aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, etc. In this specification etc., oxynitride refers to a compound in which the oxygen content is greater than the nitrogen content, and nitride oxide refers to a compound in which the nitrogen content is greater than the oxygen content.

[0270] This embodiment can be implemented by appropriately combining with the structures described in other embodiments etc.

[0271] [Example 1]

[0272] In this example, the measurement results of the emission luminance and the measurement results of the relationship between the gamma value and the gray scale in the case of making the EL element included in a display device of one mode of the present invention emit light are described.

[0273] In this example, a display device including a pixel 10d having the Figure 8 shown structure is used to measure the emission luminance of the EL element 104. Specifically, the emission luminance of the EL element 104 in the case of supplying only the image signal S1 to the pixel 10d (condition 1) and the emission luminance of the EL element 104 in the case of supplying the image signal S1 and the image signal S2 to the pixel 10d (condition 2) are measured. Here, the capacitance value C of the capacitor 113 1 and the capacitance value C of the capacitor 103 2Ratio C 1 / C 2 is set to 4 / 1, the potential V ol is set to 0V, the potential of the wiring 130 is set to 0V, the potential of the power supply line 128 is set to 12V, and the potential of the common wiring 129 is set to -2V. Additionally, under condition 1, the potential V S1 of the image signal S1 is set to 5V, and under condition 2, the potential V S1 of the image signal S1 is set to 5V, the potential V S2 of the image signal S2 is set to 5V.

[0274] Table 1 shows the calculated values of the potential V NM of the node NM calculated using Equation 1 shown in Usage Example 1 under conditions 1 and 2. Additionally, the measurement results of the emission luminance of the EL element 104 under conditions 1 and 2 are shown.

[0275] [Table 1]

[0276] Condition 1 Condition 2 <![CDATA[Potential V NM > 5V 9V Brightness <![CDATA[612cd / m 2 > <![CDATA[1329cd / m 2 >

[0277] As shown in Table 1, it was confirmed that by supplying both the image signal S2 and the image signal S1 to the pixel 10d, the emission luminance of the EL element 104 was increased compared to the case where only the image signal S1 was supplied to the pixel 10d.

[0278] Additionally, the relationship between the gamma value and the gray scale was measured using a display device including the pixel 10d having the Figure 8 shown structure. Specifically, the relationship between the gamma value and the gray scale was measured in the case where only the image signal S1 was supplied to the pixel 10d (condition 3) and in the case where the image signal S1 and the image signal S2 were supplied to the pixel 10d (condition 4). Additionally, similar to the above conditions 1 and 2, C 1 / C 2 was set to 4 / 1, the potential V ol was set to 0V, the potential of the wiring 130 was set to 0V, the potential of the power supply line 128 was set to 12V, and the potential of the common wiring 129 was set to -2V. Additionally, the potential V S1 was made equal to the potential V S2 , and when the gray scale was 0, both the potential V S1 and the potential V S2 were set to 1V, and when the gray scale was 255, both the potential V S1 and the potential V S2 were set to 5V.

[0279] Figure 16 shows the measurement results of the relationship between the gamma value and the gray scale under conditions 3 and 4. FromFigure 16 It was confirmed that in each gray level at which measurement was performed, by supplying both the image signal S2 and the image signal S1 to the pixel 10d (Condition 4), the gamma value increased as compared with the case where only the image signal S1 was supplied to the pixel 10d (Condition 3).

[0280] [Embodiment 2]

[0281] In this embodiment, the display result in the case where an image is displayed by a display device using one mode of the present invention will be described.

[0282] In this embodiment, an image is displayed by a display device including the pixel 10d having the structure shown in Figure 8 . Specifically, an image P1 corresponding to the image signal S1, an image P2 corresponding to the image signal S2, and an image in which the image P1 and the image P2 are overlapped are displayed. The capacitance value C of the capacitor 113 1 and the capacitance value C of the capacitor 103 2 The ratio C 1 / C 2 is set to 4 / 1, the potential V ol is set to 0V, the potential of the wiring 130 is set to 0V, the potential of the power supply line 128 is set to 10V, and the potential of the common wiring 129 is set to -2V.

[0283] As shown in Figure 17 , it was confirmed that by overlapping the image P1 and the image P2, an image with higher brightness was displayed as compared with the case where only the image P1 was displayed and the case where only the image P2 was displayed.

[0284] Symbol Explanation

[0285] 10: Pixel, 10a: Pixel, 10b: Pixel, 10c: Pixel, 10d: Pixel, 12: Gate Driver, 13: Source Driver, 14: Illuminance Sensor, 15: Demultiplexer, 102: Transistor, 103: Capacitor, 104: EL Element, 105: Transistor, 111: Transistor, 112: Transistor, 113: Capacitor, 114: Transistor, 121: Wiring, 122: Wiring, 124: Wiring, 125: Wiring, 126: Wiring, 128: Power Supply Line, 129: Common Wiring, 130: Wiring, 200: Display Device, 215: Display Unit, 221: Scan Line Driving Circuit, 231: Signal Line Driving Circuit, 232: Signal Line Driving Circuit, 241: Common Line Driving Circuit, 723: Electrode, 726: Insulating Layer, 728: Insulating Layer, 729: Insulating Layer, 741: Insulating Layer, 742: Semiconductor Layer, 744a: Electrode, 744b: Electrode, 746: Electrode, 755: Impurity, 771: Substrate, 772: Insulating Layer, 810: Transistor, 811: Transistor, 820: Transistor, 821: Transistor, 825: Transistor, 826: Transistor, 842: Transistor, 843: Transistor, 844: Transistor, 845: Transistor, 846: Transistor, 847: Transistor, 901: Housing, 902: Display Unit, 903: Display Unit, 904: Sensor, 911: Housing, 912: Display Unit, 913: Speaker, 919: Camera, 921: Column, 922: Display Unit, 951: Housing, 952: Display Unit, 953: Operation Button, 954: External Connection Port, 955: Speaker, 956: Microphone, 957: Camera, 961: Housing, 962: Shutter Button, 963: Microphone, 965: Display Unit, 966: Operation Key, 967: Speaker, 968: Zoom Button, 969: Lens, 971: Housing, 973: Display Unit, 974: Operation Key, 975: Speaker, 976: Communication Connection Terminal, 977: Light Sensor, 1000: DOSRAM, 1001: Memory Cell, 1002: Readout Amplifier Section, 1003: Cell Array Section, 4001: Substrate, 4005: Sealant, 4006: Substrate, 4010: Transistor, 4011: Transistor, 4014: Wiring, 4015: Electrode, 4017: Electrode, 4018: FPC, 4019: Anisotropic Conductive Layer, 4020: Capacitor, 4021: Electrode, 4030: Electrode Layer, 4031: Electrode Layer, 4041: Printed Circuit Board, 4042: Integrated Circuit, 4102: Insulating Layer, 4103: Insulating Layer, 4110: Insulating Layer, 4111: Insulating Layer, 4112: Insulating Layer, 4200: Input Device, 4210: Touch Screen, 4227: Electrode, 4228: Electrode, 4237: Wiring, 4238: Wiring, 4239: Wiring, 4263: Substrate,4272: FPC, 4273: IC, 4301: Coloring layer, 4302: Light-shielding layer, 4510: Partition wall, 4511: Light-emitting layer, 4513: Light-emitting element, 4514: Filler.

[0286] This application is based on Japanese Patent Application No. 2017-216389 filed with the Japan Patent Office on November 9, 2017, and Japanese Patent Application No. 2018-028368 filed with the Japan Patent Office on February 21, 2018, the entire contents of which are incorporated herein by reference.

Claims

1. A display device, comprising: pixels; and a circuit, wherein the pixel includes a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and a display element, wherein one of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitor, wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring, wherein one of the source and the drain of the second transistor is electrically connected to the other electrode of the first capacitor, wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring, wherein the one electrode of the first capacitor is electrically connected to the gate of the third transistor, wherein the gate of the third transistor is electrically connected to the one electrode of the second capacitor, wherein one of the source and the drain of the third transistor is electrically connected to the other electrode of the second capacitor and one electrode of the display element, wherein the circuit is electrically connected to the first wiring and the second wiring, wherein the circuit is configured to provide a first image signal to the first wiring, wherein the circuit is configured to provide a reference potential to the second wiring, and wherein the circuit is configured to provide a second image signal to the second wiring.

2. A display device, comprising: pixels; and a circuit, wherein the pixel includes a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and a display element, wherein one of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitor, wherein the other of the source and the drain of the first transistor is electrically connected to a first wiring, wherein one of the source and the drain of the second transistor is electrically connected to the other electrode of the first capacitor, wherein the other of the source and the drain of the second transistor is electrically connected to a second wiring, wherein the one electrode of the first capacitor is electrically connected to the first gate of the third transistor, wherein the first gate of the third transistor is electrically connected to the second gate of the third transistor and one electrode of the second capacitor, wherein one of the source and the drain of the third transistor is electrically connected to the other electrode of the second capacitor and one electrode of the display element, wherein the circuit is electrically connected to the first wiring and the second wiring, wherein the circuit is configured to provide a first image signal to the first wiring, wherein the circuit is configured to provide a reference potential to the second wiring, and wherein the circuit is configured to provide a second image signal to the second wiring.

3. The display device according to claim 1 or 2, wherein the reference potential is a potential having a value corresponding to the illuminance of external light.

4. The display device according to claim 3, wherein when the illuminance of the external light is higher, the reference potential is lower.

5. The display device according to claim 3, wherein the reference potential is a negative potential.

6. The display device according to claim 1 or 2, wherein The capacitance value of the first capacitor is higher than that of the second capacitor.

7. The display device according to claim 1 or 2, wherein, the display element is an organic EL element.

8. The display device according to claim 1 or 2, wherein, the first transistor includes a metal oxide in its channel formation region, wherein the metal oxide includes In, Zn, and M, and wherein M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf.

9. An electronic device, comprising: the display device according to claim 1 or 2; and a camera.

Images