An efficient and safe silicon carbide MOSFET and its applications

Abstract

The present invention relates to the field of H01L29 / 00 in IPC patent classification, and particularly relates to a high-efficiency and safe silicon carbide MOS transistor and its application. The high-efficiency and safe silicon carbide MOS transistor has a structure including a top metal layer, an N-type region, a P-type region, a top oxide layer, contact holes, silicon oxide columns, a polysilicon part, a drift region, a substrate, a bottom metal layer, a metal frame, a protective layer, and heat dissipation holes. The silicon carbide MOS prepared in this application not only has excellent electronic component performance itself, but also, due to the additional protective layer in this application, enables the MOS transistor to have the ability to work stably for a long time, effectively avoiding phenomena such as heat generation and bubbling, and MOS transistor explosion and splashing caused by the long-term operation of the MOS transistor, and is suitable for popularization in the field of electronic components.

Description

Technical Field

[0001] The present invention relates to the field of H01L29 / 00 in IPC patent classification, and particularly relates to a high-efficiency and safe silicon carbide MOS transistor and its application. Background Art

[0002] With the rapid development of the semiconductor-related industries in recent years, compared with the first-generation semiconductor materials represented by silicon and germanium used in the previous industries, they have gradually been phased out due to the continuous improvement of usage requirements; while the third-generation semiconductor materials represented by silicon carbide materials, due to their advantages such as wide bandgap, high temperature resistance, and high voltage resistance, have been widely used and studied more and more in recent years, and have greatly improved the performance and quality of semiconductor devices, among which the MOS transistors of the silicon carbide type are the most prominent.

[0003] The prior art (CN201721005486.3) provides a silicon carbide MOS transistor. For the prepared silicon carbide MOS transistor, when a high voltage is applied outside the transistor, a PN junction depletion region is formed between the protection region and the drift region, greatly reducing the leakage current when the MOS transistor is connected to an external high voltage. However, the MOS transistor lacks necessary external protection devices, which makes it easy to form a bursting phenomenon due to heat generation and foaming inside the MOS after long-term use, causing collateral damage to adjacent components.

[0004] Therefore, there is an urgent need for a MOS transistor that not only has excellent usage efficiency but also has excellent heat conduction, heat dissipation, and waterproof functions to solve the above-mentioned existing problems. Summary of the Invention

[0005] To solve the above problems, in the first aspect of the present invention, a high-efficiency and safe silicon carbide MOS transistor is provided, and its structure includes a top metal layer 1, an N-type region 4, a P-type region 5, a top oxide layer 2, a contact hole 3, a silicon oxide column 6, a polysilicon part 8, a drift region 7, a substrate 9, a bottom metal layer 10, a metal frame 11, a protective layer 12, and a heat dissipation hole 13.

[0006] As a preferred solution, the substrate 9 is a silicon carbide substrate; the bottom metal layer 10 is fixedly arranged at the bottom of the silicon carbide substrate; the drift regions 7 are fixedly arranged at the top of the silicon carbide substrate at fixed intervals; the P-type region 4, the N-type region 5, and the top oxide layer 2 are sequentially formed on the top of the drift region.

[0007] As a preferred solution, a trench is provided at the bottom of the top oxide layer 2, passing through the N-type region 5, the P-type region 4 and entering the drift region 7; the trench is fixedly filled with a polysilicon part 8 inside.

[0008] As a preferred solution, silicon oxide columns 6 arranged at fixed intervals are provided on the top of the substrate; the silicon oxide columns 6 penetrate downward from the upper surface of the N-type region 5 through the N-type region 5, the P-type region 4, and the drift region 7 to reach the upper surface of the substrate 9; the trench is arranged inside the silicon oxide column 6.

[0009] As a preferred solution, contact holes 3 are provided between the silicon oxide columns 6; the contact holes 3 penetrate through the top oxide layer 2, the N-type region 5 from top to bottom and enter the P-type region 4.

[0010] As a preferred solution, a top metal layer 1 is provided on the top of the top oxide layer 2; fixed metal frames 11 and protective layers 12 are sequentially provided on the surfaces of the top metal layer 1 and the bottom metal layer 10.

[0011] As a preferred solution, the protective layer 12 is fixed to the metal frame 11 by an embedding method to effectively protect the silicon carbide MOS transistor; the protective layer is also provided with heat dissipation holes 13 at fixed intervals.

[0012] As a preferred solution, the raw materials of the protective layer include the following components in parts by mass: 80-140 parts of a polymer resin, 5-10 parts of an antioxidant, 20-40 parts of a filler, and 5-20 parts of a functional additive.

[0013] As a preferred solution, the polymer resin is at least one of a polyolefin resin, a silicone resin, an epoxy resin, a polyvinyl alcohol resin, and an acetal resin.

[0014] As a preferred solution, the polymer resin is a mixture of a polyolefin resin and a polyvinyl alcohol resin.

[0015] As a preferred solution, the polyolefin resin is a polyethylene resin; the average molecular weight of the polyvinyl alcohol resin is 220,000-250,000.

[0016] As a preferred solution, the mass ratio of the polyolefin resin to the polyvinyl alcohol resin is 3-4:1-2.

[0017] As a preferred solution, the mass ratio of the polyolefin resin to the polyvinyl alcohol resin is 3:2.

[0018] As a preferred solution, the antioxidant is a mixture of a phenolic antioxidant and a hindered amine antioxidant.

[0019] As a preferred solution, the antioxidant is p-phenylenediamine and hydroquinone.

[0020] As a preferred solution, the mass ratio of p-phenylenediamine to hydroquinone is 1-3:1-2.

[0021] As a preferred embodiment, the mass ratio of p-phenylenediamine to hydroquinone is 2:1.5.

[0022] As a preferred embodiment, the filler is at least one of zinc oxide, titanium dioxide, bentonite, diatomaceous earth, mica powder, silicon carbide, and carbon materials.

[0023] As a preferred embodiment, the mica powder is sericite powder.

[0024] As a preferred embodiment, the average fineness of the sericite powder is 8000 - 10000 mesh.

[0025] As a preferred embodiment, the filler is a mixture of zinc oxide, graphene, and mica powder; the mass ratio of zinc oxide, graphene, and mica powder is 1 - 2:1 - 2:3 - 4.

[0026] As a preferred embodiment, the mass ratio of zinc oxide, graphene, and mica powder is 2:1:3.5.

[0027] As a preferred embodiment, the functional additives are at least one of ultraviolet absorption agents, flame retardants, hydrolysis resistant agents, antistatic agents, and waterproof agents.

[0028] As a preferred embodiment, the functional additives at least include the hydrolysis resistant agent SW - 100.

[0029] The second aspect of the present invention provides an application of the above - mentioned high - efficiency and safe silicon carbide MOS transistor, including the application of the silicon carbide MOS transistor in electronic components.

[0030] Beneficial effects:

[0031] 1. A MOS transistor material prepared by the present application, in addition to having excellent electronic component performance itself, can also have a long - term stable working ability due to the additional protective layer in the present application, effectively avoiding the phenomena of heat - induced bubbling and MOS transistor explosion and splashing caused by the long - term operation of the MOS transistor.

[0032] 2. A MOS transistor material prepared by the present application, through the synergistic effect of p - phenylenediamine and hydroquinone at a mass ratio of 2:1.5, can not only effectively form a synergistic antioxidant effect, but also promote regeneration with each other, thus avoiding the decline of antioxidant properties during long - term use; and on the other hand, it can reduce the number of free electrons in the protective layer system and reduce the group migration rate.

[0033] 3. A MOS transistor material prepared by the present application, through the synergistic effect of zinc oxide, graphene and sericite powder in a mass ratio of 2:1:3.5, can not only effectively conduct the heat energy inside the MOS transistor, but also form good gas permeability through the synergistic effect of the resin material and sericite powder with a specific fineness, reduce the generation of bubbles inside the MOS, and ensure good waterproof performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic side sectional view of the silicon carbide MOS transistor in the present application.

[0035] In the figure:

[0036] 1 - Top metal layer, 2 - Top oxide layer, 3 - Contact hole, 4 - P-type region, 5 - N-type region, 6 - Silicon oxide column, 7 - Drift region, 8 - Polysilicon part, 9 - Substrate, 10 - Bottom metal layer, 11 - Metal frame, 12 - Protective layer, 13 - Heat dissipation hole. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] Example 1

[0038] As Figure 1 shown, in the first aspect of Embodiment 1, an efficient and safe silicon carbide MOS transistor is provided, and the structure includes a top metal layer 1, an N-type region 4, a P-type region 5, a top oxide layer 2, a contact hole 3, a silicon oxide column 6, a polysilicon part 8, a drift region 7, a substrate 9, a bottom metal layer 10, a metal frame 11, a protective layer 12, and a heat dissipation hole 13.

[0039] Among them, the substrate 9 is a silicon carbide substrate; a bottom metal layer 10 is fixedly arranged at the bottom of the silicon carbide substrate; drift regions 7 arranged at fixed intervals are provided on the top of the silicon carbide substrate; a P-type region 4, an N-type region 5, and a top oxide layer 2 are sequentially formed on the top of the drift region.

[0040] A trench passing through the N-type region 5, the P-type region 4 and entering the drift region 7 is provided at the bottom of the top oxide layer 2; a polysilicon part 8 is fixedly filled inside the trench.

[0041] Silicon oxide columns 6 arranged at fixed intervals are provided on the top of the substrate; the silicon oxide columns 6 extend from the upper surface of the N-type region 5 downward through the N-type region 5, the P-type region 4, and the drift region 7 to the upper surface of the substrate 9; the trench is arranged inside the silicon oxide columns 6.

[0042] Contact holes 3 are formed between the silicon oxide columns 6; the contact holes 3 pass through the top oxide layer 2, the N-type region 5 from top to bottom and enter the P-type region 4.

[0043] A top metal layer 1 is provided on the top of the top oxide layer 2; fixed metal frames 11 and protective layers 12 are sequentially provided on the surfaces of the top metal layer 1 and the bottom metal layer 10.

[0044] The protective layer 12 is fixed to the metal frame 11 by an embedding method to effectively protect the silicon carbide MOS transistor; the protective layer is also provided with heat dissipation holes 13 at fixed intervals.

[0045] The raw materials of the protective layer, by mass, include the following components: 100 parts of polymer resin, 8 parts of antioxidant, 35 parts of filler, and 5 parts of functional additive.

[0046] Among them, the polymer resin is a mixture of polyethylene resin and polyvinyl alcohol resin, and the mass ratio is 3:2; the average molecular weight of the polyvinyl alcohol resin is 240,000.

[0047] The antioxidant is p-phenylenediamine and hydroquinone, and the mass ratio is 2:1.5.

[0048] The filler is a mixture of zinc oxide, graphene and sericite powder, and the mass ratio is 2:1:3.5; the average fineness of the sericite powder is 9000 mesh.

[0049] The functional additive is hydrolysis agent SW-100.

[0050] In this embodiment, the polyethylene resin is purchased from the DK4 model polyethylene resin product sold by Zhejiang Fenghong New Materials Co., Ltd.

[0051] In this embodiment, the polyvinyl alcohol resin is purchased from the high-viscosity grade polyvinyl alcohol product sold by Shandong Kepu Chemical Co., Ltd.

[0052] In this embodiment, the sericite powder is purchased from the sericite powder product sold by Chuzhou Baota Sericite Mining Co., Ltd. and has been ground twice to the specified fineness.

[0053] In this embodiment, the graphene is purchased from the graphene product sold by Henan Wanshan New Materials Technology Co., Ltd.

[0054] Example 2

[0055] The specific implementation manner of this embodiment is the same as that of Embodiment 1, the difference is that: the mass ratio of zinc oxide, graphene and sericite powder is 1:1.5:4.

[0056] Example 3

[0057] The specific implementation manner of this embodiment is the same as that of Embodiment 1, the difference is that: the mass ratio of the mixture of polyethylene resin and polyvinyl alcohol resin is 4:1.5.

[0058] Comparative Example 1

[0059] The specific implementation manner of this comparative example is the same as that of Example 1, except that: the mass ratio of zinc oxide, graphene and sericite powder is 1:1:1.

[0060] Comparative Example 2

[0061] The specific implementation manner of this comparative example is the same as that of Example 1, except that: the mixture of polyethylene resin and polyvinyl alcohol resin, with a mass ratio of 6:1.

[0062] Performance Evaluation

[0063] 1. Hydrophobic property: The protective layer materials prepared in the examples and comparative examples were sampled and tested. The sample specifications were 2 cm × 2 cm × 2 cm. The surface water contact angle of the samples was tested by the sessile drop method. The test water droplet volume was 4 μL, and the angle measurement time was 10 minutes. 10 specimens were tested for each example and comparative example, and the average value of the measured values was recorded in Table 1.

[0064] 2. Protective property: The MOS transistors prepared in the examples and comparative examples were used at the normal rated power, maintaining the use temperature at room temperature and the relative humidity at 60%. They were continuously operated for 500 hours, and it was observed whether there was any explosion phenomenon. If there was, it was considered unqualified. 100 specimens were tested for each example and comparative example. If less than or equal to 5 specimens were unqualified, it was recorded as A; if less than or equal to 15 specimens were unqualified, it was recorded as B; if more than 15 specimens were unqualified, it was recorded as C. The measured results were recorded in Table 1.

[0065] Table 1

[0066]

[0067]

[0068] It can be known from Examples 1 to 3, Comparative Examples 1 to 2 and Table 1 that the present invention provides a highly efficient and safe silicon carbide MOS transistor and its application. The silicon carbide MOS prepared in this application not only has excellent electronic component performance itself, but also can make the MOS transistor have long-term stable working ability because of the additional protective layer in this application, and can effectively avoid the phenomena of heat generation and bubbling, and explosion and splashing of the MOS transistor caused by the long-term operation of the MOS transistor. It is suitable for popularization in the field of electronic components and has broad development prospects. Among them, Example 1 obtained the best performance index under the best preparation raw material ratio and structure and other factors.

Claims

1. An efficient and safe silicon carbide MOS transistor, characterized in that: The structure includes a top metal layer, an N-type region, a P-type region, a top oxide layer, contact holes, silicon oxide columns, a polysilicon portion, a drift region, a substrate, a bottom metal layer, a metal frame, a protective layer, and heat dissipation holes; The raw materials of the protective layer, by mass, include the following components: 80-140 parts of a polymer resin, 5-10 parts of an antioxidant, 20-40 parts of a filler, and 5-20 parts of a functional additive; The polymer resin is a mixture of a polyethylene resin and a polyvinyl alcohol resin; The mass ratio of the polyethylene resin to the polyvinyl alcohol resin is 3-4:1-2; The average molecular weight of the polyvinyl alcohol resin is 220,000-250,000; The filler is a mixture of zinc oxide, graphene, and mica powder; the mass ratio of the zinc oxide, graphene, and mica powder is 1-2:1-2:3-4; The mica powder is sericite powder; The average fineness of the sericite powder is 8,000-10,000 mesh; The antioxidant is p-phenylenediamine and hydroquinone; the mass ratio of the p-phenylenediamine to the hydroquinone is 1-3:1-2.

2. The high-efficiency and safe silicon carbide MOS transistor according to claim 1, wherein: The substrate is a silicon carbide substrate; a bottom metal layer is fixedly arranged at the bottom of the silicon carbide substrate; a drift region arranged at fixed intervals is provided at the top of the silicon carbide substrate; a P-type region, an N-type region, and a top oxide layer are sequentially formed at the top of the drift region.

3. The high-efficiency and safe silicon carbide MOS transistor according to claim 2, wherein: A trench passing through the N-type region, the P-type region and entering the drift region is provided at the bottom of the top oxide layer; a polysilicon portion is fixedly filled inside the trench.

4. The high-efficiency and safe silicon carbide MOS transistor according to claim 3, characterized in that: Silicon oxide columns arranged at fixed intervals are provided at the top of the substrate; the silicon oxide columns extend from the upper surface of the N-type region downward through the N-type region, the P-type region and the drift region to the upper surface of the substrate; the trench is arranged inside the silicon oxide column.

5. The high-efficiency and safe silicon carbide MOS transistor according to claim 4, wherein: Contact holes are formed between the silicon oxide columns; the contact holes pass through the top oxide layer, the N-type region and enter the P-type region from top to bottom.

6. The high-efficiency and safe silicon carbide MOS transistor according to claim 5, wherein: A top metal layer is provided at the top of the top oxide layer; a fixed metal frame and a protective layer are sequentially provided on the surfaces of the top metal layer and the bottom metal layer.

7. The high-efficiency and safe silicon carbide MOS transistor according to claim 6, characterized in that: The protective layer is fixed to the metal frame by an embedding method to effectively protect the silicon carbide MOS transistor; the protective layer is also provided with heat dissipation holes at fixed intervals.

8. The application of the high-efficiency and safe silicon carbide MOS transistor according to any one of claims 1 to 7, characterized in that: It includes the application of the silicon carbide MOS transistor in electronic components.

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