Semiconductor devices and their manufacturing methods

Abstract

Embodiments of the present invention provide a semiconductor device and a method thereof capable of improving both thermal stability and contact resistance. According to one embodiment of the present invention, a semiconductor device may include: a contact plug on a substrate, wherein the contact plug includes: a silicide layer having a varying carbon content within the silicide layer, and a metal material layer on the silicide layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0063227, filed on May 17, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more specifically, to a semiconductor device including a contact plug and a method for manufacturing the same. Background Technology

[0004] In the fabrication of contact structures for semiconductor devices, ohmic contacts are formed to suppress leakage current and increase contact resistance. As a known technique, a silicide layer is formed to create the ohmic contact. Summary of the Invention

[0005] Various embodiments of the present invention provide a semiconductor device capable of improving both thermal stability and contact resistance. Various embodiments of the present invention provide a method for manufacturing a contact plug for a semiconductor device, and a semiconductor device including the contact plug.

[0006] According to one embodiment of the present invention, a semiconductor device includes: a contact plug on a substrate, wherein the contact plug includes: a silicide layer having a varying carbon content in the silicide layer, and a metal material layer on the silicide layer.

[0007] According to another embodiment of the present invention, a semiconductor device includes: a gate structure on a substrate; source / drain regions formed in the substrate on both sides of the gate structure; and a contact plug on the source / drain regions, wherein the contact plug includes: a silicide layer having a varying carbon content in the silicide layer, and a metal material layer on the silicide layer.

[0008] According to one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a plurality of silicon carbide layers on a substrate, each of the plurality of silicon carbide layers having a different carbon content from the others; forming a metal material layer on the plurality of silicon carbide layers; and forming a contact plug by reacting the plurality of silicon carbide layers with the metal material layer via heat treatment, wherein a silicide layer and a metal material layer are stacked in the contact plug.

[0009] This invention improves the reliability of semiconductor devices by promoting the formation of silicides in the portion of the semiconductor device that contacts the contact plug and suppressing the excessive growth of silicides in the portion that contacts the substrate, thereby ensuring both thermal stability and contact resistance. Attached Figure Description

[0010] Figure 1 This is a view showing a contact plug according to an embodiment of the present invention.

[0011] Figure 2A and Figure 2B This is a view illustrating a method for manufacturing a contact plug according to an embodiment of the present invention.

[0012] Figure 3 This is a view illustrating a semiconductor device according to an embodiment of the present invention.

[0013] Figure 4 This is a view illustrating a semiconductor device according to another embodiment of the present invention.

[0014] Figures 5A to 5E This is a view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0015] Various embodiments are described herein with reference to cross-sectional views, plan views, and block diagrams that are schematic diagrams of the invention. Therefore, the structure of the drawings can be modified by manufacturing techniques and / or tolerances. These embodiments of the invention are not limited to the specific structures shown in the drawings, but may include any variations in the structure that may result from manufacturing processes. Furthermore, the shapes of any regions and areas shown in the schematic drawings are intended to illustrate specific examples of the structure of the regions of various elements and are not intended to limit the scope of the invention.

[0016] Figure 1 This is a view showing a contact plug according to an embodiment of the present invention.

[0017] like Figure 1As shown, a contact plug comprising a silicide layer 104 and a metal material layer 103 can be formed on substrate 101. The silicide layer 104 and the metal material layer 103 can be stacked on top of each other to form a stack disposed on substrate 101. The silicide layer 104 can have a varying carbon content. The carbon content of the silicide layer 104 can vary depending on its distance from the outermost surface of the silicide layer 104. Substrate 101 can include various doping configurations according to manufacturing specifications. Substrate 101 can include other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Substrate 101 can include compound semiconductors and / or alloy semiconductors. Substrate 101 can include a group III-V semiconductor substrate. Substrate 101 can include a compound semiconductor substrate such as gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Substrate 101 can include an SOI (silicon-on-insulator) substrate. The substrate 101 may include conductive regions, such as impurity-doped wells and impurity-doped channels, or impurity-doped structures.

[0018] The silicide layer 104 may contact the substrate 101. The substrate 101 in contact with the silicide layer 104 may be a region doped with impurities. The silicide layer 104 may include a metal silicide. The silicide layer 104 may be applied to prevent contamination and deep-level impurity problems caused by direct contact between the metal material layer 103 forming the contact plug and the substrate 101. Therefore, since a metal with a much lower resistance than silicon can be used as the contact material, excellent contact characteristics can be ensured, and device characteristics and reliability can be improved.

[0019] like Figure 1 As shown in the view, the carbon content of the silicide layer increases from the interface with the metal material layer to the interface with the substrate. The silicide layer 104 can have a higher carbon content in the portion closer to the substrate 101. The carbon content of the silicide layer 104 can be highest at the interface with the substrate 101. The carbon content of the silicide layer 104 can be lowest at the interface with the metal material layer 103.

[0020] At the interface with substrate 101, the carbon content in silicide layer 104 can be similar to the metal content. At the interface with substrate 101, the silicon content in silicide layer 104 can be significantly higher than the carbon and metal contents. Therefore, Si-C bonding can be formed at the interface with substrate 101, thereby ensuring the thermal stability of the semiconductor device.

[0021] At the interface with substrate 101, the carbon content in silicide layer 104 can be adjusted to be no higher than the metal content in silicide layer 104. This adjustment is to prevent the formation of unintended material layers and to prevent a sharp increase in resistance that may occur when the carbon content in silicide layer 104 is higher than the metal content. Furthermore, even during the high-temperature heat treatment essential during semiconductor processing, overgrowth of silicide layer 104 can be suppressed.

[0022] In the silicide layer 104, the thickness of the portion with similar carbon and metal content can be adjusted to be smaller than the thickness of the portion with a higher metal content than carbon content. In the silicide layer 104, the ratio of the thickness of the portion with a higher metal content than carbon content to the thickness of the portion with similar carbon and metal content can be adjusted to be greater than 4:1. In the silicide layer 104, the thickness of the portion with similar carbon and metal content can be adjusted to be less than... This is because when the thickness of the portion of the silicide layer 104 with a carbon content similar to that of the metal content is greater than... At that time, it may be difficult to inject dopants. In addition, because the metal content is higher than the carbon content in most parts of the silicide layer 104, the resistance improvement effect of the silicide layer 104 can be maintained.

[0023] The metal material layer 103 can be used as a contact material. Because the specific resistance of metal is approximately 1000 times lower than that of silicon, using a metal material as a contact material is more advantageous than using silicon. Furthermore, since dopant ion implantation is not required, there is no dopant diffusion from the contact plug to the substrate 101. Therefore, the influence of dopant on refresh characteristics can be eliminated. The metal material layer 103 may include a metal material capable of forming silicides. The metal material layer 103 may include metals capable of forming silicides, such as titanium (Ti), ruthenium (Ru), molybdenum (Mo), cobalt (Co), nickel (Ni), tantalum (Ta), and nickel-platinum (NiPt), but the invention is not limited thereto.

[0024] Figure 2A and Figure 2B This is a view illustrating a method for manufacturing a contact plug according to an embodiment of the present invention. Figure 2A and Figure 2B Including with Figure 1 The same substrate 101 and metal material layer 103 are shown. The description of substrate 101 and metal material layer 103 can be omitted below.

[0025] like Figure 2AAs shown, a plurality of silicon carbide layers 102 with different carbon contents can be formed on substrate 101. Each of the plurality of silicon carbide layers 102 can be formed to have the same thickness. In another embodiment, each of the plurality of silicon carbide layers 102 can have different thicknesses from each other. According to this embodiment, a stack of five silicon carbide layers 102 is shown. However, the invention is not limited thereto and stacks of more than five silicon carbide layers 102 can be formed.

[0026] like Figure 2A As shown in the graph, the silicon content in the multiple silicon carbide layers 102 increases as they approach the substrate 101, while the carbon content in the multiple silicon carbide layers 102 increases as they approach the metal material layer 103. That is, among the multiple silicon carbide layers 102, the silicon carbide layer 102 closest to the substrate 101 can have the highest silicon content, while the silicon carbide layer 102 closest to the metal material layer 103 can have the highest carbon content.

[0027] Multiple silicon carbide layers 102 can be formed by sputtering, but the present invention is not limited thereto. The sputtering process can be performed using a dual target, a dual-material target, or a dual-material / dual-target method. A dual target uses two materials as the sputtering target and can include silicon (Si) and carbon (C). A dual-material target uses a single material as the sputtering target, but the single material can contain both silicon and carbon. In a dual-material / dual-target method, two materials, including both silicon and carbon, can be used in combination. In this case, the two materials can have different carbon and silicon composition ratios. According to embodiments, the sputtering process for forming multiple silicon carbide layers 102 can be performed by varying the power, pressure, and stack thickness.

[0028] like Figure 2B As shown, a silicide layer 104 can be formed between the substrate 101 and the metal material layer 103 by performing heat treatment.

[0029] The silicon carbide layer 102 can be heat-treated to form a silicon carbide layer with Figure 2B A silicide layer 104 is formed by a reaction between metals within the shown metal material layer 103. The silicide layer 104 may comprise a metal silicide. The silicide layer 104 can be applied to prevent contamination and deep-level impurity problems caused by direct contact between the metal material layer 103 forming the contact plug and the substrate 101. Therefore, since a metal with a much lower resistance than silicon can be used as the contact material, excellent contact characteristics can be ensured, and device characteristics and reliability can be improved.

[0030] like Figure 2BAs shown in the graph, the silicide layer 104 can have a higher carbon content in the portion closer to the substrate 101. The carbon content in the silicide layer 104 can be highest at the interface with the substrate 101. The silicide layer 104 can have the lowest carbon content at the interface with the metal material layer 103.

[0031] At the interface with substrate 101, the silicide layer 104 can have a carbon content similar to that of the metal. At the interface with substrate 101, the silicon content in the silicide layer 104 can be significantly higher than the carbon and metal contents. Therefore, Si-C bonding can be formed at the interface with substrate 101, thereby ensuring the thermal stability of the semiconductor device.

[0032] At the interface with substrate 101, the carbon content in silicide layer 104 can be adjusted to be no higher than the metal content in silicide layer 104. This adjustment is made to prevent the formation of unintended material layers and to prevent a sharp increase in resistance that could occur if the carbon content in silicide layer 104 is higher than the metal content. Furthermore, overgrowth of silicide layer 104 can be suppressed even during the high-temperature heat treatment essential during semiconductor processing.

[0033] In the silicide layer 104, the thickness of the portion with similar carbon and metal content can be adjusted to be smaller than the thickness of the portion with a higher metal content than carbon content. In the silicide layer 104, the ratio of the thickness of the portion with a higher metal content than carbon content to the thickness of the portion with similar carbon and metal content can be adjusted to be greater than 4:1. In the silicide layer 104, the thickness of the portion with similar carbon and metal content can be adjusted to be less than... That's because when the thickness of the portion with a carbon content similar to that of the metal content is greater than... At that time, it may be difficult to implant dopants into the silicide layer 104. In addition, because the metal content is higher than the carbon content in most parts of the silicide layer 104, the resistance improvement effect of the silicide layer 104 can be maintained.

[0034] Figure 3 This is a view illustrating a semiconductor device according to an embodiment of the present invention.

[0035] refer to Figure 3 The semiconductor device may include: a gate structure GST formed on a substrate 201; source / drain regions 204 formed in the substrate 201 on both sides of the gate structure GST; an interlayer dielectric layer 215 covering the upper part of the substrate 201 (including the gate structure GST); a silicide layer 216 penetrating the interlayer dielectric layer 215 and connected to the source / drain regions 204; and a metal material layer 217 formed on the silicide layer 216.

[0036] Substrate 201 may include a semiconductor substrate such as a silicon substrate. Substrate 201 may be formed of a silicon-containing material. Depending on the manufacturing specifications, substrate 201 may include various doping configurations. Substrate 201 may include other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Substrate 201 may include compound semiconductors and / or alloy semiconductors. Substrate 201 may include a group III-V semiconductor substrate. Substrate 201 may include a compound semiconductor substrate such as gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Substrate 201 may include an SOI (silicon-on-insulator) substrate. Substrate 201 may include conductive regions such as impurity-doped wells and impurity-doped channels, or impurity-doped structures.

[0037] Substrate 201 may include an active region 203 defined by device isolation layer 202. Device isolation layer 202 may be formed using a shallow trench isolation (STI) process. For example, after a trench is formed on substrate 201, a dielectric material may fill the trench. Device isolation layer 202 may include silicon oxide, silicon nitride, or a combination thereof.

[0038] The gate structure GST may include: a stacked structure of a gate dielectric layer 211, a gate electrode 212, and a gate hard mask 213; and a gate spacer 214 formed on the sidewalls of the stacked structure. The gate dielectric layer 211 may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k material. The gate electrode 212 may include a silicon-containing material or a metal-containing material. The gate electrode 212 may include, for example, polysilicon, tungsten, tungsten silicide, titanium nitride, tantalum nitride, or combinations thereof. The gate electrode 212 may include doped polysilicon, i.e., doped polysilicon. The impurities may include N-type impurities or P-type impurities. The impurities may include boron, arsenic, or combinations thereof. The gate hard mask 213 may include a dielectric material. The gate hard mask 213 may include, for example, silicon nitride. The gate spacer 214 may include a dielectric material. The gate spacer 214 may include, for example, silicon nitride.

[0039] The source / drain region 204 can be formed on the substrate 201 on both sides of the gate structure GST. The source / drain region 204 can be doped with the same impurities. The source / drain region 204 can include N-type or P-type impurities. The source / drain region 204 can be a region doped with a high content of impurities.

[0040] The interlayer dielectric layer 215 may include a low-k material. The interlayer dielectric layer 215 may include, for example, a low-k material selected from silicon oxide, silicon nitride, or including silicon carbide and boron.

[0041] The silicide layer 216 can have the same properties as... Figure 1The silicide layer 104 has the same configuration. That is, the silicide layer 216 can have the same configuration as... Figure 1 The silicide layer 104 has the same carbon content as the substrate 201. The silicide layer 216 can contact the source / drain region 204. The silicide layer 216 may include a metal silicide. The silicide layer 216 can be applied to prevent contamination and deep-level impurity problems caused by direct contact between the metal material layer 217 forming the contact plug and the substrate 201. Therefore, since a metal with a much lower resistance than silicon can be used as the contact material, excellent contact characteristics can be ensured, and device characteristics and reliability can be improved.

[0042] The carbon content in the silicide layer 216 can increase as the silicide layer approaches the substrate 201. The carbon content in the silicide layer 216 can be highest at the interface with the substrate 201. The carbon content in the silicide layer 216 can be lowest at the interface with the metal material layer 217.

[0043] The carbon content in the silicide layer 216 at the interface with substrate 201 can be similar to the metal content in the silicide layer 216. At the interface with substrate 201, the silicon content in the silicide layer 216 can be significantly higher than the carbon and metal content. Therefore, Si-C bonding can be formed at the interface with substrate 201, and as a result, the thermal stability of the semiconductor device can be ensured.

[0044] The carbon content in the silicide layer 216 at the interface with the substrate 201 can be adjusted to be no higher than the metal content in the silicide layer 216. This is because when the carbon content in the silicide layer 216 is higher than the metal content, an unintended material layer may form, and the resistance may increase sharply. Furthermore, even during the high-temperature heat treatment essential during semiconductor processing, excessive growth of the silicide layer 216 can be suppressed.

[0045] In the silicide layer 216, the thickness of the portion having a carbon content similar to the metal content can be adjusted to be less than the thickness of the portion having a metal content greater than the carbon content. In the silicide layer 216, the ratio of the thickness of the portion having a metal content greater than the carbon content to the thickness of the portion having a similar carbon and metal content can be adjusted to at least 4:1 or greater. In the silicide layer 216, the thickness of the portion having a similar carbon and metal content can be adjusted to be less than... This is because when the thickness of the portion of the silicide layer 216 with similar carbon and metal content is... At or above this level, it may be difficult to inject dopants. Furthermore, because the metal content is higher than the carbon content in most portions of the silicide layer 216, the resistance-improving effect of the silicide layer 216 can be maintained.

[0046] The metal material layer 217 can be used as a contact material. Because the resistivity of metal is approximately 1000 times lower than that of silicon, using a metal material as a contact material is more advantageous in terms of resistance than using silicon. Furthermore, since dopant ion implantation is not required, there is no dopant diffusion from the contact plug to the substrate 201, and therefore, the influence of dopant on refresh characteristics can be eliminated. The metal material layer 217 may include a metal material capable of forming silicides. For example, the metal material layer 217 may include metals capable of forming silicides, such as titanium (Ti), ruthenium (Ru), molybdenum (Mo), cobalt (Co), nickel (Ni), tantalum (Ta), and nickel-platinum (NiPt), but the invention is not limited thereto.

[0047] Figure 4 This is a view illustrating a semiconductor device according to another embodiment of the present invention.

[0048] refer to Figure 4 The semiconductor device may include a vertical gate structure. The vertical gate structure may include a vertical channel 301 and gate electrodes 302 spaced apart from both sides of the vertical channel 301. A contact plug includes a silicide layer 303 with varying carbon content and a metal material layer 304 stacked on the silicide layer. The contact plug may contact both ends of the vertical channel 301. The two ends of the vertical channel 301 in contact with the silicide layer 303 may include impurity-doped regions. The silicide layer 303 may be, for example, similar to... Figure 1 The silicide layer 104 is a metal silicide layer. The silicide layer 303 can have a metal silicide layer with... Figure 1 The silicide layer 104 has the same configuration. That is, the silicide layer 303 can have the same configuration as... Figure 1 The carbon content of the silicide layer 104 varies with the same carbon content.

[0049] Figures 5A to 5E This is a view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0050] like Figure 5A As shown, the gate structure GST can be formed on the substrate 11. The gate structure GST can be formed on the active region 13 of the substrate 11. The active region 13 can be defined by the device isolation layer 12.

[0051] Substrate 11 may include a semiconductor substrate such as a silicon substrate. Substrate 11 may be made of a silicon-containing material. Depending on the manufacturing specifications, substrate 11 may include various doping configurations. Substrate 11 may include germanium, silicon carbide (SiC), silicon germanium (SiGe), or other semiconductors such as diamond. Substrate 11 may include compound semiconductors and / or alloy semiconductors. Substrate 11 may include a group III-V semiconductor substrate. Substrate 11 may include a compound semiconductor substrate such as gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Substrate 11 may include a silicon-on-insulator (SOI) substrate. Substrate 11 may include conductive regions, such as impurity-doped wells and impurity-doped channels, or structures doped with impurities.

[0052] The device isolation layer 12 can be formed using a shallow trench isolation (STI) process. For example, after forming trenches in the substrate 11, the trenches can be filled with a dielectric material. The device isolation layer 12 may include, for example, silicon oxide, silicon nitride, or combinations thereof.

[0053] The gate structure GST may include: a stacked structure of a gate dielectric layer 21, a gate electrode 22, and a gate hard mask 23; and a gate spacer 24 formed on the sidewalls of the stacked structure. The gate structure GST can be formed by the following series of processes: sequentially stacking a gate dielectric material, a gate electrode material, and a gate hard mask material on a substrate 11; forming a mask pattern on the gate hard mask material; sequentially etching the gate hard mask material, the gate electrode material, and the gate dielectric material using the mask pattern as an etching mask to form the stacked structure; and forming the gate spacer 24 on the two sidewalls of the stacked structure.

[0054] The gate dielectric layer 21 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k material. The gate electrode 22 may include a silicon-containing material or a metal-containing material. The gate electrode 22 may include, for example, polysilicon, tungsten, tungsten silicide, titanium nitride, tantalum nitride, or combinations thereof. The gate electrode 22 may include doped polysilicon, i.e., doped polysilicon. The impurities may include N-type or P-type impurities. The impurities may include boron, arsenic, or combinations thereof. The gate hard mask 23 may include a dielectric material. The gate hard mask 23 may include, for example, silicon nitride. The gate spacer 24 may include a dielectric material. The gate spacer 24 may include, for example, silicon nitride.

[0055] Then, source / drain regions 14 can be formed by doping the substrate 11 on both sides of the gate structure GST with impurities. Source / drain regions 14 may include N-type or P-type impurities. Source / drain regions 14 may be regions doped with a high content of impurities.

[0056] like Figure 5BAs shown, an interlayer dielectric layer 25 can be formed covering the upper portion of the substrate 11 (including the gate structure GST). The interlayer dielectric layer 25 can serve as an isolation layer that separates adjacent gate structures GST, separates the gate structure GST from other conductive structures formed at the same level as the gate structure GST, and separates the gate structure GST from other conductive structures formed at the upper level of the gate structure GST.

[0057] The interlayer dielectric layer 25 may include a low-k material. The interlayer dielectric layer 25 may include, for example, a low-k material selected from silicon oxide, silicon nitride, or including silicon carbide and boron.

[0058] like Figure 5C As shown, mask pattern 26 can be formed on interlayer dielectric layer 25. Mask pattern 26 may include a material with etching selectivity relative to interlayer dielectric layer 25. Mask pattern 26 may be formed from photoresist layer.

[0059] Then, the mask pattern 26 can be used as an etching mask to etch the interlayer dielectric layer 25. Thus, an opening region 27 can be formed that penetrates the interlayer dielectric layer 25 and exposes the source / drain region 14.

[0060] like Figure 5D As shown, a contact plug can be formed by filling the gap in the opening region 27. The contact plug includes a plurality of silicon carbide layers 28 and a metal material layer 29 formed on the plurality of silicon carbide layers 28.

[0061] Multiple silicon carbide layers 28 can be formed on the source / drain regions 14 exposed by the opening region 27. Each of the multiple silicon carbide layers 28 can have a different carbon content. Figure 5D Multiple silicon carbide layers 28 can have the same characteristics as Figure 2A The configuration is the same as the previous one.

[0062] Each of the plurality of silicon carbide layers 28 may be formed to have the same thickness. In another embodiment, each of the plurality of silicon carbide layers 28 may have a different thickness from each other. Although the plurality of silicon carbide layers 28 is shown as comprising five layers, the invention is not limited thereto.

[0063] The silicon (Si) content in the multiple silicon carbide layers 28 increases as the silicon carbide layer approaches the substrate 11, and the carbon (C) content increases as the silicon carbide layer approaches the metal material layer 29. That is, among the multiple silicon carbide layers 28, the silicon carbide layer 28 closest to the substrate 11 can have the highest silicon content, while the silicon carbide layer 28 closest to the metal material layer 29 can have the highest carbon content.

[0064] Multiple silicon carbide layers 28 can be formed by sputtering, but the invention is not limited thereto. The sputtering process can be performed using one of the following: dual-target, dual-material target, or dual-material / dual-target. A dual-target uses two materials as the sputtering target and may include silicon (Si) and carbon (C). A dual-material target uses a single material as the sputtering target, but the single material may contain both silicon and carbon. In a dual-material / dual-target, both materials, including silicon and carbon, can be used, and in this case, the two materials may have different carbon and silicon composition ratios. According to embodiments, the sputtering process for forming multiple silicon carbide layers 28 can be performed by varying the power, pressure, and stack thickness.

[0065] The metal material layer 29 may include a metal material capable of forming silicides. For example, the metal material layer 29 may include metals that form silicides, such as titanium (Ti), ruthenium (Ru), molybdenum (Mo), cobalt (Co), nickel (Ni), tantalum (Ta), and nickel-platinum (NiPt), but the invention is not limited thereto.

[0066] like Figure 5E As shown, a silicide layer 30 can be formed between the substrate 11 and the metal material layer 29 by performing heat treatment.

[0067] It can be obtained through heat treatment Figure 5D A silicide layer 30 is formed by the reaction between the silicon carbide layer 28 and the metal in the metal material layer 29. The silicide layer 30 may include metal silicides. The silicide layer 30 can be applied to prevent contamination and deep-level impurity problems caused by direct contact between the metal material layer 29 forming the contact plug and the substrate 11. Therefore, since a metal with a much lower resistance than silicon can be used as the contact material, excellent contact characteristics can be ensured, and device characteristics and reliability can be improved.

[0068] The carbon content in the silicide layer 30 can increase as the silicide layer approaches the substrate 11. The carbon content in the silicide layer 30 can be highest at the interface with the substrate 11. The carbon content in the silicide layer 30 can be lowest at the interface with the metal material layer 29.

[0069] At the interface with substrate 11, the carbon content in silicide layer 30 can be similar to the metal content in silicide layer 30. At the interface with substrate 11, the silicon content in silicide layer 30 can be significantly higher than the carbon and metal content (see reference). Figure 1 Therefore, Si-C bonding can be formed at the interface with substrate 11, and as a result, the thermal stability of the semiconductor device can be ensured.

[0070] At the interface with the substrate 11, the carbon content in the silicide layer 30 can be adjusted to be no higher than the metal content. This adjustment is to prevent the formation of unintended material layers and to prevent a sharp increase in resistance that may occur when the carbon content in the silicide layer 30 is higher than the metal content. Furthermore, even during the high-temperature heat treatment essential during semiconductor processing, overgrowth of the silicide layer 30 can be suppressed.

[0071] In the silicide layer 30, the thickness of portions having similar carbon and metal contents can be adjusted to be less than the thickness of portions having a higher metal content than carbon. The ratio of the thickness of the portions having a higher metal content than carbon to the thickness of portions having similar carbon and metal contents in the silicide layer 30 can be adjusted to at least 4:1 or greater. The ratio of the thickness of the portions having similar carbon and metal contents in the silicide layer 30 can be adjusted to be less than... This is because when the thickness of the portion of the silicide layer 30 with similar carbon and metal content is... At or above this level, it may be difficult to inject dopants. Furthermore, because the metal content is higher than the carbon content in most portions of the silicide layer 30, the resistance-improving effect of the silicide layer 30 can be maintained.

[0072] Although the technical features of the present invention have been shown and described with reference to specific embodiments thereof, those skilled in the art should understand that various changes and modifications can be made thereto without departing from the scope of this disclosure.

Claims

1. A semiconductor device, comprising: A contact plug on a substrate, wherein the contact plug comprises: A silicide layer having a varying carbon content within the silicide layer, and A metallic material layer, which is located on top of the silicide layer. Specifically, from the interface with the metal material layer to the interface with the substrate, the carbon content of the silicide layer increases. At the interface with the substrate, the carbon content in the silicide layer does not exceed the metal content. In the silicide layer, the thickness of the portion where the carbon content and metal content are similar is smaller than the thickness of the portion where the metal content is greater than the carbon content.

2. The semiconductor device as claimed in claim 1, wherein, The silicide layer includes metal silicides.

3. The semiconductor device as claimed in claim 2, wherein, The metal silicide includes the same metal material as the metal material layer.

4. The semiconductor device as claimed in claim 1, wherein, The carbon content in the silicide layer is highest at the interface with the substrate.

5. The semiconductor device as claimed in claim 1, wherein, The carbon content in the silicide layer is lowest at the interface with the metal material layer.

6. The semiconductor device of claim 1, wherein, At the interface with the substrate, the silicon content in the silicide layer is greater than the carbon content and the metal content.

7. A semiconductor device, comprising: A gate structure, wherein the gate structure is on a substrate; Source / drain regions are formed in the substrate on both sides of the gate structure; as well as A contact plug, the contact plug being located above the source / drain region. The contact plug includes: A silicide layer having a varying carbon content within the silicide layer, and A metallic material layer, which is located on top of the silicide layer. Specifically, from the interface with the metal material layer to the interface with the substrate, the carbon content of the silicide layer increases. At the interface with the substrate, the carbon content in the silicide layer does not exceed the metal content. In the silicide layer, the thickness of the portion where the carbon content and metal content are similar is smaller than the thickness of the portion where the metal content is greater than the carbon content.

8. The semiconductor device of claim 7, wherein, The silicide layer includes metal silicides.

9. The semiconductor device of claim 8, wherein, The metal silicide includes the same metal material as the metal material layer.

10. The semiconductor device of claim 7, wherein, The carbon content in the silicide layer is highest at the interface with the substrate.

11. The semiconductor device of claim 7, wherein, The carbon content in the silicide layer is lowest at the interface with the metal material layer.

12. The semiconductor device of claim 7, wherein, At the interface with the substrate, the silicon content in the silicide layer is greater than the carbon content and the metal content.

13. A method for manufacturing a semiconductor device, the method comprising: Multiple silicon carbide layers are formed on a substrate, each of the multiple silicon carbide layers having a different carbon content than the others; A metal material layer is formed on the plurality of silicon carbide layers; as well as Contact plugs are formed by reacting the plurality of silicon carbide layers with the metal material layer through heat treatment, wherein silicide layers and metal material layers are stacked in the contact plugs. Specifically, from the interface with the metal material layer to the interface with the substrate, the carbon content of the silicon carbide layer increases. At the interface with the substrate, the carbon content in the silicon carbide layer does not exceed the metal content. In the silicon carbide layer, the thickness of the portion where the carbon content and metal content are similar is smaller than the thickness of the portion where the metal content is greater than the carbon content.

14. The method of claim 13, wherein, The silicon carbide layers have a higher silicon content closer to the substrate and a higher carbon content closer to the metal material layer.

15. The method of claim 13, wherein, Among the plurality of silicon carbide layers, the silicon carbide layer closest to the substrate has the highest silicon content, and among the plurality of silicon carbide layers, the silicon carbide layer closest to the metal material layer has the highest carbon content.

16. The method of claim 13, wherein, The steps of forming the plurality of silicon carbide layers are performed by a sputtering process.

17. The method of claim 16, wherein, The sputtering process is performed using a dual-target system, where each of the silicon and carbon materials is used as the sputtering target.

18. The method of claim 16, wherein, The sputtering process is performed using a dual-material target, wherein the dual-material target uses silicon carbide as the sputtering target.

19. The method of claim 16, wherein, The sputtering process is performed using a dual-material / dual-target method, wherein two silicon carbide materials with different carbon and silicon compositions are used as sputtering targets.

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