Flip chip ball grid array substrate half-addition process

Abstract

The application provides a kind of FCBGA substrate's semi-addition process method, it is related to package substrate manufacturing technical field.The method includes: step S1, in the inner layer circuit surface of package substrate, ABF layer and copper foil are sequentially laminated;Step S2, the ABF layer after lamination is placed in oven and baked to complete pre-curing;Step S3, the ABF layer of pre-curing is vacuum heated and pressurized, so that ABF layer is completely cured;Step S4, remove copper foil, and manufacture outer layer circuit on completely cured ABF layer;Step S5, repeat the above steps S1-S4, form multilayer circuit package substrate.The application can solve the technical problem of large copper skin explosion board, ensure the reliability of the substrate, reduce the process limit, improve the design freedom, reduce the process window, improve the yield, and reduce the substrate warpage.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of packaging substrate manufacturing technology, in particular to a kind of FCBGA substrate's semi-addition process method. BACKGROUND

[0002] Due to the requirement of high-density wiring, the main process method of FCBGA (Flip Chip Ball Grid Array) substrate manufacturing is semi-addition method. Semi-addition method is not only a copper line manufacturing technology problem, but also this technology can usually only use ABF (Ajinomoto Build-up Film) material as the insulating layer. In other words, only ABF material can realize the semi-addition method to manufacture high-density wiring.

[0003] Due to the nature of the material itself, ABF material contains a certain amount of solvent, which, if not removed during substrate manufacturing, will accumulate in the substrate after multiple layers of wiring layers are accumulated. The solvent accumulated in the substrate is prone to cause the substrate to bubble and explode. In the substrate wiring metal layer, continuous large-area copper skin cannot be set, and the area requiring copper skin must be processed with a certain interval of air holes to allow the gas in the ABF layer to be excluded to avoid board explosion. SUMMARY

[0004] In view of the above problems, the present application provides a kind of FCBGA substrate's semi-addition process method, avoid large copper skin to cause board explosion.

[0005] To achieve the above purpose, the present application provides a kind of FCBGA substrate's semi-addition process method, comprising: step S1, on the surface of the inner layer circuit 2 of the packaging substrate, ABF layer 3 and copper foil 4 are sequentially pressed; step S2, the ABF layer 3 after pressing is placed in an oven for baking to complete pre-curing; step S3, vacuum heating and pressurizing is carried out on the pre-cured ABF layer 3 to make the ABF layer 3 completely cured; step S4, remove the copper foil 4, and manufacture the outer layer circuit 9 on the completely cured ABF layer 3; step S5, repeat the above steps S1-S4 to form a multilayer circuit packaging substrate.

[0006] Further, in step S1, before sequentially pressing ABF layer 3 and copper foil 4, it also includes: roughening treatment is carried out on the surface of the inner layer circuit 2.

[0007] Further, in step S2, the ABF layer 3 after pressing is placed in an oven for baking, which includes: first baking at 130℃ for 30min, and then baking at 180℃ for 60min.

[0008] Further, in step S3, the pre-cured ABF layer 3 is vacuum heated and pressurized, including: placing the pre-cured ABF layer 3 in a vacuum condition, under the mirror isolation steel plate clamping of the laminator, through heating and pressurizing, the ABF layer 3 is completely cured.

[0009] Further, the temperature after heating is 190-210℃, and the pressure after pressurizing is greater than 1MPa.

[0010] Further, in step S4, the copper foil 4 is removed, and the outer layer circuit 9 is manufactured on the completely cured ABF layer 3, including: step S41, laser drilling is performed on the completely cured ABF layer 3 and the copper foil 4, so that the blind hole 5 in communication with the inner layer circuit 2 is formed in the ABF layer 3 and the copper foil 4; step S42, removing the laser drilling residue; step S43, removing the surface copper foil 4; step S44, electroless plating copper in the ABF layer 3 and the blind hole 5 to form the electroplating seed layer 6; step S45, photoetching to form a patterned electroplating mask 7 on the electroplating seed layer 6; step S46, electroplating to form a circuit pattern 8 in the area of the electroplating seed layer 6 not covered by the patterned electroplating mask 7 and filling the blind hole 5; step S47, removing the patterned electroplating mask 7; step S48, removing the electroplating seed layer 6 covered by the patterned electroplating mask 7 to form the outer layer circuit 9.

[0011] Further, in step S44, the thickness of the electroplating seed layer 6 is 0.3-1μm.

[0012] Further, after the multi-layer circuit packaging substrate is formed in step S5, a solder resist layer 10 is further formed on the outermost layer of the multi-layer circuit packaging substrate.

[0013] Further, after the solder resist layer 10 is formed, an organic protective film 11 is coated on the area of the outermost layer of the multi-layer circuit packaging substrate not covered by the solder resist layer 10.

[0014] Further, the material of the organic protective film 11 includes any one of NiAu, NiPdAu, OSP, Sn.

[0015] Compared with the prior art, the semi-additive process method of the FCBGA substrate provided by the present application has at least the following beneficial effects:

[0016] (1) The large copper skin does not explode, ensuring the reliability of the substrate;

[0017] (2) Reducing process constraints and improving design freedom;

[0018] (3) Reducing process window and improving yield;

[0019] (4) Reducing substrate warpage. BRIEF DESCRIPTION OF DRAWINGS

[0020] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0021] Figure 1 An operation flow chart of a half-addition process method of the FCBGA substrate according to an embodiment of the present application is schematically shown;

[0022] Figure 2 A process flow chart of a half-addition process method of the FCBGA substrate according to an embodiment of the present application is schematically shown;

[0023] Figure 3 An operation flow chart of a manufacturing process of the outer layer circuit according to an embodiment of the present application is schematically shown;

[0024] Figure 4 A process flow chart of a manufacturing process of the outer layer circuit according to an embodiment of the present application is schematically shown;

[0025] Figure 5 A structure diagram of the multilayer circuit package substrate according to an embodiment of the present application is schematically shown;

[0026] Figure 6 A structure diagram of the solder resist layer according to an embodiment of the present application is schematically shown;

[0027] Figure 7 A structure diagram of the organic protection film according to an embodiment of the present application is schematically shown.

[0028]

BRIEF DESCRIPTION OF DRAWINGS

[0029] 1 - core plate; 2 - inner layer circuit; 3 - ABF layer; 4 - copper foil; 5 - blind hole; 6 - electroplating seed layer; 7 - patterned electroplating mask; 8 - circuit pattern; 9 - outer layer circuit; 10 - solder resist layer; 11 - organic protection film. DETAILED DESCRIPTION

[0030] To make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to specific embodiments and drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0031] The terms used herein are only intended to describe specific embodiments, and are not intended to limit the present application. The terms "comprise", "include" and the like used herein indicate the presence of the stated features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0032] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0033] Figure 1 The schematic diagram illustrates the operation flow of a semi-additive process method for an FCBGA substrate according to an embodiment of the present invention. Figure 2 The diagram illustrates a process flow chart of a semi-additive process for an FCBGA substrate according to an embodiment of the present invention.

[0034] Please see Figure 1 and Figure 2 The semi-additive process method for the FCBGA substrate according to this embodiment may include steps S1 to S5.

[0035] Step S1: On the surface of the inner circuit 2 of the packaging substrate, ABF layer 3 and copper foil 4 are sequentially laminated.

[0036] The innermost material of the packaging substrate is a core board 1, on which copper lines are fabricated as inner layer lines 2. The manufacturing method and structure of this inner layer line 2 are the same as those of a conventional printed circuit board, for example... Figure 2 As shown, a through slot is formed on the core board 1, which penetrates the upper and lower surfaces of the core board 1. The inner layer circuit 2 fills the through slot and extends to the upper and lower surfaces of the core board 1.

[0037] Before sequentially laminating ABF layer 3 and copper foil 4, the surface of inner layer circuit 2 needs to be roughened to improve the bonding force between inner layer circuit 2 and ABF layer 3.

[0038] The embodiments of the present invention use ABF layer products as interlayer insulation materials for circuits, which can be used to fabricate precision circuits on the surface of the material using a semi-additive process.

[0039] Next, on the surface of the inner circuit 2, an ABF layer 3 can be first laminated using a vacuum laminator at a temperature lower than normal, and then copper foil 4 can be laminated onto the surface of the ABF layer 3.

[0040] Step S2: Place the pressed ABF layer 3 in an oven to bake and complete the pre-curing.

[0041] This step uses low-temperature baking, the main purpose of which is to remove moisture adsorbed by the encapsulation substrate during processing. Specifically, the laminated ABF layer 3 is placed in an oven for baking, first at 130°C for 30 minutes, and then at 180°C for 60 minutes. After baking, the curing degree of ABF layer 3 increases slightly.

[0042] Step S3, vacuum heating and pressurizing the pre-cured ABF layer 3 to completely cure the ABF layer 3.

[0043] In the embodiment of the present application, vacuum heating and pressurizing the pre-cured ABF layer 3 can include: placing the pre-cured ABF layer 3 in a vacuum condition, and through heating and pressurizing under the mirror isolation steel plate clamping of the laminator, completely curing the ABF layer 3.

[0044] Further, the temperature after heating can be 190℃-210℃, and the pressure after pressurizing can be greater than 1MPa.

[0045] It should be noted that the conventional ABF curing is after the ABF surface circuit is made, and is baked at 130℃ for 30 minutes in an oven, and then baked at 190℃-210℃ for 1 hour in a temperature oven. In the embodiment of the present application, the pre-cured packaging substrate is clamped by the mirror isolation steel plate in the laminator, and the ABF is completely cured by the action of temperature and pressure in the vacuum chamber.

[0046] Step S4, removing the copper foil 4 to manufacture the outer layer circuit 9 on the completely cured ABF layer 3.

[0047] Step S5, repeating the above steps S1-S4 to form a multi-layer circuit packaging substrate.

[0048] Therefore, the outer layer circuit 9 is made on the surface of the completely cured ABF layer 3, and the manufactured outer layer circuit 9 is repeated as the inner layer circuit 2 to obtain a multi-layer circuit packaging substrate.

[0049] In order to specifically describe the manufacturing process of the outer layer circuit 9, Figure 3 The operation flowchart of the manufacturing process of the outer layer circuit according to the embodiment of the present application is schematically shown, Figure 4 The process flowchart of the manufacturing process of the outer layer circuit according to the embodiment of the present application is schematically shown.

[0050] Please refer to Figure 3 and Figure 4 In the embodiment of the present application, in the above step S4, removing the copper foil 4 to manufacture the outer layer circuit 9 on the completely cured ABF layer 3 can further include steps S41-S48.

[0051] Step S41, laser drilling the completely cured ABF layer 3 and the copper foil 4 to form a blind hole 5 in communication with the inner layer circuit 2 in the ABF layer 3 and the copper foil 4.

[0052] Laser drilling to form a blind hole 5 in communication with the inner layer circuit 2 in the ABF layer 3 and the copper foil 4, thereby forming an interlayer interconnection channel.

[0053] It is to be noted that the conventional laser drilling process is performed on the surface of the ABF layer 3 after pre-curing. Unlike the conventional process, the laser drilling process of the embodiment of the present application is performed on the surface of the fully cured ABF layer 3.

[0054] Step S42, removing the laser drilling residual glue.

[0055] The residual glue carried by the laser drilling inside the blind hole 5 is removed. Unlike the conventional process, the conventional process is to remove the glue on the surface of the ABF hole after pre-curing.

[0056] Step S43, removing the surface copper foil 4.

[0057] Thus, the ABF layer 3 and the blind hole 5 are exposed.

[0058] Step S44, electroless plating copper in the ABF layer 3 and the blind hole 5 to form the electroplating seed layer 6.

[0059] The electroless plating copper can provide conductivity for subsequent electroplating. Unlike the conventional electroless plating copper deposition on the surface of the pre-cured ABF, the electroless plating copper of the embodiment of the present application is deposited on the surface of the fully cured ABF layer 3, and the non-hole area of the ABF layer 3 is not roughened by removing the glue.

[0060] Further, the thickness of the electroplating seed layer 6 can be 0.3 μm to 1 μm.

[0061] Step S45, photoetching to form a patterned electroplating mask 7 on the electroplating seed layer 6.

[0062] Dry film is pressed on the electroplating seed layer 6, and photoetching and development are performed to form a patterned electroplating mask 7.

[0063] Step S46, electroplating to form a circuit pattern 8 in the area of the electroplating seed layer 6 not covered by the patterned electroplating mask 7 and filling the blind hole 5.

[0064] This step is patterned electroplating, which is used to plate out the circuit pattern 8.

[0065] Step S47, removing the patterned electroplating mask 7.

[0066] Step S48, removing the electroplating seed layer 6 covered by the patterned electroplating mask 7 to form an outer layer circuit 9.

[0067] By rapid etching, the electroplating seed layer covered by the patterned electroplating mask 7 is removed to form an outer layer circuit 9.

[0068] Next, Figure 5 The structure diagram of the multilayer circuit packaging substrate according to the embodiment of the present application is schematically shown.

[0069] As Figure 5As shown, in this embodiment of the invention, the manufactured outer layer circuit 9 is used as the inner layer circuit 2, and the above steps S1 to S4 are repeated to alternately stack the inner layer circuit 2, ABF layer 3 and outer layer circuit 9 to obtain a multilayer circuit packaging substrate.

[0070] Figure 6 A schematic diagram of the solder mask layer according to an embodiment of the present invention is shown.

[0071] like Figure 6 As shown in the embodiment of the present invention, after forming the multilayer circuit packaging substrate in step S5, the method may further include: forming a solder resist layer 10 on the outermost layer of the multilayer circuit packaging substrate. The solder resist layer, as a protective layer, can be coated on lines or substrates of the packaging substrate that do not require soldering, and can also provide long-term protection for the formed circuit patterns.

[0072] Figure 7 A schematic diagram of the structure of an organic protective film according to an embodiment of the present invention is shown.

[0073] like Figure 7 As shown in the embodiment of the present invention, after fabricating the solder resist layer 10, the process may further include: coating an organic protective film 11 onto the outermost area of ​​the multilayer circuit package substrate not covered by the solder resist layer 10. The coating of the organic protective film can both protect the copper from oxidation and improve the solderability of the copper pads.

[0074] Furthermore, the organic protective film 11 material includes any one of NiAu, NiPdAu, OSP, and Sn.

[0075] As can be seen from the above description, the semi-additive process method for FCBGA substrates provided in the embodiments of the present invention achieves at least the following technical effects:

[0076] (1) The large copper sheet does not burst, ensuring the reliability of the substrate;

[0077] (2) Reduce process constraints and increase design freedom;

[0078] (3) Reduce the process window and improve yield;

[0079] (4) Reduce substrate warpage.

[0080] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. Furthermore, the word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

[0081] The above-described specific embodiments further illustrate the objects, technical solutions and advantages of the present application. It should be understood that the above-described specific embodiments are merely for the purpose of illustrating the present application and are not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semi-additive process method for an FCBGA substrate, characterized in that, Comprising: Step S1, on the surface of the inner layer circuit (2) of the packaging substrate, sequentially press ABF layer (3) and copper foil (4); Step S2, the ABF layer (3) after pressing is placed in the oven to bake, to complete the pre-curing; Step S3, the pre-cured ABF layer (3) is vacuum heated and pressurized, so that the ABF layer (3) is completely cured; Step S4, remove the copper foil (4), on the completely cured ABF layer (3) to manufacture outer layer circuit (9) comprising: Step S41, the completely cured ABF layer (3) and copper foil (4) are laser drilled to form a blind hole (5) in the ABF layer (3) and the copper foil (4) which communicates with the inner layer circuit (2); Step S42, remove the laser drilling residue; Step S43, remove the surface copper foil (4); Step S44, electroless copper plating in the ABF layer (3) and the blind hole (5) to form an electroplating seed layer (6); Step S45, photoetching to form a patterned electroplating mask (7) on the electroplating seed layer (6); Step S46, electroplating to form a circuit pattern (8) in the area of the electroplating seed layer (6) not covered by the patterned electroplating mask (7) and fill the blind hole (5); Step S47, remove the patterned electroplating mask (7); Step S48, remove the electroplating seed layer (6) covered by the patterned electroplating mask (7) to form the outer layer circuit (9); Step S5, repeat the above steps S1~S4 to form a multilayer circuit packaging substrate.

2. The process for half-addition of the FCBGA substrate according to claim 1, wherein, In step S1, before sequentially pressing the ABF layer (3) and the copper foil (4), further comprising: Roughening treatment is performed on the surface of the inner layer circuit (2).

3. The process for half-addition of the FCBGA substrate according to claim 1, wherein, In step S2, the ABF layer (3) after pressing is placed in the oven to bake, comprising: First bake at 130℃ for 30min, then bake at 180℃ for 60min.

4. The process for half-addition of the FCBGA substrate according to claim 1, wherein, In step S3, the pre-cured ABF layer (3) is vacuum heated and pressurized, comprising: The pre-cured ABF layer (3) is placed in a vacuum condition, and the mirror isolation steel plate is clamped under the laminator, and the ABF layer (3) is completely cured by heating and pressurizing.

5. The process for half-addition of the FCBGA substrate according to claim 4, wherein, The temperature after heating is 190℃~210℃, and the pressure after pressurizing is greater than 1MPa.

6. The process for half-addition of the FCBGA substrate according to claim 1, wherein, In step S44, the thickness of the electroplating seed layer (6) is 0.3μm~1μm.

7. The process for half-addition of the FCBGA substrate according to claim 1, wherein, In step S5, after forming the multilayer circuit packaging substrate, further comprising: A solder resist layer (10) is made on the outermost layer of the multilayer circuit packaging substrate.

8. The process for half-addition of the FCBGA substrate according to claim 7, wherein, After making the solder resist layer (10), further comprising: An organic protective film (11) is coated on the area of the outermost layer of the multilayer circuit packaging substrate not covered by the solder resist layer (10).

9. The process for half-addition of the FCBGA substrate according to claim 8, wherein, The material of the organic protective film (11) includes any one of NiAu, NiPdAu, OSP, Sn.

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