A hardware acceleration method for underwater target recognition

Abstract

The application provides a hardware acceleration method for underwater target identification, comprising: obtaining a sample set, wherein the sample set comprises a radiation noise DEMON spectrum and an underwater target category corresponding to the radiation noise DEMON spectrum; constructing a 1D-CNN model, taking the radiation noise DEMON spectrum as input and the underwater target category as result, training the 1D-CNN model to obtain an underwater target identification model; obtaining a forward propagation operation code by using code to describe a forward propagation operation process of the underwater target identification model; encapsulating the forward propagation operation code into an IP core; and accelerating the IP core based on a hardware layer to obtain an optimized IP core. By changing the internal structure of the model, each layer is connected with each other but independently designed, the calculation process of each part is independently carried out, and the calculation process and throughput of each part are analyzed to select a suitable acceleration strategy based on the hardware layer, so that the model can meet the performance requirements of real-time and low power consumption.

Description

Technical Field

[0001] The present disclosure generally relates to the field of underwater target recognition technology, and more particularly to a hardware acceleration method for underwater target recognition. Background Art

[0002] Accurately and quickly identifying and judging targets through sonar is a critical requirement for modern submarine exploration. Historically, underwater target identification has relied primarily on sonar operators, who continuously monitor underwater targets in extremely low signal-to-noise ratio environments to detect the rhythm, fluctuations, and timbre of ship-radiated noise, and then use spectrograms to determine the target's type.

[0003] With the emergence of new low-noise submarines, these characteristics, widely used in passive detection, have been deliberately reduced by designers, making them less detectable. In this situation, relying on sonar operators to listen for sound and make judgments undoubtedly increases their workload and mission difficulty. Furthermore, over-reliance on human subjectivity and accumulated experience can lead to misjudgments and missed detections of targets. With the advancement of automation technology, the development of sonar equipment that can automatically classify and identify the radiated noise of underwater targets has become an urgent need.

[0004] Neural networks, currently the most popular deep learning model, have garnered significant attention from scholars both domestically and internationally in the field of underwater acoustic recognition. Automatic underwater acoustic target recognition can leverage neural network algorithms, improving upon traditional methods to continuously optimize the classification and decision-making mechanisms. This has led to the development of intelligent underwater target recognition systems applicable to real-world environments, supplementing or even replacing manual judgment.

[0005] In recent years, research on applying FPGAs (Field-Programmable Gate Arrays) to convolutional neural network (CNN) computing has continued to emerge, and performance has gradually improved across the board. However, modeling complex dynamic algorithms at the RTL (Register Transfer Level) circuit level is extremely difficult, significantly limiting development speed. Furthermore, due to the high data throughput, the sequential execution architecture of general-purpose processors is insufficient to simultaneously meet the performance requirements of real-time performance and low power consumption. Summary of the Invention

[0006] In view of the above-mentioned defects or deficiencies in the prior art, it is desired to provide a hardware acceleration method for underwater target recognition.

[0007] This application provides a hardware acceleration method for underwater target recognition, comprising:

[0008] Acquire a sample set, the sample set including: a radiation noise DEMON spectrum and underwater target types corresponding to the radiation noise DEMON spectrum;

[0009] Constructing a 1D-CNN model, taking the radiated noise DEMON spectrum as input and the underwater target type as a result, training the 1D-CNN model to obtain an underwater target recognition model;

[0010] Using code to describe the forward propagation operation process of the underwater target recognition model to obtain a forward propagation operation code;

[0011] Encapsulating the forward propagation operation code into an IP core;

[0012] The IP core is accelerated based on the hardware level to obtain an optimized IP core.

[0013] According to the technical solution provided in the embodiment of the present application, the underwater target recognition model includes: a first convolutional layer, a second convolutional layer, a first pooling layer, a second pooling layer, a flattening layer and a fully connected layer; the fully connected layer includes multiple hidden layers;

[0014] The first convolution layer includes: 4 convolution kernels of length 5; the second convolution layer includes: 5 convolution kernels of length 3; the downsampling multiples of the first pooling layer and the second pooling layer are both 4;

[0015] The forward propagation operation process of the underwater target recognition model includes:

[0016] Input the DEMON spectrum into the first convolution layer, and output four first eigenvectors of 2048 data points after convolution operation; the DEMON spectrum is a one-dimensional spectrum with 2048 data points;

[0017] Input the first feature vector into the first pooling layer, and output four second feature vectors of 512 data points after 4-fold downsampling;

[0018] Input the second eigenvector into the second convolutional layer, and output four third eigenvectors of 128 data points after 4-fold downsampling;

[0019] Input the third eigenvector into the second pooling layer, and output four fourth eigenvectors of 32 data points after 4-fold downsampling;

[0020] The fourth eigenvector is input into the flattening layer, and the result calculated by the flattening layer is input into the fully connected layer, and the recognition result of the underwater target type is output through the softmax function.

[0021] According to the technical solution provided in the embodiment of the present application, the processing tool for encapsulating the forward propagation operation code into an IP core is the Vivado HLS high-level synthesis tool;

[0022] The IP core includes: input interface definition, output interface definition, data storage method and top-level function design; the input interface and output interface both use AXI bus, the protocol is AXI4, and the interface is AXI-HP.

[0023] According to the technical solution provided in the embodiment of the present application, the operation process of the optimized IP core includes:

[0024] After starting the optimized IP core, the weights and bias parameters of each layer of the neural network are loaded into BRAM;

[0025] Using the input interface of the top-level function to read into the input end of the first convolutional layer in a burst read and write manner through the AXI bus;

[0026] After the forward propagation operation, the output result of the hidden layer is written to the ARM side using a burst read and write method to complete a classification and recognition process.

[0027] According to the technical solution provided in the embodiment of the present application, the tool for hardware-level acceleration of the IP core is the Vivado HLS high-level synthesis tool; the method for hardware-level acceleration of the IP core using the Vivado HLS high-level synthesis tool includes: data type quantization, loop unrolling and loop blocking.

[0028] According to the technical solution provided in the embodiment of the present application, the data type of the underwater target recognition model is:

[0029] 10-bit data width, 5-bit integer part, 5-bit fractional part, quantization mode with rounding; overflow mode with the maximum value that can be represented by the remaining bits.

[0030] According to the technical solution provided in the embodiment of the present application, the loop unrolling step includes:

[0031] Expand the convolution kernel in the horizontal direction according to its own dimension, and the expansion degree according to its own dimension is Pkx;

[0032] In one clock cycle, the first product of the values ​​of the four frequency points and the corresponding positions of the convolution kernel is calculated;

[0033] According to a first addition tree, the first products are added in pairs to obtain a first intermediate result; the depth of the first addition tree is log2(Pkx);

[0034] Expand the pipeline of the entire calculation process;

[0035] Calculate the delay consumed by a single convolution operation; obtain the first delay result;

[0036] Expand the first eigenvector, the second eigenvector, and the third eigenvector according to the channel dimension; the expansion degree according to the channel dimension is Pif;

[0037] In one clock cycle, a feature data point is read in parallel from the same position of the Pif inputs of the first feature vector, the second feature vector, and the third feature vector, and multiplied with the corresponding weight in the same convolution kernel to obtain a second product;

[0038] According to a second addition tree, adding the second products in pairs to obtain a second intermediate result; the depth of the second addition tree is log2(pif);

[0039] Expand the pipeline of the entire calculation process;

[0040] Calculate the delay consumed by a single convolution operation; and obtain a second delay result.

[0041] According to the technical solution provided in the embodiment of the present application, the step of cyclic block division includes:

[0042] Divide the first eigenvector, the second eigenvector and the third eigenvector into blocks; the number of blocks is Pix;

[0043] Inputting the first eigenvector, the second eigenvector and the third eigenvector into the convolution kernel;

[0044] The convolution kernel simultaneously performs convolution operations on multiple positions, reads the storage space where the convolution kernel is located twice within one clock cycle, and simultaneously performs array partitioning processing on the input array; and obtains multiple third intermediate results;

[0045] The multiple intermediate results are reorganized and output.

[0046] According to the technical solution provided in the embodiment of the present application, the optimized IP core is simulated and debugged by writing a specified test program, and the optimized IP core is tested by setting a standard comparison value and comparing it with the result of the underwater target recognition model.

[0047] According to the technical solution provided in the embodiment of the present application, the testing method for the optimized IP core includes:

[0048] Performing RTL packaging on the optimized IP core and converting the optimized IP core into synthesizable code for FPGA;

[0049] Exporting the synthesizable code to a Vivado compilation environment and generating a bitstream;

[0050] Burning the bit stream generated by the optimized IP core into the first embedded platform; burning the burning file generated by the underwater target recognition model into the second embedded platform;

[0051] The first embedded platform and the second embedded platform respectively perform the same number of forward propagation operations on the optimized IP core and the underwater target recognition model using the same test data; and calculate a first propagation time and a first power consumption of the first embedded platform, and a second propagation time and a second power consumption of the second embedded platform;

[0052] Performing data comparison on the first propagation time and the second propagation time, and the first power consumption and the second power consumption respectively;

[0053] When the first propagation time is less than the second propagation time and the first power consumption is less than the second power consumption, a hardware acceleration effect is achieved;

[0054] When the first propagation time is less than the second propagation time and the first power consumption is not greater than a first set multiple of the second power consumption, a hardware acceleration effect is achieved;

[0055] When the first propagation time is not greater than a second set multiple of the second propagation time and the first power consumption is less than the second power consumption, a hardware acceleration effect is achieved.

[0056] The beneficial effects of this application are:

[0057] The underwater target recognition model is obtained by training a constructed 1D-CNN model using a sample set containing a radiated noise DEMON spectrum and the underwater target types corresponding to the radiated noise DEMON spectrum. The forward propagation operation process of the underwater target recognition model is described in code to obtain the forward propagation operation code. The forward propagation operation code is then encapsulated into an IP core. The IP core is then accelerated at the hardware level to obtain an optimized IP core. The underwater target recognition model is first described in code and encapsulated into an IP core, and then the IP core is hardware accelerated to obtain the optimized IP core. By modifying the internal structure of the model, each layer is interconnected but independently designed, and the computational process of each component is performed independently. The computational process and throughput of each component are analyzed to select an appropriate hardware-based layer-by-layer acceleration strategy, enabling the model to meet both real-time performance and low power consumption requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0059] Figure 1 A flowchart of a hardware acceleration method for underwater target recognition provided by this application;

[0060] Figure 2 This is the structural diagram of the underwater target recognition model;

[0061] Figure 3 Schematic diagram of the impact of data bit width on network model accuracy;

[0062] Figure 4 Schematic diagram of the convolution kernel expansion method;

[0063] Figure 5 Schematic diagram of the expansion method of the intermediate eigenvector;

[0064] Figure 6 It is a schematic diagram of the loop block method;

[0065] Figure 7 To optimize the IP core correctness verification process diagram;

[0066] Figure 8 Comparison chart of optimized IP core and IP core resource utilization. DETAILED DESCRIPTION

[0067] The present application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. It should also be noted that, for ease of description, only portions relevant to the invention are shown in the accompanying drawings.

[0068] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0069] Please refer to Figure 1 , which is a schematic diagram of a hardware acceleration method for underwater target recognition provided by this embodiment, including:

[0070] S1: Acquire a sample set, the sample set including: a radiation noise DEMON spectrum and underwater target types corresponding to the radiation noise DEMON spectrum;

[0071] S2: constructing a 1D-CNN model, taking the radiation noise DEMON spectrum as input and the underwater target type as a result, training the 1D-CNN model to obtain an underwater target recognition model;

[0072] S3: Using code to describe the forward propagation operation process of the underwater target recognition model to obtain a forward propagation operation code;

[0073] S4: Encapsulating the forward propagation operation code into an IP core;

[0074] S5: Accelerate the IP core based on the hardware level to obtain an optimized IP core.

[0075] In some embodiments, the forward propagation computational process of the 1D-CNN model is described and encapsulated using C code, including a first convolutional layer, a second convolutional layer, a first pooling layer, a second pooling layer, a flattening layer, and a fully connected layer; the fully connected layer includes multiple hidden layers. Test data is input into the 1D-CNN model, and after undergoing convolution and pooling multiplication and addition operations, underwater target classification is achieved. Each layer is interconnected but independently designed, and the computational process of each component is independent.

[0076] In some implementations, the input interface and the output interface both use an AXI bus, whose protocol is AXI4 and whose interface is AXI-HP; through the AXI bus, the PL end (digital end) can serve as a master device to access the PS end memory.

[0077] In some implementations, the top-level function design serves to instantiate the sub-modules, enabling communication between modules and between modules and the top-level module through interfaces.

[0078] In some implementations, hardware-based optimization and acceleration of the 1D-CNN model's computational process can reduce the overall forward propagation computation time. The pipelined parallel expansion strategy primarily includes: adjusting the loop order during the network's forward propagation process, optimizing data transmission channels, reducing the number of BRAM reads, and increasing data reusability; optimizing the convolution computation process using a pipelined approach to increase the hardware module's throughput; and parallelizing loops within the pipeline to reduce pipeline time.

[0079] Specifically, the test data of the optimized IP core and the underwater target recognition model are shown in Table 1.

[0080] In some embodiments, the first underwater target recognition model and the second underwater target recognition model are identical. The first underwater target recognition model uses an embedded platform model of ARM Cortex-A9 (dual-core); the second underwater target recognition model uses an embedded platform model of Intel Core i5-2400 (4 cores).

[0081] In some embodiments, the first underwater target recognition model, the second underwater target recognition model, and the optimized IP core are each subjected to the same number of forward propagation operations using the same test data. The performance of the models is tested by calculating the prediction time, data throughput, peak system power consumption, and energy efficiency ratio for 3,500 samples.

[0082] The optimized IP core consumed significantly less computation time to predict 3,500 samples than the first underwater target recognition model. Its data throughput was higher than that of the first underwater target recognition model. Its peak power consumption was slightly higher than that of the first underwater target recognition model. Its energy efficiency was significantly higher than that of the first underwater target recognition model. Combined with test data, the optimized IP core demonstrated overall superior performance during forward propagation operations compared to the first underwater target recognition model.

[0083] The optimized IP core consumed slightly more computational time to predict 3,500 samples than the second underwater target recognition model. Its data throughput was slightly lower than that of the second underwater target recognition model. Its peak power consumption was significantly lower than that of the second underwater target recognition model. Its energy efficiency was significantly higher than that of the second underwater target recognition model. Combined with test data, the optimized IP core demonstrated overall superior performance during forward propagation operations compared to the second underwater target recognition model.

[0084] Through data comparison, it can be concluded that the forward propagation operation process of the 1D-CNN model is described in code, then encapsulated into an IP core, and finally the IP core is accelerated at the hardware level to obtain the optimized IP core, which can achieve hardware-level acceleration and take into account the performance requirements of real-time and low power consumption.

[0085] Table 1 Data comparison table of optimized IP core and underwater target recognition model

[0086]

[0087] Further, refer to Figure 2 , the underwater target recognition model includes: a first convolutional layer, a second convolutional layer, a first pooling layer, a second pooling layer, a flattening layer and a fully connected layer; the fully connected layer includes multiple hidden layers;

[0088] The first convolution layer includes: 4 convolution kernels of length 5; the second convolution layer includes: 5 convolution kernels of length 3; the downsampling multiples of the first pooling layer and the second pooling layer are both 4;

[0089] The forward propagation operation process of the underwater target recognition model includes:

[0090] Input the DEMON spectrum into the first convolution layer, and output four first eigenvectors of 2048 data points after convolution operation; the DEMON spectrum is a one-dimensional spectrum with 2048 data points;

[0091] Input the first feature vector into the first pooling layer, and output four second feature vectors of 512 data points after 4-fold downsampling;

[0092] Input the second eigenvector into the second convolutional layer, and output four third eigenvectors of 128 data points after 4-fold downsampling;

[0093] Input the third eigenvector into the second pooling layer, and output four fourth eigenvectors of 32 data points after 4-fold downsampling;

[0094] The fourth eigenvector is input into the flattening layer, and the result calculated by the flattening layer is input into the fully connected layer, and the recognition result of the underwater target type is output through the softmax function.

[0095] In some embodiments, the forward propagation operation process of the 1D-CNN model is described and encapsulated using C code, including: a first convolutional layer, a second convolutional layer, a first pooling layer, a second pooling layer, a flattening layer, and a fully connected layer; the fully connected layer includes multiple hidden layers.

[0096] In some embodiments, the first convolutional layer includes four convolution kernels of length 5; the second convolutional layer includes five convolution kernels of length 3; and the first and second pooling layers each have a downsampling factor of 4. The test data is input into the 1D-CNN model, and after convolution and pooling multiplication and addition operations, underwater target classification is achieved. Each layer is interconnected but independently designed, and the computational process of each component is independent.

[0097] Furthermore, the processing tool for packaging the forward propagation operation code into an IP core is a Vivado HLS high-level synthesis tool;

[0098] The IP core includes: input interface definition, output interface definition, data storage method and top-level function design; the input interface and output interface both use AXI bus, the protocol is AXI4, and the interface is AXI-HP.

[0099] In some implementations, the input interface and the output interface both use an AXI bus, whose protocol is AXI4 and whose interface is AXI-HP; through the AXI bus, the PL end (digital end) can serve as a master device to access the PS end memory.

[0100] In some implementations, the top-level function design serves to instantiate the sub-modules, enabling communication between modules and between modules and the top-level module through interfaces.

[0101] Furthermore, the operation process of optimizing the IP core includes:

[0102] After starting the optimized IP core, the weights and bias parameters of each layer of the neural network are loaded into BRAM;

[0103] Using the input interface of the top-level function to read into the input end of the first convolutional layer in a burst read and write manner through the AXI bus;

[0104] After the forward propagation operation, the output result of the hidden layer is written to the ARM side using a burst read and write method to complete a classification and recognition process.

[0105] In some implementations, hardware-based optimization and acceleration of the 1D-CNN model's computational process can reduce the overall forward propagation computation time. The pipelined parallel expansion strategy primarily includes: adjusting the loop order during the network's forward propagation process, optimizing data transmission channels, reducing the number of BRAM reads, and increasing data reusability; optimizing the convolution computation process using a pipelined approach to increase the hardware module's throughput; and parallelizing loops within the pipeline to reduce pipeline time.

[0106] Furthermore, the tool for performing hardware-level acceleration on the IP core is the Vivado HLS high-level synthesis tool; the hardware-level acceleration method for the IP core using the Vivado HLS high-level synthesis tool includes: data type quantization, loop unrolling and loop blocking.

[0107] In some implementations, accelerating the IP core using only one of data type quantization, loop unrolling, or loop blocking can achieve an acceleration effect.

[0108] In some implementations, accelerating the IP core using data type quantization, loop unrolling, and loop blocking simultaneously can achieve even greater acceleration. By adjusting the loop order during network forward propagation and optimizing data transmission channels, the number of BRAM reads is reduced, increasing data reusability. By optimizing the convolution calculation process through pipelining, the hardware module throughput is increased. Furthermore, loops within the pipeline are parallelized to reduce pipeline time.

[0109] Furthermore, the data type of the underwater target recognition model is:

[0110] 10-bit data width, 5-bit integer part, 5-bit fractional part, quantization mode with rounding; overflow mode with the maximum value that can be represented by the remaining bits.

[0111] In some implementations, the rounding quantization mode is AP_RND; and the overflow mode for obtaining the maximum value that can be represented by the remaining number of bits is AP_SAT.

[0112] In some implementations, data type quantization is performed by reading parameter weights, biases, and intermediate values ​​of network operations and calculating their distribution. Analysis reveals that the values ​​of the parameters and intermediate results of the designed network model are primarily distributed between -1 and 8. Using the float data type for calculations would underutilize the bit width of the exponent and fractional components, necessitating fixed-point conversion of the data type.

[0113] In some embodiments, reference Figure 3 This is a schematic diagram of the effect of data bit width on network model accuracy. The horizontal axis represents the number of bits occupied by the overall data type, and the vertical axis represents the deviation between the result obtained by the optimized IP core and the correct result after forward propagation of 3500 data. The deviation is calculated according to formula (1).

[0114]

[0115] Among them, Result float [i] is the result of the i-th data calculated through forward propagation when the model parameters and calculation results of the convolutional neural network are all standard float floating-point data; Result ap_fixed [i] is the result of calculating the i-th data after changing the data type.

[0116] The bit width of the integer part is fixed to 4, 5, or 6. The bit width of the decimal part is adjusted to test the impact of the bit width of the data type on the network accuracy, and then the appropriate data type is selected.

[0117] After comparison, the data type is determined to be ap_fixed<10,5,AP_RND,AP_SAT>, indicating a 10-bit width, 5 bits for the integer portion, 5 bits for the fractional portion, AP_RND for the quantization mode, and AP_SAT for the overflow mode. All data in the optimized IP core uses ap_fixed<10,5,AP_RND,AP_SAT>.

[0118] Data quantization can adjust the loop order in the network forward propagation process, optimize the data transmission channel, reduce the number of BRAM reads, and increase data reuse.

[0119] Furthermore, the loop unrolling step includes:

[0120] Expand the convolution kernel in the horizontal direction according to its own dimension, and the expansion degree according to its own dimension is Pkx;

[0121] In one clock cycle, the first product of the values ​​of the four frequency points and the corresponding positions of the convolution kernel is calculated;

[0122] According to a first addition tree, the first products are added in pairs to obtain a first intermediate result; the depth of the first addition tree is log2(Pkx);

[0123] Expand the pipeline of the entire calculation process;

[0124] Calculate the delay consumed by a single convolution operation; obtain the first delay result;

[0125] Expand the first eigenvector, the second eigenvector, the third eigenvector, and the fourth eigenvector according to the channel dimension; the expansion degree according to the channel dimension is Pif;

[0126] In one clock cycle, a feature data point is read in parallel from the same position of the Pif inputs of the first eigenvector, the second eigenvector, the third eigenvector, and the fourth eigenvector, and multiplied with the corresponding weight in the same convolution kernel to obtain a second product;

[0127] According to a second addition tree, adding the second products in pairs to obtain a second intermediate result; the depth of the second addition tree is log2(pif);

[0128] Expand the pipeline of the entire calculation process;

[0129] Calculate the delay consumed by a single convolution operation; and obtain a second delay result.

[0130] In some embodiments, since the main calculations in the convolutional neural network are in the convolution layer, the convolution kernel is expanded according to the dimension of the convolution kernel, and the input DEMON spectrum and the first eigenvector, the second eigenvector, the third eigenvector and the fourth eigenvector are expanded according to the channel dimension. The overall calculation process adopts a pipeline flow method to realize time-sharing multiplexing of resources.

[0131] By implementing multi-dimensional expansion of the convolution loop and designing multiple parallel multiplication and addition computing units, the computing power is improved.

[0132] In some embodiments, reference Figure 4 , which is a schematic diagram of the convolution kernel expansion method. Among them, the pixel point is a floating-point data, including: a vector composed of 2048 floating-point data; as input data. Pkx is the expansion degree of the convolution kernel. Taking the convolution kernel size of 1x4 as an example, Pkx=4, which means that the convolution kernel is expanded in the horizontal direction. After the entire convolution kernel is expanded, the product of the values ​​of the four frequency points and the corresponding different positions of the convolution kernel can be realized within one clock cycle. At this time, the depth of the addition tree is log2(Pkx), which represents the logarithm of Pkx with base 2. The intermediate result is obtained by adding the products two by two through an addition tree. The overall calculation process is pipelined and expanded to realize the parallel pipeline calculation of the convolution operation and improve the efficiency of DSP (Digital signal processing). The final delay consumed by a single convolution operation is Latency Kernel Expansion According to formula (2), we can calculate:

[0133]

[0134] Among them, Latency is the number of clock cycles required for the function to calculate all output values ​​before optimization. Loop Iteration Indicates the number of clock cycles before the function can accept new input data, Interval Loop Iteration The number of clock cycles before the next iteration of the loop begins processing data, and TripCount is the number of loops. Pipeline It represents the delay consumed by a single convolution operation after pipeline expansion, and Pkx represents the expansion degree of the convolution kernel.

[0135] Taking the calculation process of the first convolutional layer as an example, the input DEMON spectrum dimension is 2048, the convolution kernel size is 5, and the clock cycles required for reading, writing and calculating once are 7. Under normal circumstances, Latency = 7 + 7 × (2048-1) = 14336 clock cycles. It can be concluded that the method of using pipeline hydration and convolution kernel expansion is:

[0136] For ease of calculation, the value 411 is used, representing 411 clock cycles. The calculation shows that the rate has increased by about 35 times. This effectively increases the calculation speed and achieves an acceleration effect.

[0137] In some embodiments, reference Figure 5 , is a schematic diagram of the expansion method of the intermediate feature vector. Among them, the pixel point is a floating point data, including: a vector composed of 2048 floating point data; as input data. Pif is the expansion degree of the feature vector channel. Taking the number of feature vector channels as 4 as an example, Pif=4, which means that the first feature vector, the second feature vector, the third feature vector and the fourth feature vector of the input are expanded according to the channel dimension. After the channel is expanded, within one clock cycle, a feature data point is read from the same position of the Pif input feature vectors in parallel and multiplied with the corresponding weight in the same convolution kernel. The product is added two by two through an addition tree with a depth of log2(pif) to obtain an intermediate result. The overall calculation process is also pipelined and expanded. The final delay consumed by a single convolution operation is Latency Input Expansion According to formula (3), we can calculate:

[0138]

[0139] Taking the second convolutional layer as an example, the dimension of the second feature vector output by the first pooling layer is 4x2048 (where the number of channels is 4), the convolution kernel dimension is 4x5 (the number of channels is 4, the same as the number of feature vectors to be convolved), and the clock cycles required for reading, writing, and calculating once are 7. Under normal circumstances, Latency = 4×[7+7×(2048-1)] = 57344 clock cycles. Then, the pipeline and convolution kernel expansion method is as follows:

[0140] For the convenience of calculation, the value 1643 is taken, which represents 1643 clock cycles. After calculation, it is found that the rate is increased by about 35 times.

[0141] By implementing multi-dimensional expansion of the convolution loop and designing multiple parallel multiplication and addition computing units, computing power is improved; by optimizing the convolution calculation process through pipelining, the throughput of the hardware module is improved; and by parallelizing the loops within the pipeline, the pipeline time is reduced.

[0142] Furthermore, the step of looping and blocking includes:

[0143] Divide the first eigenvector, the second eigenvector, the third eigenvector and the fourth eigenvector into blocks; the number of blocks is Pix;

[0144] Inputting the first eigenvector, the second eigenvector, the third eigenvector and the fourth eigenvector into the convolution kernel;

[0145] The convolution kernel simultaneously performs convolution operations on multiple positions, reads the storage space where the convolution kernel is located twice within one clock cycle, and simultaneously performs array partitioning processing on the input array; and obtains multiple third intermediate results;

[0146] The multiple intermediate results are reorganized and output.

[0147] In some embodiments, reference Figure 6 , a schematic diagram of the cyclic block partitioning method. A pixel is a floating-point data element, including a vector of 2048 floating-point data elements, serving as input data. Pix represents the number of blocks into which the input feature vector is partitioned. Block partitioning allows the convolution kernel to simultaneously perform convolution operations on multiple locations of the input feature vector during the convolution process, then recombining the results from each block. Testing has shown that the computation speed is Pix times faster than without block partitioning. Because parallel computing requires reading and writing different locations in the memory space within the same clock cycle, access restrictions can be imposed if the number of array read and write channels is less than the number of blocks. Therefore, the memory space for the input feature vector must be partitioned; multiple access channels to the memory space are opened to address memory access bottlenecks. For the convolution kernel, the partitioned input data is reused Pix times during parallel computing. For example, if the input data is partitioned into Pix = 2 blocks, the memory space containing the convolution kernel must be read twice during the parallel computing process, and the input array must be partitioned (array_partition = 2). Array partitioning can effectively improve data throughput.

[0148] Furthermore, the optimized IP core is simulated and debugged by writing a specified test program, and the optimized IP core is tested by setting a standard comparison value and comparing it with the result of the underwater target recognition model.

[0149] In some implementations, to verify the correctness of the optimized IP core's functionality, a test program (TestBench) is written to simulate and debug the optimized IP core; a standard comparison value (Golden Value) is set to compare with the actual output results. The optimized IP core that meets the requirements is synthesized and a series of report files and RTL design files are generated, packaged, and exported. The exported optimized IP core includes relevant files such as drivers, reference documentation, and usage examples for subsequent system integration.

[0150] In some embodiments, reference Figure 7, the test data is input into the trained network model and the module to be tested respectively; the trained network model outputs a standard output result, and the deviation is calculated by setting a standard comparison value and the result of the optimized IP core output input by the module to be tested; if the deviation is less than the error range, the optimized IP core is saved; if the deviation is greater than the error range, it is concluded that the code is wrong.

[0151] Furthermore, the testing method for the optimized IP core includes:

[0152] Performing RTL packaging on the optimized IP core and converting the optimized IP core into synthesizable code for FPGA;

[0153] Exporting the synthesizable code to a Vivado compilation environment and generating a bitstream;

[0154] Burning the bit stream generated by the optimized IP core into the first embedded platform; burning the burning file generated by the underwater target recognition model into the second embedded platform;

[0155] The first embedded platform and the second embedded platform respectively perform the same number of forward propagation operations on the optimized IP core and the underwater target recognition model using the same test data; and calculate a first propagation time and a first power consumption of the first embedded platform, and a second propagation time and a second power consumption of the second embedded platform;

[0156] Performing data comparison on the first propagation time and the second propagation time, and the first power consumption and the second power consumption respectively;

[0157] When the first propagation time is less than the second propagation time and the first power consumption is less than the second power consumption, a hardware acceleration effect is achieved;

[0158] When the first propagation time is less than the second propagation time and the first power consumption is not greater than a first set multiple of the second power consumption, a hardware acceleration effect is achieved;

[0159] When the first propagation time is not greater than a second set multiple of the second propagation time and the first power consumption is less than the second power consumption, a hardware acceleration effect is achieved.

[0160] In some implementations, the first embedded platform is an FPGA, and the second embedded platform is a BRAM.

[0161] In some embodiments, reference Figure 8The following is a comparison chart of the optimized IP core and IP core resource utilization. Among them, BRAM is block memory, DSP48E is the smallest computing unit of the 7 series, FF (flip flop) is a trigger, and LUT is a lookup table. In order to test the performance of the optimized IP core, the small 1D-CNN model is deployed based on the XC7Z020CLG400-1 chip of Xilinx's Zynq-7000 series. A DEMON spectrum is input, and the system outputs an array with a dimension of 7 to represent the predicted probability values ​​of seven categories from 0 to 6. The forward propagation operation process of the 1D-CNN model is described in code, and then encapsulated into the IP core. Finally, hardware-based acceleration is performed to obtain the optimized IP core. According to Figure 8 Comparison of data reveals that parallelizing the network computation process slightly increases resource utilization compared to unoptimized processes, with LUT utilization reaching approximately 76% and BRAM utilization reaching approximately 73%. This algorithmic optimization trades resources for area, reducing the latency of the network forward propagation process by improving on-chip resource utilization.

[0162] As shown in Table 1, a data comparison shows that FPGA-based designs significantly improve both power consumption and forward propagation speed compared to traditional PC and ARM architectures. Calculations show that the computational throughput of the FPGA+ARM architecture is 38.5 times that of the pure ARM architecture. During forward propagation, while the Zynq's computational speed is similar to that of a PC, its power consumption is only 5.26% of that of a PC. A comparison of energy efficiency reveals that Zynq's energy efficiency is 30.47 times that of ARM and 17 times that of a PC.

[0163] The above description is merely a preferred embodiment of the present application and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention herein is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also encompasses other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the inventive concept. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features having similar functions disclosed in this application.

Claims

1. A hardware acceleration method for underwater target recognition, characterized in that: include: Acquire a sample set, the sample set including: a radiation noise DEMON spectrum and underwater target types corresponding to the radiation noise DEMON spectrum; Constructing a 1D-CNN model, taking the radiated noise DEMON spectrum as input and the underwater target type as a result, training the 1D-CNN model to obtain an underwater target recognition model; Using code to describe the forward propagation operation process of the underwater target recognition model to obtain a forward propagation operation code; Encapsulating the forward propagation operation code into an IP core; The IP core is accelerated at the hardware level to obtain an optimized IP core; the underwater target recognition model includes: a first convolutional layer, a second convolutional layer, a first pooling layer, a second pooling layer, a flattening layer, and a fully connected layer; the fully connected layer includes multiple hidden layers; The first convolution layer includes: 4 convolution kernels of length 5; the second convolution layer includes: 5 convolution kernels of length 3; the downsampling multiples of the first pooling layer and the second pooling layer are both 4; The forward propagation operation process of the underwater target recognition model includes: Input the DEMON spectrum into the first convolution layer, and output four first eigenvectors of 2048 data points after convolution operation; the DEMON spectrum is a one-dimensional spectrum with 2048 data points; Input the first feature vector into the first pooling layer, and output four second feature vectors of 512 data points after 4-fold downsampling; Input the second eigenvector into the second convolutional layer, and output four third eigenvectors of 128 data points after 4-fold downsampling; Input the third eigenvector into the second pooling layer, and output four fourth eigenvectors of 32 data points after 4-fold downsampling; Input the fourth eigenvector into the flattening layer, then input the result calculated by the flattening layer into the fully connected layer, and output the recognition result of the underwater target type through the softmax function; The tool for hardware-level acceleration of the IP core is the Vivado HLS high-level synthesis tool; the hardware-level acceleration method of the IP core using the Vivado HLS high-level synthesis tool includes: data type quantization, loop unrolling and loop blocking; The loop unrolling step includes: Expand the convolution kernel in the horizontal direction according to its own dimension, and the expansion degree according to its own dimension is Pkx; In one clock cycle, the first product of the values ​​of the four frequency points and the corresponding positions of the convolution kernel is calculated; According to a first addition tree, the first products are added in pairs to obtain a first intermediate result; the depth of the first addition tree is log2(Pkx); Expand the pipeline of the entire calculation process; Calculate the delay consumed by a single convolution operation; obtain the first delay result; Expand the first eigenvector, the second eigenvector, the third eigenvector, and the fourth eigenvector according to the channel dimension; the expansion degree according to the channel dimension is Pif; In one clock cycle, a feature data point is read in parallel from the same position of the Pif inputs of the first eigenvector, the second eigenvector, the third eigenvector, and the fourth eigenvector, and multiplied with the corresponding weight in the same convolution kernel to obtain a second product; According to a second addition tree, adding the second products in pairs to obtain a second intermediate result; the depth of the second addition tree is log2(pif); Expand the pipeline of the entire calculation process; Calculate the delay consumed by a single convolution operation; and obtain a second delay result.

2. The hardware acceleration method for underwater target recognition according to claim 1, characterized in that: The processing tool for packaging the forward propagation operation code into an IP core is the Vivado HLS high-level synthesis tool; The IP core includes: input interface definition, output interface definition, data storage method and top-level function design; the input interface and output interface both use AXI bus, the protocol is AXI4, and the interface is AXI-HP.

3. The hardware acceleration method for underwater target recognition according to claim 2, characterized in that: The operation process of optimizing the IP core includes: After starting the optimized IP core, the weights and bias parameters of each layer of the neural network are loaded into BRAM; Using the input interface of the top-level function to read into the input end of the first convolutional layer in a burst read and write manner through the AXI bus; After the forward propagation operation, the output result of the hidden layer is written to the ARM side using a burst read and write method to complete a classification and recognition process.

4. The hardware acceleration method for underwater target recognition according to claim 1, characterized in that: The data types of the underwater target recognition model are: 10-bit data width, 5-bit integer part, 5-bit fractional part, quantization mode with rounding; overflow mode with the maximum value that can be represented by the remaining bits.

5. The hardware acceleration method for underwater target recognition according to claim 1, characterized in that: The steps of loop blocking include: Divide the first eigenvector, the second eigenvector, the third eigenvector and the fourth eigenvector into blocks; the number of blocks is Pix; Inputting the first eigenvector, the second eigenvector, the third eigenvector and the fourth eigenvector into the convolution kernel; The convolution kernel simultaneously performs convolution operations on multiple positions, reads the storage space where the convolution kernel is located twice within one clock cycle, and simultaneously performs array partitioning processing on the input array; and obtains multiple third intermediate results; The multiple intermediate results are reorganized and output.

6. The hardware acceleration method for underwater target recognition according to claim 1, characterized in that: The optimized IP core is simulated and debugged by writing a specified test program, and the optimized IP core is tested by setting a standard comparison value and comparing it with the result of the underwater target recognition model.

7. The hardware acceleration method for underwater target recognition according to claim 6, characterized in that: The testing method for the optimized IP core includes: Performing RTL packaging on the optimized IP core and converting the optimized IP core into synthesizable code for FPGA; Exporting the synthesizable code to a Vivado compilation environment and generating a bitstream; Burning the bit stream generated by the optimized IP core into the first embedded platform; burning the burning file generated by the underwater target recognition model into the second embedded platform; The first embedded platform and the second embedded platform respectively perform the same number of forward propagation operations on the optimized IP core and the underwater target recognition model using the same test data; and calculate a first propagation time and a first power consumption of the first embedded platform, and a second propagation time and a second power consumption of the second embedded platform; Performing data comparison on the first propagation time and the second propagation time, and the first power consumption and the second power consumption respectively; When the first propagation time is less than the second propagation time and the first power consumption is less than the second power consumption, a hardware acceleration effect is achieved; When the first propagation time is less than the second propagation time and the first power consumption is not greater than a first set multiple of the second power consumption, a hardware acceleration effect is achieved; When the first propagation time is not greater than a second set multiple of the second propagation time and the first power consumption is less than the second power consumption, a hardware acceleration effect is achieved.

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