Interconnection structure and its formation method

Abstract

Interconnect structures and methods of forming thereof are described. In some embodiments, the structure includes: a first intermetallic dielectric (IMD) layer disposed over a plurality of conductive components; and a first passive component disposed on the first IMD layer in a first region of a substrate. The structure further includes: a second passive component disposed on the first IMD layer in a second region of the substrate. The second passive component includes a first conductive layer, and the first conductive layer has a first thickness. The structure further includes: a second IMD layer disposed on the first passive component in the first region and on the second passive component and a portion of the first IMD layer in the second region. The second IMD layer has a second thickness ranging from about five times to about 20 times the first thickness.

Description

Technical Field

[0001] Embodiments of this application relate to interconnect structures and methods of forming them. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. However, these advancements have increased the complexity of handling and manufacturing ICs, and similar developments in IC handling and manufacturing are needed to realize these advancements. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component that can be created using manufacturing processes) has decreased.

[0003] Passive components such as capacitors, resistors, and inductors can be integrated into an IC along with active components such as transistors. While existing processes for manufacturing passive components are generally sufficient for their intended purpose, they are not entirely satisfactory in all respects as devices continue to scale down. Summary of the Invention

[0004] Some embodiments of this application provide an interconnect structure disposed above a substrate, comprising: a first inter-metal dielectric (IMD) layer disposed above a plurality of conductive components; a first passive component disposed on the first IMD layer in a first region of the substrate, wherein the first passive component is a capacitor; a second passive component disposed on the first IMD layer in a second region of the substrate, wherein the second passive component is a resistor including a first conductive layer, and the first conductive layer has a first thickness; and a second IMD layer disposed on the first passive component in the first region and on the second passive component and a portion of the first IMD layer in the second region, wherein the top surfaces of the second IMD layer in the first region and the second region are substantially flat, and the second IMD layer has a second thickness ranging from 5 times to 20 times the first thickness. In some embodiments, the interconnect structure further comprises: a third IMD layer, wherein the plurality of conductive components are disposed in the third IMD layer.

[0005] Other embodiments of this application provide an interconnect structure disposed above a substrate, comprising: a first inter-metal dielectric (IMD) layer disposed above a plurality of conductive components; a first passive component disposed on the first IMD layer in a first region of the substrate, wherein the first passive component comprises: a first conductive layer; a first insulating layer disposed on the first conductive layer; a second conductive layer disposed on the first insulating layer; a second insulating layer disposed on the second conductive layer; and a third conductive layer disposed on the second insulating layer; a second passive component disposed above the first IMD layer in a second region of the substrate, wherein the second passive component comprises a fourth conductive layer disposed above the first IMD layer in the second region, and an insulating layer disposed on the fourth conductive layer in the second region; and a second IMD layer disposed on the third conductive layer in the first region and the insulating layer in the second region.

[0006] Further embodiments of this application provide a method for forming an interconnect structure, including: forming a first inter-metal dielectric (IMD) layer over a plurality of conductive components; forming a first passive component over the first IMD layer, including: forming a first conductive layer over the first IMD layer; forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming a second insulating layer on the second conductive layer; and forming a third conductive layer on the second insulating layer; forming a second passive component over the first IMD layer, including: forming a fourth conductive layer over the first IMD layer, wherein the fourth conductive layer is formed simultaneously with the first conductive layer, the second conductive layer, or the third conductive layer; and forming a second IMD layer on the first passive component and the second passive component. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1A This is a perspective view of one of the various stages of manufacturing a semiconductor device structure according to some embodiments.

[0009] Figure 1B According to some embodiments Figure 1A A cross-sectional side view of the stage of manufacturing a semiconductor device structure, taken by line AA.

[0010] Figure 2This is a cross-sectional side view of a stage in the manufacturing of a semiconductor device structure according to some embodiments.

[0011] Figure 3 This is a cross-sectional side view of the top of an interconnect structure according to some embodiments.

[0012] Figure 4A and Figure 4B This is a plan view of the conductive layer of a passive component disposed in an interconnect structure according to some embodiments.

[0013] Figures 5 to 8 This is a cross-sectional side view of the top of the interconnect structure according to an alternative embodiment.

[0014] Figures 9A to 9I These are cross-sectional side views of various stages of manufacturing interconnect structures according to some embodiments.

[0015] Figures 10A to 10F This is a cross-sectional side view of various stages of manufacturing the interconnect structure according to an alternative embodiment. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, this document may use spatial relative terms such as “below,” “under,” “lower,” “above,” “above,” “on,” “top,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] Figure 1A and Figure 1B The stages of manufacturing the semiconductor device structure 100 are illustrated. (For example...) Figure 1A and Figure 1BAs shown, the semiconductor device structure 100 includes a substrate 102 and one or more devices 200 formed on the substrate 102. The substrate 102 may be a semiconductor substrate. In some embodiments, the substrate 102 includes at least a single-crystal semiconductor layer located on the surface of the substrate 102. The substrate 102 may include crystalline semiconductor materials such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). For example, the substrate 102 is made of Si. In some embodiments, the substrate 102 is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. On one hand, the insulating layer is an oxygen-containing material, such as an oxide.

[0019] Substrate 102 may include one or more buffer layers (not shown) located on the surface of substrate 102. The buffer layers may be used to gradually change the lattice constant from that of the substrate to the lattice constant of the source / drain region. The buffer layers may be formed from epitaxially grown crystalline semiconductor materials, such as, but not limited to, Si, Ge, Germanium-tin (GeSn), SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP.

[0020] The substrate 102 may include various regions that have been appropriately doped with impurities (e.g., p-type or n-type impurities). The dopant is, for example, phosphorus for an n-type fin field-effect transistor (FinFET) and boron for a p-type FinFET.

[0021] As described above, device 200 can be any suitable device, such as a transistor, diode, image sensor, resistor, capacitor, inductor, memory cell, or a combination thereof. In some embodiments, device 200 is a transistor, such as a planar field-effect transistor (FET), FinFET, nanostructured transistor, or other suitable transistor. Nanostructured transistors may include nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding a channel. An example of device 200 formed on substrate 102 is a FinFET, which... Figure 1A and Figure 1B As shown in the figure. Device 200 includes source / drain (S / D) region 124 and gate stack 140. Figure 1A(Only one is shown in the image). Each gate stack 140 may be disposed between the S / D region 124 used as the source region and the S / D region 124 used as the drain region. For example, each gate stack 140 may extend along the Y-axis between one or more S / D regions 124 used as the source region and one or more S / D regions 124 used as the drain region. Figure 1B As shown, two gate stacks 140 are formed on the substrate 102. In some embodiments, more than two gate stacks 140 are formed on the substrate 102. A channel region 108 is formed between the S / D region 124, which serves as the source region, and the S / D region 124, which serves as the drain region.

[0022] S / D region 124 may include semiconductor materials such as Si or Ge, III-V compound semiconductors, II-VI compound semiconductors, or other suitable semiconductor materials. Exemplary S / D region 124 may include, but is not limited to, Ge, SiGe, GaAs, AlGaAs, GaAsP, SiP, InAs, AlAs, InP, GaN, InGaAs, InAlAs, GaSb, AlP, GaP, etc. S / D region 124 may include: p-type dopants, such as boron; n-type dopants, such as phosphorus or arsenic; and / or other suitable dopants including combinations thereof. S / D region 124 may be formed by epitaxial growth methods using CVD, atomic layer deposition (ALD), or molecular beam epitaxy (MBE). Channel region 108 may include one or more semiconductor materials such as Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, or InP. In some embodiments, the channel region 108 comprises the same semiconductor material as the substrate 102. In some embodiments, the device 200 is a FinFET, and the channel region 108 is a plurality of fins disposed beneath the gate stack 140. In some embodiments, the device 200 is a nanostructure transistor, and the channel region 108 is surrounded by the gate stack 140.

[0023] like Figure 1A and Figure 1BAs shown, each gate stack 140 includes a gate electrode layer 138 disposed over (or around) a channel region 108 for a nanostructure transistor. The gate electrode layer 138 may be a metallic material, such as tungsten, cobalt, aluminum, ruthenium, copper, or multilayers thereof, and may be deposited by ALD, plasma-enhanced chemical vapor deposition (PECVD), MBD, physical vapor deposition (PVD), or any suitable deposition technique. Each gate stack 140 may also include a gate dielectric layer 136 disposed over the channel region 108. The gate electrode layer 138 may be disposed over the gate dielectric layer 136. In some embodiments, an interface layer (not shown) may be disposed between the channel region 108 and the gate dielectric layer 136, and one or more work function layers (not shown) may be formed between the gate dielectric layer 136 and the gate electrode layer 138. The interface dielectric layer may include a dielectric material, such as an oxygen-containing material or a nitrogen-containing material, or multilayers thereof, and may be formed by any suitable deposition method, such as CVD, PECVD, or ALD. The gate dielectric layer 136 may include a dielectric material, such as an oxygen-containing or nitrogen-containing material, a high-k dielectric material having a k-value greater than that of silicon dioxide, or multiple layers thereof. The gate dielectric layer 136 may be formed by any suitable method, such as CVD, PECVD, or ALD. In some embodiments, the gate dielectric layer 136 may be a conformal layer. The term "conformal" may be used herein to describe layers having substantially the same thickness over the respective regions. One or more function layers may include titanium aluminum carbide, titanium aluminum oxide, titanium aluminum nitride, etc.

[0024] Gate spacers 122 are formed along the sidewalls of the gate stack 140 (e.g., the sidewalls of the gate dielectric layer 136). Gate spacers 122 may comprise silicon oxycarbide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., multilayers thereof, or combinations thereof, and may be deposited by CVD, ALD, or other suitable deposition techniques.

[0025] like Figure 1A As shown, fin sidewall spacers 123 may be disposed on opposite sides of each S / D region 124, and fin sidewall spacers 123 may comprise the same material as gate spacers 122. Portions of gate stack 140, gate spacers 122, and fin sidewall spacers 123 may be disposed on isolation region 114. Isolation region 114 is disposed on substrate 102. Isolation region 114 may comprise an insulating material, such as an oxygen-containing material, a nitrogen-containing material, or a combination thereof. In some embodiments, isolation region 114 is shallow trench isolation (STI). The insulating material may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or other suitable deposition processes. In one aspect, isolation region 114 comprises silicon oxide formed by an FCVD process.

[0026] like Figure 1A and Figure 1B As shown, a contact etch stop layer (CESL) 126 is formed on the S / D region 124 and the isolation region 114, and an interlayer dielectric (ILD) layer 128 is formed on the CESL 126. The CESL 126 can provide a mechanism to stop the etch process when an opening is formed in the ILD layer 128. The CESL 126 can be conformally deposited on the surfaces of the S / D region 124 and the isolation region 114. The CESL 126 can include oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon oxycarbide, etc., or combinations thereof, and can be deposited by CVD, PECVD, ALD, or any suitable deposition technique. The ILD layer 128 may comprise an oxide formed of tetraethyl orthosilicate (TEOS), undoped silicate glass or doped silicon oxide (such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), organosilicon glass (OSG), SiOC) and / or any suitable low-k dielectric material (e.g., a material having a dielectric constant lower than that of silicon dioxide), and may be deposited by spin coating, CVD, FCVD, PECVD, PVD or any suitable deposition technique.

[0027] Conductive contacts (not shown) may be disposed in the ILD layer 128 and above the S / D region 124. The conductive contacts may be conductive and comprise one or more materials having Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN, and may be formed by any suitable method, such as electrochemical plating (ECP) or PVD. A silicide layer (not shown) may be disposed between the conductive contacts and the S / D region 124.

[0028] The semiconductor device structure 100 may further include an interconnect structure 300 disposed above the device 200 and the substrate 102, such as Figure 2As shown in the diagram. The interconnect structure 300 includes various conductive components, such as a first plurality of conductive components 304 and a second plurality of conductive components 306, and an inter-metal dielectric (IMD) layer 302 to separate and isolate the various conductive components 304, 306. In some embodiments, the first plurality of conductive components 304 are wires and the second plurality of conductive components 306 are conductive vias. The interconnect structure 300 includes multiple layers of conductive components 304, and the conductive components 304 are arranged in each layer to provide electrical paths to various devices 200 disposed below. The conductive components 306 provide vertical electrical wiring from the devices 200 to the conductive components 304 and between the conductive components 304. For example, the bottommost conductive component 306 of the interconnect structure 300 may be electrically connected to the S / D region 124 ( Figure 1B ) and gate electrode layer 138 ( Figure 1B The conductive contacts are located above the conductive components. Conductive components 304 and 306 can be made of one or more conductive materials, such as metals, metal alloys, metal nitrides, or silicides. For example, conductive components 304 and 306 are made of copper, aluminum, aluminum-copper alloys, titanium, titanium nitride, tantalum, tantalum nitride, silicon titanium nitride, zirconium, gold, silver, cobalt, nickel, tungsten, tungsten nitride, silicon tungsten nitride, platinum, chromium, molybdenum, hafnium, other suitable conductive materials, or combinations thereof.

[0029] IMD layer 302 includes one or more dielectric materials to provide isolation to the respective conductive components 304, 306. IMD layer 302 may include multiple dielectric layers of multiple levels embedded in the conductive components 304, 306. IMD layer 302 is made of a dielectric material, such as SiO2. x SiO x C y H z or SiO x C y Where x, y, and z are integers or non-integers. In some embodiments, the IMD layer 302 includes a dielectric material having a k value ranging from about 1 to about 5. Passive components (not shown), such as capacitors, resistors, and / or inductors, may be disposed in the interconnect structure 300.

[0030] Figure 3 This is a cross-sectional side view of the top of the interconnect structure 300 according to some embodiments. (See also:) Figure 3As shown, the interconnect structure 300 also includes passive components 382 and 392 disposed therein. In some embodiments, passive component 382 is a capacitor, such as a metal-insulator-metal (MIM) capacitor, and passive component 392 is a resistor. Passive component 382 is disposed in region 380 of the semiconductor device structure 100, and passive component 392 is disposed in region 390 of the semiconductor device structure 100. In some embodiments, region 380 may be a capacitor region, and region 390 may be a resistor region. Region 380 may be located adjacent to region 390, or regions 380 and 390 may be located in different regions of the substrate 102. In other words, regions 380 and 390 may be located close to each other or spaced apart from each other.

[0031] like Figure 3 As shown, the passive component 382 includes a first conductive layer 312, a first insulating layer 314 disposed on the first conductive layer 312, a second conductive layer 316 disposed on the first insulating layer 314, a second insulating layer 318 disposed on the second conductive layer 316 and the first insulating layer 314, and a third conductive layer 320 disposed on the second insulating layer 318. The second conductive layer 316 may partially overlap with the first conductive layer 312, and the third conductive layer 320 may partially overlap with the second conductive layer 316. Each of the first conductive layer 312, the second conductive layer 316, and the third conductive layer 320 includes a conductive material, such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, copper-aluminum alloys (AlCu), tungsten (W), tungsten alloys, or other suitable materials. Each of the first conductive layer 312, the second conductive layer 316, and the third conductive layer 320 has a thickness ranging from about 20 nm to about 100 nm. Each of the first insulating layer 314 and the second insulating layer 318 comprises an electrically insulating material, such as a high-k dielectric material. In some embodiments, each of the first insulating layer 314 and the second insulating layer 318 comprises zirconium dioxide (ZrO2), aluminum oxide (Al2O3), or titanium dioxide (Ti). x O y ), tantalum oxide (Ta x O y ), titanium oxynitride (Ti x O y N z ), tantalum oxynitride (Ta x O y N x (where x, y, and z can be integers or non-integers) or other suitable materials. Each of the first insulating layer 314 and the second insulating layer 318 has a thickness ranging from about 1 nm to about 10 nm.

[0032] like Figure 3 As shown, the interconnect structure 300 includes a conductive component 304 disposed in a first IMD layer 302a in two regions 380 and 390. The conductive component 304 may be... Figure 2 The topmost conductive component 304 is shown. An etch stop layer 310 is disposed on a first IMD layer 302a, and a second IMD layer 302b is disposed on the etch stop layer 310. The etch stop layer 310 may comprise an oxide or nitride of a metal, such as Al, Ti, Zr, Hf, Y, or other suitable metals. In some embodiments, the etch stop layer 310 comprises an oxide or nitride of a semiconductor, such as silicon. The etch stop layer 310 may be formed by any suitable process, such as CVD or ALD. A third IMD layer 302c is disposed on a passive component 382. Conductive components 324a and 324b are configured to pass through the etch stop layer 310, the second IMD layer 302b, the passive component 382, ​​and the third IMD layer 302c. In some embodiments, the conductive components 324a and 324b are redistribution layers (RDLs). Conductive component 324a is electrically connected to the second conductive layer 316 of passive component 382, ​​and conductive component 324b is electrically connected to the first conductive layer 312 and the third conductive layer 320 of passive component 382. Each conductive component 324a, 324b is aligned with a corresponding conductive component 304 disposed in the first IMD layer 302a. In some embodiments, a barrier layer 322 is disposed between each conductive component 324a, 324b and the etch stop layer 310, the second IMD layer 302b, the passive component 382, ​​and the third IMD layer 302c. Each conductive component 324a, 324b comprises a conductive material, such as Cu, AlCu, or other suitable materials. The barrier layer 322 comprises a conductive material, such as Ti, Ta, TiN, TaN, or other suitable materials. In some embodiments, the barrier layer 322 contacts the corresponding conductive component 304, and the conductive components 324a, 324b contact the corresponding barrier layer 322.

[0033] like Figure 3As shown, in region 390, passive component 392 includes a conductive layer 330 disposed on a second IMD layer 302b. A third IMD layer 302c is disposed on the conductive layer 330. Conductive members 324c and 324d are configured to pass through the etch stop layer 310, the second IMD layer 302b, the passive component 392, and the third IMD layer 302c. In some embodiments, conductive members 324c and 324d are RDLs. Conductive members 324c and 324d are both electrically connected to the conductive layer 330 of passive component 392. Each conductive member 324c and 324d is aligned with a corresponding conductive member 304 disposed in the first IMD layer 302a. In some embodiments, a barrier layer 322 is disposed between each conductive member 324c and 324d and the etch stop layer 310, the second IMD layer 302b, the passive component 392, and the third IMD layer 302c. Conductive components 324c and 324d are made of the same material as conductive components 324a and 324b. In some embodiments, barrier layer 322 contacts the corresponding conductive component 304, and conductive components 324c and 324d contact the corresponding barrier layer 322.

[0034] In some embodiments, the first conductive layer 312, the second conductive layer 316, and the third conductive layer 320 of the passive component 382 comprise the same material, and the conductive layer 330 of the passive component 392 comprises the same material as the first conductive layer 312, the second conductive layer 316, and the third conductive layer 320. In some embodiments, the first conductive layer 312 comprises a first material, the second conductive layer 316 and the third conductive layer 320 comprise a second material, and the conductive layer 330 comprises the first material. The first material has a substantially larger resistivity than the second material. In some embodiments, the second conductive layer 316 comprises the first material, the first conductive layer 312 and the third conductive layer 320 comprise the second material, and the conductive layer 330 comprises the first material. The first material has a substantially larger resistivity than the second material. In some embodiments, the third conductive layer 320 comprises the first material, the first conductive layer 312 and the second conductive layer 316 comprise the second material, and the conductive layer 330 comprises the first material. The first material has a substantially larger resistivity than the second material. In some embodiments, the conductive layer 330 has the same thickness as the first conductive layer 312, the second conductive layer 316, and the third conductive layer 320. In some embodiments, the conductive layer 330 has a thickness smaller than that of the first conductive layer 312, the second conductive layer 316, and the third conductive layer 320.

[0035] As described above, passive component 382 can be a capacitor, and passive component 392 can be a resistor. Although the conductive layer 330 of passive component 392 may include at least one of the first conductive layer 312, the second conductive layer 316, and the third conductive layer 320 of passive component 382, ​​the conductive layer 330 has a significantly smaller resistance due to its size (which is much smaller than the size of conductive layers 312, 316, or 320). Figure 4A and Figure 4B These are plan views of the conductive layers 312 and 330 of passive components 382 and 392 according to some embodiments. Figure 4A and Figure 4B As shown, conductive layer 312 (or conductive layer 316 or 320) has a main surface 402, and conductive layer 330 has a main surface 404. Main surface 402 is substantially larger than main surface 404. Therefore, conductive layer 330 of passive component 392 serves as a resistor in a circuit. In some embodiments, conductive layer 330 has a resistance of tens of thousands of ohms.

[0036] Figures 5 to 8 This is a cross-sectional side view of the top of the interconnect structure 300 according to an optional embodiment. (See attached image.) Figure 5 As shown, a first insulating layer 314 is disposed on the conductive layer 330 in region 390, and a third IMD layer 302c is disposed on the insulating layer 314 in region 390. The first conductive layer 312 of the passive component 382 and the conductive layer 330 of the passive component 392 can be formed by the same patterning process, and the first insulating layer 314 is disposed on the first conductive layer 312 and the conductive layer 330.

[0037] like Figure 6 As shown, the conductive layer 330 of the passive component 392 is disposed between the first insulating layer 314 and the second insulating layer 318, and the third IMD layer 302c is disposed on the second insulating layer 318 in region 390. The first insulating layer 314 is disposed in both regions 380 and 390. The second conductive layer 316 of the passive component 382 and the conductive layer 330 of the passive component 392 can be formed by the same patterning process, and the second insulating layer 318 is disposed on the second conductive layer 316 and the conductive layer 330. In some embodiments, the second insulating layer 318 is not formed in region 390, such as... Figure 7 As shown, the third IMD layer 302c is disposed on the conductive layer 330 in region 390.

[0038] like Figure 8As shown, the second insulating layer 318 can be disposed on the second IMD layer 302b in region 390, and the conductive layer 330 is disposed on the second insulating layer 318. The third conductive layer 320 of the passive component 382 and the conductive layer 330 of the passive component 392 can be formed by the same patterning process.

[0039] Figures 9A to 9I These are cross-sectional side views of various stages of manufacturing the interconnect structure 300 according to some embodiments. Figure 9A As shown, a barrier layer 902 is disposed between each conductive component 304 and a first IMD layer 302a. An etch stop layer 310 is disposed on the first IMD layer 302a in regions 380 and 390, and a second IMD layer 302b is disposed on the etch stop layer 310 in regions 380 and 390. A conductive layer 904 is formed on the second IMD layer 302b in regions 380 and 390. The conductive layer 904 can be a blanket layer formed by any suitable process, such as ECP, PVD, or ALD.

[0040] like Figure 9B As shown, a patterning process is performed on conductive layer 904, and first conductive layer 312 and conductive layer 330 are formed in regions 380 and 390, respectively. The patterning process may include: forming a mask (not shown) on conductive layer 904; patterning the mask; and transferring the pattern of the mask to conductive layer 904 by removing a portion of conductive layer 904. First conductive layer 312 and conductive layer 330 are formed by the same patterning process. In other words, first conductive layer 312 and conductive layer 330 are formed simultaneously.

[0041] like Figure 9C As shown, a mask is formed in region 390 to cover conductive layer 330 and a portion of second IMD layer 302b. The mask may include any suitable material, such as photoresist or bottom anti-reflective coating (BARC) layer. Mask 906 does not cover the first conductive layer 312 and a portion of second IMD layer 302b in region 380.

[0042] like Figure 9D As shown, a first insulating layer 314 is formed on a portion of the second IMD layer 302b and the first conductive layer 312 in region 380, and a conductive layer 908 is formed on the first insulating layer 314 in region 380. The conductive layer 908 can be a blanket layer formed by any suitable process, such as ECP, PVD, or ALD. A portion of the first insulating layer 314 and a portion of the conductive layer 908 formed on the mask 906 in region 390 are not... Figure 9D As shown in the image.

[0043] like Figure 9EAs shown, a patterning process is performed on conductive layer 908, and a second conductive layer 316 is formed in region 380. The portion of conductive layer 908 formed above mask 906 in region 390 can also be removed by the patterning process. The patterning process may include: forming a mask (not shown) on conductive layer 908; patterning the mask; and transferring the pattern of the mask to conductive layer 908 by removing a portion of conductive layer 908.

[0044] like Figure 9F As shown, a second insulating layer 318 is formed on a portion of the first insulating layer 314 and the second conductive layer 316 in region 380, and a third conductive layer 320 is formed on the second insulating layer 318 in region 380. The third conductive layer 320 can be formed by first forming a blanket conductive layer on the second insulating layer 318 and then patterning the blanket conductive layer. The portion of the second insulating layer 318 formed on the mask 906 in region 390 is not shown. Figure 9F As shown in the image.

[0045] like Figure 9G As shown, mask 906, along with the material formed thereon, is removed by any suitable process. Therefore, portions of conductive layer 330 and the second IMD layer 302b are exposed in region 390. Figure 9G As shown, a passive component 382 (such as a capacitor) is formed on a second IMD layer 302b in region 380, and a passive component 392 (such as a resistor) is formed on the second IMD layer 302b in region 390. In some embodiments, a mask (not shown) may be formed on the passive component 382 to protect the passive component 382 before removing the mask 906 and the material formed thereon. A planarization process, such as a chemical mechanical polishing (CMP) process, may be implemented to expose the mask 906 in region 390, and the mask 906 and the mask (not shown) formed on the passive component 382 may be removed by a selective etching process that substantially does not affect the third conductive layer 320, the conductive layer 330, the second insulating layer 318, and the second IMD layer 302b.

[0046] The conductive layer 330 of the passive component 392 and the first conductive layer 312 of the passive component 382 are formed simultaneously, such as Figures 9A to 9G As described in [the text]. However, by forming mask 906 at different times, the conductive layer 330 of passive component 392 can be formed simultaneously with the second conductive layer 316 or the third conductive layer 320 of passive component 382. For example, in some embodiments, mask 906 can be formed at the same time as the conductive layer 904 ( Figure 9A The second IMD layer 302b is formed in region 390 before the first insulating layer 314. The conductive layer 908 can be formed on a portion thereof. Figure 9DBefore the formation of conductive layer 904, mask 906 is removed, and conductive layer 908 is also formed on a portion of the second IMD layer 302b in region 390. Patterning of conductive layer 908 forms second conductive layer 316 and conductive layer 330. In some embodiments, mask 906 may be used before the formation of conductive layer 904. Figure 9A The first insulating layer 314, the second conductive layer 316, and the second insulating layer 318 are formed on a portion of the second IMD layer 302b in region 390. The mask 906 can be removed before forming a conductive layer (not shown) that will be patterned into a third conductive layer 320, and the conductive layer (not shown) is also formed on a portion of the second IMD layer 302b in region 390. The patterning of the conductive layer forms the third conductive layer 320 and the conductive layer 330.

[0047] like Figure 9H As shown, a third IMD layer 302c is formed on portions of passive component 382, ​​passive component 392, and the second IMD layer 302b. The third IMD layer 302c can be formed by any suitable process, such as FCVD. In some embodiments, a CMP process can be implemented such that the top surface of the third IMD layer 302c is flat in regions 380 and 390. Figure 9H As shown, the third IMD layer 302c has a thickness T1 in region 390, and the conductive layer 330 has a thickness T2 in region 390. In some embodiments, the thickness T1 is about 5 to about 20 times the thickness T2. If the thickness T1 is less than about 5 times the thickness T2, a portion of the third IMD layer 302c in region 380 may not be thick enough to cover the passive component 382. On the other hand, if the thickness T1 is greater than about 20 times the thickness T2, the manufacturing cost increases without significant advantage. In some embodiments, the thickness T1 ranges from about 100 nm to about 1000 nm, and the thickness T2 ranges from about 20 nm to about 100 nm. Passive components 382 and 392 are both embedded in the same third IMD layer 302c, and the passive component 392 is formed by the same process used to form the passive component 382. Therefore, the manufacturing cost is reduced, and the manufacturing complexity is decreased. Furthermore, because the capacitor (passive component 382) and resistor (passive component 392) are arranged side-by-side in the semiconductor die, the semiconductor die can be used for RF or mixed-signal circuit designs. For example, in some embodiments, the semiconductor die (or chip) includes passive components 382, ​​392, and device 200 (…). Figure 1A and Figure 1B Inductors (which can be conductive components 324a, 324b, 324c, 324d) and varactor diodes (which are transistors with n-type source and drain in an n-type well), and the semiconductor dies can be used for analog-to-digital converters (ADCs), voltage-controlled oscillators (VCOs), filters, decoupling capacitors or other suitable applications.

[0048] like Figure 9I As shown, barrier layer 322 and conductive components 324a, 324b, 324c, and 324d are formed in third IMD layer 302c, passive components 382 and 392, second IMD layer 302b, and etch stop layer 310.

[0049] Figures 10A to 10F These are cross-sectional side views of various stages of manufacturing the interconnect structure 300 according to an optional embodiment. Figure 10A As shown, a mask 1002 is formed on a portion of the second IMD layer 302b in region 390. The mask 1002 may include elements related to mask 906. Figure 9C It is made of the same material and formed using the same process as mask 906.

[0050] like Figure 10B As shown, the first conductive layer 312 is formed on a portion of the second IMD layer 302b in region 380. Next, as... Figure 10C As shown, mask 1002 is removed, and a first insulating layer 314 is formed in regions 380 and 390. The first insulating layer 314 is formed on a portion of the second IMD layer 302b and the first conductive layer 312 in region 380, and also on a portion of the second IMD layer 302b in region 390. A second conductive layer 316 and a conductive layer 330 are formed on the first insulating layer 314 in regions 380 and 390, respectively. The second conductive layer 316 and the conductive layer 330 can be formed by first forming a blanket conductive layer on the first insulating layer 314 and then patterning the blanket conductive layer.

[0051] like Figure 10D As shown, a mask 1004 is formed on a portion of the conductive layer 330 and the first insulating layer 314 in region 390. Mask 1004 may comprise the same material as mask 1002 and can be formed by the same process as mask 1002. The next step, as... Figure 10E As shown, a second insulating layer 318 and a third conductive layer 320 are formed in region 380. In some embodiments, the mask 1004 is formed after the second insulating layer 318 is formed. Therefore, in some embodiments, a conductive layer 330 is disposed between the first insulating layer 314 and the second insulating layer 318 in region 390. By having a second insulating layer 318 disposed on the conductive layer 330, the conductive layer 330 is protected from the etchant during the removal of the mask 1004.

[0052] like Figure 10FAs shown, after removing mask 1004, a third IMD layer 302c is formed on passive components 382 and 392, and a barrier layer 322 and conductive components 324a, 324b, 324c, and 324d are formed in the third IMD layer 302c, passive components 382 and 392, the second IMD layer 302b, and the etch stop layer 310. Masks 1002 and 1004 can be formed and removed at different times to form... Figure 6 , Figure 7 and Figure 8 The interconnection structure 300 shown is illustrated.

[0053] The present invention provides interconnect structures and methods of forming thereof in various embodiments. In some embodiments, the interconnect structure includes two different passive components (such as passive components 382, ​​392) disposed in the same IMD layer (such as a third IMD layer 302c). Passive components 382, ​​392 are formed using the same process. Some embodiments may achieve advantages. For example, because passive components 382, ​​392 are formed using the same process, manufacturing costs are reduced and manufacturing complexity is decreased.

[0054] The embodiment is an interconnect structure. The structure includes: a first inter-metal dielectric (IMD) layer disposed over a plurality of conductive components; and a first passive component disposed on the first IMD layer in a first region of a substrate. The first passive component is a capacitor. The structure further includes: a second passive component disposed on the first IMD layer in a second region of the substrate. The second passive component is a resistor including a first conductive layer, and the first conductive layer has a first thickness. The structure further includes: a second IMD layer disposed on the first passive component in the first region and on portions of the second passive component and the first IMD layer in the second region. The top surface of the second IMD layer in the first and second regions is substantially flat, and the second IMD layer has a second thickness ranging from about five times to about 20 times the first thickness.

[0055] Another embodiment is an interconnect structure. The structure includes: a first inter-metal dielectric (IMD) layer disposed over a plurality of conductive components; and a first passive component disposed on the first IMD layer in a first region of a substrate. The first passive component includes a first conductive layer, a first insulating layer disposed on the first conductive layer, a second conductive layer disposed on the first insulating layer, a second insulating layer disposed on the second conductive layer, and a third conductive layer disposed on the second insulating layer. The structure further includes: a second passive component disposed over the first IMD layer in a second region of the substrate. The second passive component includes a fourth conductive layer disposed over the first IMD layer in the second region, and an insulating layer disposed on the fourth conductive layer in the second region. The structure also includes a second IMD layer disposed on the third conductive layer in the first region and on the insulating layer in the second region.

[0056] A further embodiment is a method. The method includes: forming a first intermetallic dielectric (IMD) layer over a plurality of conductive components; and forming a first passive component over the first IMD layer. Forming the first passive component over the first IMD layer includes: forming a first conductive layer over the first IMD layer; forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming a second insulating layer on the second conductive layer; and forming a third conductive layer on the second insulating layer. The method further includes: forming a second passive component over the first IMD layer. Forming the second passive component over the first IMD layer includes forming a fourth conductive layer over the first IMD layer, and the fourth conductive layer is formed simultaneously with the first conductive layer, the second conductive layer, or the third conductive layer. The method further includes forming a second IMD layer on the first passive component and the second passive component.

[0057] Some embodiments of this application provide an interconnect structure disposed above a substrate, comprising: a first inter-metal dielectric (IMD) layer disposed above a plurality of conductive components; a first passive component disposed on the first IMD layer in a first region of the substrate, wherein the first passive component is a capacitor; a second passive component disposed on the first IMD layer in a second region of the substrate, wherein the second passive component is a resistor including a first conductive layer, and the first conductive layer has a first thickness; and a second IMD layer disposed on the first passive component in the first region and on the second passive component and a portion of the first IMD layer in the second region, wherein the top surfaces of the second IMD layer in the first region and the second region are substantially flat, and the second IMD layer has a second thickness ranging from 5 times to 20 times the first thickness. In some embodiments, the interconnect structure further comprises: a third IMD layer, wherein the plurality of conductive components are disposed in the third IMD layer. In some embodiments, the interconnect structure further comprises: an etch stop layer disposed between the first IMD layer and the third IMD layer. In some embodiments, the first passive component includes: a second conductive layer; a third conductive layer partially overlapping the second conductive layer; and a fourth conductive layer partially overlapping the third conductive layer. In some embodiments, the second conductive layer, the third conductive layer, and the fourth conductive layer comprise the same material. In some embodiments, the first conductive layer comprises the same material as the second conductive layer, the third conductive layer, and the fourth conductive layer. In some embodiments, the second conductive layer, the third conductive layer, and the fourth conductive layer comprise different materials. In some embodiments, the first conductive layer comprises the same material as at least one of the second conductive layer, the third conductive layer, and the fourth conductive layer. In some embodiments, the first passive component further includes: a first insulating layer disposed between the second conductive layer and the third conductive layer; and a second insulating layer disposed between the second conductive layer and the third conductive layer. In some embodiments, the first insulating layer is disposed between the first intermetallic dielectric layer and the first conductive layer in the second region. In some embodiments, the second insulating layer is disposed between the first intermetallic dielectric layer and the first conductive layer in the second region.

[0058] Other embodiments of this application provide an interconnect structure disposed above a substrate, comprising: a first inter-metal dielectric (IMD) layer disposed above a plurality of conductive components; a first passive component disposed on the first IMD layer in a first region of the substrate, wherein the first passive component comprises: a first conductive layer; a first insulating layer disposed on the first conductive layer; a second conductive layer disposed on the first insulating layer; a second insulating layer disposed on the second conductive layer; and a third conductive layer disposed on the second insulating layer; a second passive component disposed above the first IMD layer in a second region of the substrate, wherein the second passive component includes a fourth conductive layer disposed above the first IMD layer in the second region, and an insulating layer disposed on the fourth conductive layer in the second region; and a second IMD layer disposed on the third conductive layer in the first region and the insulating layer in the second region. In some embodiments, each of the first insulating layer and the second insulating layer comprises a high-k dielectric material. In some embodiments, the interconnect structure further includes: a first conductive component configured to pass through the second inter-metal dielectric layer, the second conductive layer, the first insulating layer, and the first inter-metal dielectric layer in the first region; a second conductive component configured to pass through the second inter-metal dielectric layer, the third conductive layer, the second insulating layer, the first insulating layer, the first conductive layer, and the first inter-metal dielectric layer in the first region; a third conductive component configured to pass through the second inter-metal dielectric layer, the insulating layer, the fourth conductive layer, and the first inter-metal dielectric layer in the second region; and a fourth conductive component configured to pass through the second inter-metal dielectric layer, the insulating layer, the fourth conductive layer, and the first inter-metal dielectric layer in the second region. In some embodiments, the first conductive layer comprises the same material as the fourth conductive layer, and the insulating layer is the first insulating layer. In some embodiments, the second conductive layer comprises the same material as the fourth conductive layer, and the insulating layer is the second insulating layer. In some embodiments, the fourth conductive layer is disposed on the first insulating layer in the second region, and the first insulating layer is disposed on the first inter-metal dielectric layer in the second region.

[0059] Further embodiments of this application provide a method for forming an interconnect structure, including: forming a first inter-metal dielectric (IMD) layer over a plurality of conductive components; forming a first passive component over the first IMD layer, including: forming a first conductive layer over the first IMD layer; forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming a second insulating layer on the second conductive layer; and forming a third conductive layer on the second insulating layer; forming a second passive component over the first IMD layer, including: forming a fourth conductive layer over the first IMD layer, wherein the fourth conductive layer is formed simultaneously with the first conductive layer, the second conductive layer, or the third conductive layer; and forming a second IMD layer on the first passive component and the second passive component. In some embodiments, the method further includes: forming a mask on the fourth conductive layer before forming the first insulating layer. In some embodiments, the first insulating layer is formed on the first conductive layer and the fourth conductive layer.

[0060] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. An interconnect structure disposed above a substrate, comprising: a first intermetal dielectric (IMD) layer disposed above a plurality of conductive components; a first passive component disposed on the first intermetal dielectric layer in a first region of the substrate, wherein the first passive component is a capacitor; a second passive component disposed on the first intermetal dielectric layer in a second region of the substrate, wherein the second passive component is a resistor comprising a first conductive layer and the first conductive layer has a first thickness; and a second intermetal dielectric layer disposed on the first passive component in the first region and on the second passive component and a portion of the first intermetal dielectric layer in the second region, wherein a top surface of the second intermetal dielectric layer in the first region and the second region is substantially planar and the second intermetal dielectric layer has a second thickness ranging from 5 times to 20 times the first thickness, wherein the first passive component comprises: a second conductive layer; a third conductive layer partially overlapping the second conductive layer; and a fourth conductive layer partially overlapping the third conductive layer, wherein a major surface of the second conductive layer, the third conductive layer, and the fourth conductive layer, as viewed from top down, is greater than a major surface of the first conductive layer.

2. The interconnect structure of claim 1, further comprising: a third intermetal dielectric layer, wherein the plurality of conductive components are disposed in the third intermetal dielectric layer.

3. The interconnect structure of claim 2, further comprising: an etch stop layer disposed between the first intermetal dielectric layer and the third intermetal dielectric layer.

4. The interconnect structure of claim 3, wherein, the etch stop layer comprises an oxide or a nitride of a metal.

5. The interconnect structure of claim 1, wherein, the second conductive layer, the third conductive layer, and the fourth conductive layer comprise a same material.

6. The interconnect structure of claim 5, wherein, the first conductive layer comprises a same material as the second conductive layer, the third conductive layer, and the fourth conductive layer.

7. The interconnect structure of claim 1, wherein, the second conductive layer, the third conductive layer, and the fourth conductive layer comprise different materials.

8. The interconnect structure of claim 7, wherein, the first conductive layer comprises a same material as at least one of the second conductive layer, the third conductive layer, and the fourth conductive layer.

9. The interconnect structure of claim 1, wherein, the first passive component further comprises: a first insulating layer disposed between the second conductive layer and the third conductive layer; and a second insulating layer disposed between the second conductive layer and the third conductive layer.

10. The interconnect structure of claim 9, wherein, the first insulating layer is disposed between the first intermetal dielectric layer and the first conductive layer in the second region.

11. The interconnect structure of claim 9, wherein, the second insulating layer is disposed between the first intermetal dielectric layer and the first conductive layer in the second region.

12. An interconnect structure disposed above a substrate, comprising: a first intermetal dielectric (IMD) layer disposed above a plurality of conductive components; a first passive component disposed on the first intermetal dielectric layer in a first region of the substrate, wherein the first passive component comprises: a first conductive layer; a first insulating layer disposed on the first conductive layer; a second conductive layer disposed on the first insulating layer; a second insulating layer disposed on the second conductive layer; and a third conductive layer disposed on the second insulating layer; a second passive component disposed over the first intermetallic dielectric layer in a second region of the substrate, wherein the second passive component includes a fourth conductive layer disposed over the first intermetallic dielectric layer in the second region, and an insulating layer disposed on the fourth conductive layer in the second region; and a second intermetallic dielectric layer disposed on the third conductive layer in the first region and on the insulating layer in the second region, wherein, viewed from the top, a major surface of the first conductive layer, the second conductive layer, and the third conductive layer is larger than a major surface of the fourth conductive layer.

13. The interconnect structure of claim 12, wherein, The first insulating layer and the second insulating layer each include a high-k dielectric material.

14. The interconnect structure of claim 12, further comprising: a first conductive feature disposed through the second intermetallic dielectric layer, the second conductive layer, the first insulating layer, and the first intermetallic dielectric layer in the first region; a second conductive feature disposed through the second intermetallic dielectric layer, the third conductive layer, the second insulating layer, the first insulating layer, the first conductive layer, and the first intermetallic dielectric layer in the first region; a third conductive feature disposed through the second intermetallic dielectric layer, the insulating layer, the fourth conductive layer, and the first intermetallic dielectric layer in the second region; and a fourth conductive feature disposed through the second intermetallic dielectric layer, the insulating layer, the fourth conductive layer, and the first intermetallic dielectric layer in the second region. The first conductive layer includes the same material as the fourth conductive layer, and the insulating layer is the first insulating layer.

15. The interconnect structure of claim 12, wherein, The second conductive layer includes the same material as the fourth conductive layer, and the insulating layer is the second insulating layer.

16. The interconnect structure of claim 12, wherein, The fourth conductive layer is disposed on the first insulating layer in the second region, and the first insulating layer is disposed on the first intermetallic dielectric layer in the second region.

17. The interconnect structure of claim 16, wherein, 18. A method of forming an interconnect structure, comprising: forming a first intermetallic dielectric (IMD) layer over a plurality of conductive features; forming a first passive component over the first intermetallic dielectric layer, comprising: forming a first conductive layer over the first intermetallic dielectric layer; forming a first insulating layer on the first conductive layer; forming a second conductive layer on the first insulating layer; forming a second insulating layer on the second conductive layer; and forming a third conductive layer on the second insulating layer; forming a second passive component over the first intermetallic dielectric layer, comprising: forming a fourth conductive layer over the first intermetallic dielectric layer, wherein the fourth conductive layer is formed simultaneously with the first conductive layer, the second conductive layer, or the third conductive layer; and forming a second intermetallic dielectric layer on the first passive component and the second passive component, wherein, viewed from the top, a major surface of the first conductive layer, the second conductive layer, and the third conductive layer is larger than a major surface of the fourth conductive layer. forming a mask on the fourth conductive layer prior to forming the first insulating layer.

19. The method of claim 18, further comprising: ​ 20. The method of claim 18, wherein, The first insulating layer is formed on the first conductive layer and the fourth conductive layer. The first insulating layer is formed on the first conductive layer and the fourth conductive layer.

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