Integrated circuit structure with fluorescent material and related methods

Abstract

The present disclosure provides an integrated circuit (IC) structure having a fluorescent material and related methods. An IC structure according to the present disclosure can include a layer of fluorescent material located on an IC component. The layer of fluorescent material defines a portion of an identification mark for the IC structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to integrated circuits (ICs). More specifically, embodiments of the present disclosure provide a structure and related methods for verifying such a structure. BACKGROUND

[0002] In the microelectronics industry, the ability of certain participants to modify chips is of increasing concern. The effects of unauthorized modifications range from benign effects (e.g., incoherent data on a display) to serious malfunctions (e.g., an unstable pacemaker clock). In some cases, these effects can be difficult to distinguish from random errors and / or degradation caused by aging. As cooperation between global manufacturers becomes increasingly important for manufacturing efficiency, control of sensitive events and / or transfers in the supply chain also becomes increasingly important for manufacturers and customers. SUMMARY

[0003] Aspects of the present disclosure provide an integrated circuit (IC) structure comprising: a layer of fluorescent material on an IC component, wherein the layer of fluorescent material defines a portion of an identification mark for the IC structure.

[0004] Further aspects of the present disclosure provide a method of verifying an integrated circuit (IC) structure, the method comprising: detecting a layer of fluorescent material on an IC component, wherein the detected layer of fluorescent material defines a portion of an identification mark for the IC structure; and comparing the identification mark to a verification map for the IC structure to verify the IC structure.

[0005] Other aspects of the present disclosure provide an integrated circuit (IC) structure comprising: an IC component on a substrate; and a layer of fluorescent material on the IC component, wherein the layer of fluorescent material defines a portion of an identification mark for the IC structure. BRIEF DESCRIPTION OF DRAWINGS

[0006] These and other features of the present disclosure will be more readily understood from the following detailed description of the various aspects of the present disclosure, taken in conjunction with the accompanying drawings, which illustrate various embodiments of the present disclosure, in which:

[0007] Figure 1 A plan view of an IC structure with fluorescent material and a tool for verifying the IC structure according to embodiments of the present disclosure is shown.

[0008] Figure 2 A cross-sectional view of a portion of an IC structure in which fluorescent material can be formed according to embodiments of the present disclosure is shown.

[0009] Figure 3 A cross-sectional view of forming fluorescent material on an IC structure according to embodiments of the present disclosure is shown.

[0010] Figure 4 A cross-sectional view showing further processing and illumination of the IC structure to detect the fluorescent material according to embodiments of the present disclosure is shown.

[0011] Figure 5 A cross-sectional view showing formation of the fluorescent material within the via opening according to embodiments of the present disclosure is shown.

[0012] Figure 6 A cross-sectional view showing filling of the via opening with the fluorescent material and via metal and illumination to detect the fluorescent material according to embodiments of the present disclosure is shown.

[0013] Figure 7 A cross-sectional view showing filling of the via opening with a non-metallic via according to further embodiments of the present disclosure is shown.

[0014] Figure 8 A cross-sectional view showing the IC structure with the via having the fluorescent material electrically disconnected from the circuit according to embodiments of the present disclosure is shown.

[0015] Figure 9 A cross-sectional view showing the semiconductor substrate having a trench to be filled with the fluorescent material according to embodiments of the present disclosure is shown.

[0016] Figure 10 A cross-sectional view showing filling of the trench with the fluorescent material and illumination of the fluorescent material according to embodiments of the present disclosure is shown.

[0017] Figure 11 An exemplary flowchart of a method for forming, detecting, and verifying an IC structure having a fluorescent material according to embodiments of the present disclosure is shown.

[0018] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents similar elements between the figures. DETAILED DESCRIPTION

[0019] In the following description, reference is made to the accompanying drawings which form a part hereof, and in which are shown by way of illustration specific exemplary embodiments in which the teachings can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the teachings, and it is to be understood that other embodiments can be utilized and that changes can be made without departing from the scope of the present teachings. The following description is, therefore, not to be taken in a limiting sense.

[0020] It will be understood that when an element as a layer, region or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0021] Reference throughout this specification to "one embodiment" or "an embodiment" or "exemplary embodiment" or similar term means that a particular feature, structure, characteristic, or change being referred to can be included in at least one embodiment of the present disclosure. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" or any other similar term in various places throughout this specification are not necessarily referring to the same embodiment. It is appreciated that any of the features, structures, characteristics, or changes that are described in connection with one embodiment can be included in at least one other embodiment. Furthermore, it is appreciated that any of the features, structures, characteristics, or changes that are described in connection with one embodiment can be included in at least one other embodiment.

[0022] Embodiments of the present disclosure provide structures and methods for verifying integrated circuit (IC) structures, for example, to determine whether a product has been modified without authorization. Embodiments of the present disclosure can provide an IC structure in which a layer of fluorescent material is located on an IC component. The fluorescent material can be formed as a single region or as part of a pattern of regions. The layer of fluorescent material defines a portion of an identification mark for the IC structure. By using a tool for illuminating the fluorescent material, an analyst can compare the location of the fluorescent material to a map for the IC structure to verify the authenticity of the product. The fluorescent material can be formed as a film of material in contact with various surfaces of metal layers, vias, substrates, and / or any other conceivable components within the IC structure. Further, the component coated with the fluorescent material can or can not be included in an electrically active area of the IC structure.

[0023] Verifying the IC structure can be accomplished using a verification map for the IC structure that indicates the location of the fluorescent material and / or other identification features of the IC structure. The verification map can be provided only to a recipient of the IC structure, for example, through a secure communication channel. The recipient can inspect the IC structure to see whether the fluorescent material locations match the corresponding locations in the verification map. In some cases, each different unit of the IC structure can have a unique verification map.

[0024] Reference Figure 1 Embodiments of the present disclosure can include and / or be implemented on an integrated circuit (IC) structure 100. Further, the methods described herein can be implemented on the IC structure 100 to verify whether the structure or portions thereof have been modified without authorization. Figure 1 The illustrated IC structure 100 can represent a portion of a larger structure that extends across a two-dimensional region in a plane X-Y. The IC structure 100 can include several IC components 102 distributed across a region 104 (e.g., insulating material and / or other material separating the IC components 102 from one another). In various applications, the region 104 can include only a portion of the IC structure 100 or include the entirety of the IC structure 100. The IC components 102 can include any conceivable active or inactive components of the IC structure 100, for example, for serving various operational and / or manufacturing purposes.

[0025] According to one example, the IC components 102 in the IC structure 100 can include electrically active conductors, such as wires, vias, etc., for transporting electrical current through the IC structure 100. In further non-limiting examples, the IC components 102 can include, for example, active or passive semiconductor materials, conductors, insulators, transistors, capacitors, inductors, liners, guard rings, etc. In additional examples, the IC components 102 can include component subassemblies, such as logic gates, inverters, amplifiers, clocks, power supplies, photonic components, etc. In Figure 1 In the example of FIG. 1, the IC components 102 are illustrated as vias (extending into or out of the X-Y plane) that are separated by portions of insulator material distributed across the region 104. While certain portions of the IC components 102 can be interconnected, they can include different structures and / or materials that can be used with the various fluorescent materials described herein.

[0026] Embodiments of the IC structure 100 can include fluorescent materials 108 located on a portion of the IC components 102. In Figure 1 In the example of FIG. 1, several layers of fluorescent materials 108 are adjacent sidewalls of various IC components 102 within the region 104. However, other IC components 102 lack fluorescent materials 108 and can therefore be distinguished from the IC components 102 having fluorescent materials 108 within the region 104. The fluorescent materials 108 can include any now known or later developed material that exhibits fluorescence when subjected to light radiation (e.g., in the visible spectrum and / or wavelengths detectable by radiation sensitive equipment). Fluorescence refers to radiation emitted by a substance during exposure to a source of radiation (e.g., light, X-rays, etc.). In one example, the fluorescent materials 108 can include diamond. In a more specific example, the fluorescent materials 108 can include synthetic diamond deposited by chemical vapor deposition (CVD). In the case of CVD deposited synthetic diamond, the fluorescent materials 108 can be manufactured to exhibit a particular kind of fluorescence (e.g., having a particular color of wavelength) when deposited on the IC components 102. Thus, the fluorescent materials 108 can be invisible to users and / or certain tools unless a particular wavelength of radiation is applied. The fluorescent materials 108 can be formed on various IC components 102, including, as non-limiting examples: a metal layer including a last metal layer, a liner on a TSV and / or via (whether or not these components have electrical functionality), a layer in an interlayer dielectric region, a layer in a cut-through via, a pattern on a backside surface or other surface of a semiconductor substrate, etc.

[0027] Various systems, such as analysis component 120, can verify IC structure 100 by analyzing fluorescent material 108. Analysis component 120 may include radiation source 122, i.e., one or more lamps, diodes, and / or any instrument now known or later developed capable of generating radiation (e.g., light) within the UV spectral band or other desired wavelengths. Radiation source 122 can transmit radiation to region 104 of IC structure 100. Various portions of IC structure 100 can absorb and / or reflect radiation from radiation source 122. Fluorescent material 108 can exhibit fluorescence upon receiving radiation within a specific frequency range. In this case, an observer, such as a person, testing tool (e.g., photodetector), can observe a specific color and / or type of fluorescence within region 104 of IC structure 100. Specifically, fluorescence will be detected at IC component 102 having fluorescent material 108, while no fluorescence will be detected near IC component 102 without fluorescent material 108.

[0028] The fluorescence of the fluorescent material 108 at certain IC components 102 can indicate whether the IC structure 100 has been modified without authorization. In some cases, the analysis component 120 may include a computing device 130 for implementing the method according to this disclosure. The computing device 130 may be electrically coupled to the radiation source 122 (e.g., via a method such as...). Figure 1 The computing device 130 may be electrically and / or data coupled (as shown), or it may be independent of the radiation source 122. Where applicable, the computing device 130 may include computing architectures, such as processor units, input / output (I / O) interfaces, memory, buses, etc., for coupling to the radiation source 122 and / or implementing various functions. In some cases, the computing device 130 may be in the form of control circuitry. The computing device 130 may include hardware and / or software for receiving data relating to the location of the fluorescent material 108 on the IC structure 100 (e.g., transmitted from a user or another component coupled to the computing device 130). Using such data, the computing device 130 can compare the observed fluorescence and / or location with a verification diagram 132 of the IC structure 100.

[0029] The verification map 132 can provide a model or other representation of the regions 104 to cross-reference various locations with the assigned locations of the fluorescent material 108. Thus, the verification map 132 verifies the IC structure 100 based on whether the fluorescent material 108 appears in the portions of the regions 104 where they are assigned to appear and does not appear in other locations. In further implementations, the verification map 132 can specify certain types of IC components 102 in which the fluorescent material 108 is to appear or not appear. In further implementations, the verification map 132 can not be provided on the computing device 130, but can be documented for reference by any conceivable media form (e.g., a non-electronically stored document).

[0030] Embodiments of the present disclosure allow the fluorescent material 108 to be formed at multiple locations on the IC structure 100 (e.g., different types of IC components 102). Regardless of any structural and / or processing variations required to provide the fluorescent material 108 at different locations and / or on different types of IC components 102, the fluorescent material 108 can function substantially as described herein with respect to Figure 1

[0031] Figure 2 An initial structure 200 is shown prior to being processed into an embodiment of the IC structure 100. The processing of the structure 200 is discussed to illustrate how the fluorescent material 108 can be incorporated into a product. Figure 2 A cross-sectional view of the structure 200 is shown having an insulator 202 in which one or more metal wires 204 can be formed. The insulator 202 can be formed of any now known or later developed substance for providing electrical insulation and can include, by way of example, silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides (i.e., organosilicates) including silicon (Si), carbon (C), oxygen (O), and / or hydrogen (H) atoms, thermoset polyarylene ether, spin-on silicon-containing carbon polymeric materials, near frictionless carbon (NFC), or layers constructed therefrom. In some cases, for example, when the structure 200 is on another conductive layer and / or dielectric material layer, the insulator 202 can be an interlayer dielectric (ILD) layer for spacing apart different conductive layers of the structure.

[0032] ​Structure 200 may include one or more metal wirings 204 for interconnecting various components through an insulator 202 of one metal level and / or from one metal level to another. The metal wirings 204 may include one or more conductive materials formed by deposition and / or etching, and may include a combination of vertical and horizontal extensions formed, for example, by dual damascene formation. The metal wirings 204 may include one or more conductive metals, metal alloys, etc., and thus may include copper (Cu), aluminum (Al), gold (Au), etc. The metal wirings 204 may also be formed on, for example, a refractory metal liner 206 to prevent electromigration degradation and / or to separate the conductive material of the metal wirings 204 from the insulator 202 or other adjacent materials. The refractory metal liner 206 may include, for example, but not limited to, materials such as tantalum nitride (TaN) and tantalum; tantalum nitride, tantalum and cobalt, or combinations thereof.

[0033] Structure 200 may include additional insulating material layers to further isolate the different metal layers from each other. For example, structure 200 may include an insulating film 208 in the form of, for example, doped silicon carbide and / or other insulating materials with similar properties. Structure 200 may additionally or alternatively include at least one nitride region 210 (e.g., mid-stage (MOL) nitride) extending laterally through insulator 202. Nitride region 210 may have electrical insulating properties similar to the rest of insulator 202, but may include a different chemical composition. More specifically, nitride region 210 may be composed of a material with greater wet etch resistance than the rest of insulator 202, as discussed elsewhere herein. In cases where insulator 202 comprises a nitride material, nitride region 210 may be composed of a different nitride material having a stronger resistance to structural modifications (e.g., various forms of etching during manufacturing) than insulator 202 (e.g., silicon nitride (Si3N4)).

[0034] like Figure 2 The structure 200 shown is at a stage where only the subsequent metal level 212 is partially formed. In some cases, the subsequent metal level 212 can be a final metal level formed in addition to, for example, ten or more different metal levels. Embodiments of this disclosure allow fluorescent material 108 ( Figure 1 While it is still forming, it is embedded into the subsequent metal layer 212. The subsequent metal layer 212 can be considered as a type of IC component 102 on which fluorescent material 108 can be formed. Figure 1 ). Figure 2A conductor layer 214 is shown deposited within openings in insulator 202 and on portions of the upper surface of insulator 202. In the case of a final metal layer, conductor layer 214 may comprise aluminum, or in the case of other metal layers and / or technical applications, may comprise other conductors described herein (e.g., copper, gold, etc.). As discussed herein, a refractory metal liner 206 is located below and / or alongside portions of conductor layer 214 to prevent degradation and to separate it from insulator 202. One or more openings 216 may be adjacent to portions of conductor layer 214, for example, to be filled with various insulating and / or lining materials in subsequent fabrication. Thus, embodiments of this disclosure can integrate the formation of fluorescent materials into the lining of conductor layer 214.

[0035] Figure 3 The process of lining conductor layer 214 with fluorescent material 108 and other electrically insulating material films is shown. For example, an insulating liner 218 can be formed on conductor layer 214 and opening 216 ( Figure 2 Within, for example, by deposition to the desired thickness. The insulator liner 218 may have the same composition and / or similar dielectric constant as the insulator 202 and / or other insulating materials described herein. Additionally or alternatively, embodiments of this disclosure may include forming a nitride liner 220 on the insulator liner 218 or otherwise on the conductor layer 214 and / or within the opening 216. The nitride liner 220 may include any nitride insulating material now known or developed later, including those previously described with respect to the nitride region 210. Regardless of the use of liners 218 and 220, further processing may include forming the fluorescent material 108 on the subsequent metal layer 212 (e.g., above the conductor layer 214) by chemical vapor deposition and / or other techniques suitable for forming a layer of fluorescent material 108 on the exposed surface. With the fluorescent material 108 in place, further processing may continue substantially according to known techniques to form the metal layer of the product.

[0036] Figure 4Further processing to produce the IC structure 100 according to embodiments of the present disclosure is shown. Here, some portions of the insulator liner 218, the nitride liner 220, and / or the phosphor material 108 can be removed from a target location above the conductor layer 214 (e.g., by etching with the aid of a mask (not shown) to form the opening 222). The opening 222 can define a site for coupling from the subsequent metal level 212 to an external coupling element (e.g., a solder ball, an intermediate conductor, an additional metal level, etc.). The formation of these components above and / or within the opening 222 is generally known and thus is not discussed in further detail. In any case, the formation of the phosphor material 108 in the subsequent metal level 212 allows the radiation source 122 to detect the presence of the phosphor material 108 on the subsequent metal level 212. Other components of the subsequent metal level 212 can be transparent or non-phosphorescent, and thus the presence of various other conductive and / or insulative components within the subsequent metal level 212 does not affect the ability of the radiation source 122 to transmit radiation to the phosphor material 108. Other portions of the subsequent metal level 212 and / or other metal levels of the IC structure 100 can not include the phosphor material 108. Thus, the inclusion or lack of the phosphor material 108 in identifiable locations of the IC structure 100 allows a user to verify whether the IC structure 100 has been modified without authorization by the radiation source 122. That is, the mere presence of the phosphor material 108 in the IC structure 100 does not, by itself, verify whether a given product or unit is genuine. Rather, one or more products can be verified based on whether the phosphor material 108 is located at corresponding locations to the verification map 132 Figure 1 ) or other representations of the IC structure 100 to indicate whether the product is genuine.

[0037] Referring now to Figure 5 , embodiments of the present disclosure can allow the phosphor material 108 to be formed as an intermediate liner between other types of structures and / or locations. Figure 5 An initial structure 230 having a substrate 232 is shown, upon and within which various other components can be formed. The substrate 232 can include, for example, one or more semiconductor materials. More specifically, the substrate 232 can include, but is not limited to, silicon, germanium, silicon germanium, silicon carbide, or any other common IC semiconductor substrate. The entirety of the substrate 232 or a portion thereof can be strained. The substrate 232 can include, for example, a via opening 234 extending at least partially into the substrate 232. The via opening 234 can be formed by masking and etching of the substrate 232 to define a location for forming a conductive material that can extend vertically from one side of the substrate 232 to the other.

[0038] Figure 5The substrate 232 is shown prior to formation of the conductive material therein. For example, an insulator liner 218 can be formed on the substrate 232 and within the via opening 234, and the insulator liner 218 can include the same materials and / or similar insulator materials described with respect to other embodiments. A phosphor material 108 can be formed on the insulator liner 218 (or, in some cases, directly on the substrate 232 and / or within the via opening 234) as an additional layer, substantially as described in other implementations. Further processing can include forming a nitride liner 220 on the phosphor material 108 and within a portion of the via opening 234 (e.g., by deposition), substantially as described in other implementations. Here, the phosphor material 108 can be an intermediate liner between the two other materials (e.g., the insulator liner 218 and the nitride liner 220) for the conductive material formed in the opening 234.

[0039] With reference to Figure 6 , embodiments of the present disclosure can include forming a via metal 236 in the via opening 234 Figure 5 ) with the phosphor material 108 in place, the via metal 236 can be formed in the via opening 234 by deposition, optionally with (and / or between) the liners 218, 220. The via metal 236 can include, for example, at least one of copper, tungsten, tantalum, titanium, etc. The via metal 236 can have a height of, for example, approximately 10 micrometers (pm) to approximately 120 pm, or more specifically, a height of between approximately 50 pm to approximately 60 pm. The via metal 236 can have a cross-sectional width or diameter of approximately 10 pm. However, it should be understood that embodiments of the present disclosure can be equally applicable to via metals 236 having a height greater than 120 pm and / or a diameter less than 10 pm (e.g., 5 pm or less).

[0040] Turning now to Figure 7 , further embodiments of the present disclosure can include forming a non-metallic via 238 in the via opening 234 Figure 5 ) can include, for example, a non-conductive material, such as borophosphosilicate glass (BPSG) and / or any other conceivable material capable of being formed within the via opening 234, for example, by deposition. In yet another example, the non-metallic via 238 can include the same phosphor material that can be used to form the phosphor material 108. In embodiments where the non-metallic via 238 is formed and includes the phosphor material therein, portions of the liners 218, 220 and / or other liner materials within the via opening 234 can be omitted. Thus, the non-metallic via 238 can include any non-conductive substance now known or later developed for providing an electrically passive region, and / or it can itself include the phosphor material 108 capable of being detected by the radiation source 122.

[0041] Referring to Figure 6 and 7 Further processing of the IC structure 100, whether or not via metal 236 or non-metallic via 238 is formed, can include planarization (e.g., using chemical mechanical planarization (CMP)) to the upper surface of the insulator liner 218 (or, alternatively, to other layers planarized to the substrate 232 and / or above). Planarization of the IC structure 100 can enable a desired size of any via metal 236 and / or non-metallic via 238 within the substrate 232. With the via metal 236 and / or non-metallic via 238 in place, the IC structure 100 can include the IC component 102 in the form of a silicon through-silicon via (TSV) 240 within the substrate 232. Figure 1 The radiation source 122 can radiate the TSV 240, and the fluorescent material 108 on the TSV 240 and / or included within the non-metallic via 238 can be detected when the radiation source 122 is active. Further, other portions of the substrate 232 can be removed to bond the TSV 240 to other components within and / or outside of the IC structure 100.

[0042] Figure 8 Other implementations of the IC structure 100 are shown in which the TSV 240 (possibly including via metal 236 and / or non-metallic via 238) is not used for electrical purposes, but rather provides a site at which the fluorescent material 108 is located. In this case, an insulator 202 (e.g., an ILD as discussed herein) can be formed on the insulator liner 218, with various metal wiring 204 formed within the insulator 202. The metal wiring 204 can include a refractory metal liner 206 as described elsewhere herein Figures 2-4 , and such a liner is omitted in Figure 7 for simplicity of illustration. In alternative implementations, one or more of the metal wiring 204 can be formed to reach and / or contact the TSV 240. However, Figure 8 An example is shown in which a set of active circuitry 242 with metal wiring 204 is physically and electrically decoupled from the TSV 240. In this case, the TSV 240 does not provide an electrical operational function within the IC structure 100. Nonetheless, the fluorescent material 108 can still be formed on the sidewalls of the TSV 240. Here, the radiation source 122 is able to transmit radiation to the TSV 240 to identify the fluorescent material 108 thereon. Thus, for example, in the case that the TSV 240 is disconnected from the circuitry 242, the IC component 102 with the fluorescent material 108 can not include an operational component in the IC structure 100.

[0043] Turning now to Figure 9 and 10Embodiments of the present disclosure can be implemented such that the substrate 232 itself is the IC component 102 Figure 1 ) on which the phosphor material 108 is formed. For example, the initial structure 250 (only Figure 8 ) can include one or more trenches 252 (only Figure 8 ) formed directly in the substrate 232. The trenches 252 can extend partially into the substrate 232 and can not expose any material other than the composition of the substrate 232 itself. In particular, the trenches 252 can be formed within a particular surface or region of the substrate 232 that does not have electrically operated components.

[0044] In one example, the trenches 252 can be located within a backside surface 254 of the substrate 232. The backside surface 254 can be vertically opposite a surface of the substrate 232 on which devices and / or other overlying components can be formed. The backside surface 254 typically does not include active structures or devices, and thus the phosphor material 108 can be formed within the backside surface 254 of the substrate 232 without interfering with operational elements. The trenches 252 can be formed within the backside surface 254 after other processing is complete, for example after the backside surface 254 is polished to a reduced thickness. In another example, the trenches 252 can be formed in a dicing region of the IC structure 100.

[0045] However, as embodied, the trenches 252 optionally do not have additional material, such as the various insulating and / or conductive materials discussed herein. The one or more trenches 252 can then be filled with the phosphor material 108, for example using CVD and other processes suitable for forming the phosphor material 108. In some cases, only some of the trenches 252 can be filled with the phosphor material 108, while other trenches 252 can be filled with a non-phosphor material 256 (only Figure 9 ) (e.g., any conceivable material that lacks phosphorescence, such as conventional insulators and / or conductors, as defined herein). The radiation source 122 can be used with the substrate 232 to identify the location of the phosphor material 108, as described elsewhere herein. The locations of the phosphor material 108 and the non-phosphor material 256 can thereby define a mark for identifying the IC structure 100. Such locations can be recorded in the verification map 132 Figure 1 ), for example, as discussed herein.

[0046] Figure 11 An illustrative flowchart showing various operations for verifying the IC structure 100 using the phosphor material 108 is shown. Some of the operations described herein can be preliminary and / or implemented by other parties and are therefore shown in dashed line in Figure 10 . Reference is made to Figure 1 and 10The process P0.1 includes, for example, forming the IC structure 100 with at least one region of the fluorescent material 108. The formation of the IC structure 100 can be achieved using any of the various examples discussed herein and / or other conceivable methods for forming the fluorescent material 108 within the IC structure 100. The method according to the present disclosure can further include, for example, the process P0.2 to create a verification map 132 for specifying locations in which the fluorescent material 108 is expected to occur in the IC structure 100. The verification map 132 can be provided as data to the computing device 130 and / or can be recorded in various other forms of storage media (possibly including formats that are capable of being inspected without the computing device 130).

[0047] Further processing according to the present disclosure can be implemented, for example, by a final recipient of the IC structure 100 after further manufacturing of the IC structure 100 and / or shipping the IC structure 100 to a destination. The process P1.1 according to the present disclosure can include, for example, detecting the fluorescent material 108 on the IC component 102 using a tool such as the radiation source 122 discussed herein. The fluorescent material 108 detected in the IC structure 100 can define an identification mark. The process P1.2 in embodiments of the present disclosure can then include, for example, comparing the identification mark with the verification map 132 in which the fluorescent material 108 is present. The comparison in the process P1.2 can be implemented manually, for example, via an operator of the radiation source 122 and / or automatically via the computing device 130 coupled to the radiation source 122 and / or a computer device 130 that otherwise receives input specifying the identified locations of the fluorescent material 108. Thereafter, the process P1.3 includes verifying whether the fluorescent material 108 in the IC structure 100 matches the locations listed in the verification map 132. In the event that the locations of the fluorescent material 108 match the verification map 132, the IC structure 100 is verified. Otherwise, the IC structure 100 can have been subjected to an unauthorized modification operation that removed the fluorescent material 108. The method can then end (“complete”) and the IC structure 100 can be used or discarded based on the results of the process P1.3.

[0048] Embodiments of the present disclosure provide several technical and commercial advantages, some of which are discussed herein as examples. As will be apparent from the discussion herein, embodiments of the present disclosure allow for the fabrication of IC structures 100 with built-in verification features, thereby allowing for optical verification of the IC structures 100 without specialized equipment. In some cases, only a source of radiation 122 is needed to verify that the IC structure 100 has not been modified without authorization. Embodiments of the present disclosure also allow for the fluorescent material 108 to be formed at various preselected locations within the IC structure 100, thereby hindering the ability of third parties to replicate and / or modify certain sensitive IC components 102. The fluorescent material 108 can or can not be present at thousands or millions of locations, thus making it impossible for a third party to form the fluorescent material 108 in the same locations or in subsequent IC products 100 without altering the fluorescent material 108. For example, if a third party and / or intermediate recipient receives the IC structure 100 prior to the IC structure 100 being provided to an end customer, altering the IC structure 100 will affect portions of the structure that include the fluorescent material 108. These portions, if removed, will also result in the fluorescent material 108 being removed from the IC structure 100. In this case, the remaining fluorescent material 108 of the IC structure 100 will not match the verification pattern 132 Figure 1 ) and the IC structure 100 will be rejected.

[0049] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0050] The above-described methods are used to fabricate integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricant as raw chips, i.e., as a single wafer having a plurality of unpackaged chips, as bare chips, or in packages. In the latter case the chips are mounted in single chip packages (e.g., plastic carriers, with leads that are affixed to a motherboard or other higher level carrier) or in multi-chip packages (e.g., ceramic carriers that have surfaces that interconnect and / or mask buried interconnections). In any case the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of the product being fabricated (for example a motherboard). As a final product the product being fabricated can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products, including servers, desktops, laptop computers, handheld devices, and other high-end products.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Optional" or "optionally" means that the subsequently described event or circumstance can or can not occur, and that the description includes instances where the event occurs and instances where it does not.

[0052] Approximating language can be used to modify any quantitative representation that can possibly vary, depending upon the precision with which it is used and / or it's related subject matter. For instance, by using the terms "about" and "substantially” it will be understood that the precision of a value need not be exactly as stated, but can allow for some variability. In at least some instances, the approximate language can correspond to the precision of an instrument for measuring the value. In the present disclosure and throughout the claims, range limitations can be combined and / or interchanged, such ranges are identified and include all the sub-ranges contained therein, unless context or language indicates otherwise. "Approximately” applied to a range of values applies to both values, and unless otherwise indicated, can indicate + / - 10% of the stated value, depending on the precision of the measuring instrument.

[0053] All means or step-plus-function elements in the claims that follow the designation of an element preceded by the phrase "means for" or "step for" are intended to encompass every possible means or step for performing the function performed by the element in which this phrase appears. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations will be apparent to those skilled in the art. Embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, and to thereby enable others skilled in the art to best utilize the disclosure with various modifications as are suited to the particular use contemplated.

Claims

1. An integrated circuit (IC) structure, comprising: a layer of fluorescent material on an IC component, wherein the layer of fluorescent material defines a portion of an identification mark for the IC structure, wherein the layer of fluorescent material is between an outer surface of a via and an insulator liner.

2. The IC structure of claim 1, wherein, the layer of fluorescent material comprises a liner within a metal layer.

3. The IC structure of claim 1, wherein, the layer of fluorescent material is on a refractory metal liner of the via.

4. The IC structure of claim 1, wherein, the layer of fluorescent material comprises a liner on a through-silicon via (TSV), the TSV being disconnected from circuitry within the IC structure.

5. The IC structure of claim 1, wherein, the IC component comprises a semiconductor substrate, and wherein the layer of fluorescent material is within a trench defined within a backside surface of the semiconductor substrate.

6. The IC structure of claim 1, wherein, the layer of fluorescent material comprises one of a plurality of layers of fluorescent material, the plurality of layers of fluorescent material defining the identification mark for the IC structure.

7. The IC structure of claim 1, wherein, the layer of fluorescent material comprises chemical vapor deposition (CVD) diamond.

8. A method of verifying an integrated circuit (IC) structure, the method comprising: detecting a layer of fluorescent material on an IC component, wherein the detected layer of fluorescent material defines a portion of an identification mark for the IC structure; and comparing the identification mark to a verification map for the IC structure to verify the IC structure.

9. The method of claim 8, wherein, detecting the layer of fluorescent material on the IC component comprises illuminating a portion of a metal layer.

10. The method of claim 8, wherein, detecting the layer of fluorescent material on the IC component comprises illuminating a liner on a via.

11. The method of claim 10, wherein, the illuminated liner is between a refractory metal liner of the via and an insulator liner of the via.

12. The method of claim 8, wherein, detecting the layer of fluorescent material on the IC component comprises illuminating a through-silicon via (TSV), the TSV being disconnected from circuitry within the IC structure.

13. The method of claim 8, wherein, detecting the layer of fluorescent material on the IC component comprises illuminating a backside surface of a semiconductor substrate.

14. The method of claim 8, wherein, detecting the layer of fluorescent material comprises detecting a plurality of layers of fluorescent material, the plurality of layers of fluorescent material defining the identification mark for the IC structure.

15. An integrated circuit (IC) structure, comprising: an IC component on a substrate, wherein the substrate comprises a backside surface having a first trench and a second trench therein; a layer of fluorescent material within the first trench of the backside surface of the substrate, wherein the layer of fluorescent material defines a portion of an identification mark for the IC structure; and a non-fluorescent material within the second trench of the backside surface of the substrate.

16. The IC structure of claim 15, wherein, the IC component comprises a metal layer, and wherein the layer of fluorescent material comprises a liner on an interlayer dielectric (ILD) of the metal layer.

17. The IC structure of claim 15, wherein, the IC component comprises a via, and wherein the layer of fluorescent material comprises an intermediate liner between a refractory metal liner of the via and an insulator liner of the via.

18. The IC structure of claim 15, wherein, the layer of fluorescent material comprises chemical vapor deposition (CVD) diamond.

Images