Recessed semiconductor device and associated systems and methods

Abstract

The present disclosure relates to recessed semiconductor devices and associated systems and methods. Disclosed herein are semiconductor devices having a plated structure at a recessed edge, semiconductor assemblies formed by the semiconductor devices, and associated systems and methods. In one embodiment, the semiconductor assembly includes a first semiconductor device and a second semiconductor device. The first semiconductor device may include an upper surface and a first dielectric layer above the upper surface, the second semiconductor device may include a lower surface and a second dielectric layer above the lower surface, and the first and second dielectric layers may be joined to couple the first and second semiconductor devices. The first and second dielectric layers may each include a plurality of inwardly extending recesses exposing a plurality of metal structures on the respective upper and lower surfaces, and the upper surface recesses and metal structures may correspond to the lower surface recesses and metal structures. The metal structures may be electrically coupled via the plated structures positioned in the recesses.

Description

Technical Field

[0001] The present technology relates generally to semiconductor devices, and more particularly, to semiconductor devices having recessed edges and plating structures in the recessed edges. Background Art

[0002] Packaged semiconductor dies including memory chips, microprocessor chips, and imager chips typically include a semiconductor die mounted on a substrate and encased in a protective covering. The semiconductor die may include functional features, such as memory cells, processor circuits, and imager devices, and bonding pads electrically connected to the functional features. The bonding pads may be electrically connected to terminals external to the protective covering to allow the semiconductor die to be connected to higher-level circuitry.

[0003] Market pressures continue to drive semiconductor manufacturers to reduce the size of die packages and / or assemblies to accommodate the space constraints of electronic devices, while also driving semiconductor manufacturers to increase the functional capacity of each assembly to meet operating parameters. A method for increasing the processing power of a semiconductor assembly without significantly increasing the surface area covered by the assembly (i.e., the "footprint" of the assembly) is to stack multiple semiconductor dies vertically up and down in a single assembly. The dies in such vertically stacked assemblies can be interconnected by electrically coupling the bonding pads of a separate die to the bonding pads of an adjacent die using through silicon vias (TSVs). Typically, these interconnects include pillars or bumps that increase the height of the vertical stack and limit the number of dies that can be included in the vertically stacked assembly. Summary of the invention

[0004] In one aspect, the present disclosure relates to a semiconductor assembly comprising: a first semiconductor device comprising: an upper surface comprising a plurality of first metal structures at a first lateral edge of the upper surface, and a first dielectric layer above the upper surface, the first dielectric layer comprising a plurality of first recesses extending inwardly from the first lateral edge, the plurality of first recesses at least partially exposing the first metal structures; a second semiconductor device mounted on the first semiconductor device, the second semiconductor device comprising: a lower surface comprising a plurality of second metal structures at a second lateral edge of the lower surface, wherein each second metal structure is aligned with a corresponding first metal structure of the first semiconductor device, and a second dielectric layer above the lower surface, the second dielectric layer comprising a plurality of second recesses extending inwardly from the second lateral edge, the plurality of second recesses at least partially exposing the second metal structures, wherein the second dielectric layer is bonded to the first dielectric layer of the first semiconductor device; and a plurality of plating structures positioned within the first and second recesses, wherein each plating structure electrically couples the first metal structure of the first semiconductor device to the corresponding second metal structure of the second semiconductor device.

[0005] In another aspect, the present disclosure relates to a semiconductor assembly comprising: a first semiconductor device comprising: an upper surface comprising a plurality of metal structures at a first lateral edge of the upper surface, and a first dielectric layer above the upper surface, the first dielectric layer comprising a plurality of recesses extending inwardly from the first lateral edge, the plurality of recesses at least partially exposing the metal structures; a second semiconductor device mounted on the first semiconductor device, the second semiconductor device comprising: a lower surface comprising a second dielectric layer, wherein the second dielectric layer is bonded to the first dielectric layer of the first semiconductor device, and a plurality of conductive protrusions at a second lateral edge of the lower surface, the plurality of conductive protrusions extending from the second dielectric layer, wherein each conductive protrusion is aligned with a corresponding metal structure of the first semiconductor device; and a plurality of plating structures positioned within the recesses, wherein each plating structure electrically couples the metal structure of the first semiconductor device to the conductive protrusion of the second semiconductor device.

[0006] In yet another aspect, the present disclosure relates to a method for manufacturing a semiconductor assembly, the method comprising: forming a plurality of recesses in a first dielectric layer on a first side of a first semiconductor device, wherein the semiconductor device includes a plurality of metal structures at a first lateral edge of the first side that are at least partially exposed by the recesses; coupling the first dielectric layer of the first semiconductor device to a second dielectric layer on a second side of a second semiconductor device, wherein the second side of the semiconductor device includes a plurality of conductive elements aligned with the metal structures and the recesses of the first semiconductor device; and plating a conductive material in the recesses so as to electrically couple the metal structures of the first semiconductor device to the conductive elements of the second semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Many aspects of the present invention may be better understood with reference to the accompanying drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on clearly illustrating the principles of the present invention.

[0008] Figure 1A is a side cross-sectional view of a semiconductor device configured in accordance with an embodiment of the present technology.

[0009] Figure 1B yes Figure 1A A top view of a semiconductor device.

[0010] Figure 1C is a side cross-sectional view of a semiconductor assembly at an initial stage of a manufacturing process in accordance with an embodiment of the present technology.

[0011] Figure 1D yes Figure 1CA side cross-sectional view of a semiconductor assembly at a later stage in the manufacturing process.

[0012] Figure 2A is a side cross-sectional view of a semiconductor device according to an embodiment of the present technology.

[0013] Figure 2B is a side cross-sectional view of another semiconductor device according to an embodiment of the present technology.

[0014] Figure 2C is a side cross-sectional view of a semiconductor assembly at an initial stage of a manufacturing process in accordance with an embodiment of the present technology.

[0015] Figure 2D yes Figure 2C A side cross-sectional view of a semiconductor assembly at a later stage in the manufacturing process.

[0016] Figure 2E is a side cross-sectional view of a lower device and an upper device according to an embodiment of the present technology.

[0017] Figures 3A to 3D are side cross-sectional views illustrating various stages of a process or method for fabricating a plurality of semiconductor devices in accordance with an embodiment of the present technology.

[0018] Figures 4A-4L are side cross-sectional views illustrating various stages of a process or method for fabricating a plurality of semiconductor devices in accordance with an embodiment of the present technology.

[0019] Figure 5 is a block diagram illustrating a method of fabricating a semiconductor assembly according to an embodiment of the present technology.

[0020] Figure 6 is a schematic diagram of a system including a semiconductor device or assembly configured in accordance with an embodiment of the present technology. DETAILED DESCRIPTION

[0021] Specific details of several embodiments of semiconductor devices and associated systems and methods are described below. In several embodiments described below, a semiconductor assembly configured according to the present technology may include a first semiconductor device. The first semiconductor device may have an upper surface, including a plurality of first metal structures at a first lateral edge of the upper surface. The metal structure may be a pad, a bonding pad, a contact, a layer, a region, a conductive element, etc. suitable for forming an electrical interconnection to another semiconductor device. The first semiconductor device may further include a first dielectric layer above the upper surface, the first dielectric layer including a plurality of first recesses extending inward from the first lateral edge and at least partially exposing the first metal structure. The semiconductor assembly may further include a second semiconductor device mounted on the first semiconductor device. The second semiconductor device may include a lower surface, including a plurality of second metal structures at a second lateral edge of the lower surface. Each of the second metal structures may be aligned (e.g., vertically aligned) with a corresponding first metal structure on the first semiconductor device. The second semiconductor device may further include a second dielectric layer above the lower surface, the second dielectric layer including a plurality of second recesses at least partially exposing the second metal structure. The second dielectric layer may be bonded to the first dielectric layer of the first semiconductor device.

[0022] The semiconductor assembly may further include a plurality of plating structures positioned within first and second recesses of the first and second semiconductor devices. Each plating structure may electrically couple a first metal structure of the first semiconductor device to a corresponding second metal structure of the second semiconductor device. In some embodiments, the plating structures are deposited in the first and second recesses using an electroless plating process. Thus, the first and second semiconductor devices may be stacked vertically to form the semiconductor assembly, and the plating structures that electrically couple the first and second devices may add a minimum (if any) height to the assembly. In addition, compared to conventional hybrid bonding techniques that typically require very tight planarization tolerances to form high-yield device interconnects, the recesses around the die described herein allow the plating structures to be formed after the die stack is formed, which can provide an increased process margin. The recesses described herein may also serve as guides for improving accuracy when aligning to adjacent semiconductor devices.

[0023] Those skilled in the relevant art will recognize that the appropriate stages of the methods described herein may be performed at the wafer level or at the die level. Thus, the term "substrate" may refer to a wafer-level substrate or a singulated die-level substrate, depending on the context in which it is used. Furthermore, unless the context indicates otherwise, the structures disclosed herein may be formed using semiconductor manufacturing techniques, the details of which are well known to those skilled in the art. For example, materials may be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials may be removed using, for example, plasma etching, wet etching, chemical mechanical planarization, or other suitable techniques.

[0024] Numerous specific details are disclosed herein to provide a thorough and useful description of embodiments of the present technology. However, those skilled in the art will appreciate that the technology may have additional embodiments and that the technology may be used without the following references. Figure 1A-6 The present invention is practiced without the use of several of the details of the described embodiments. For example, some details of semiconductor devices and / or assemblies well-known in the art have been omitted in order to obscure the present invention. In general, it should be understood that various other devices and systems besides those specific embodiments disclosed herein may be within the scope of the present invention.

[0025] As used herein, the terms "vertical," "lateral," "upper," "lower," "above," and "below" may refer to the relative direction or position of features in a semiconductor device in view of the orientation shown in the figure. For example, "upper" or "uppermost" may refer to a feature that is positioned closer to the top of the page than another feature. However, these terms should be broadly understood to include semiconductor devices having other orientations, such as inverted or tilted orientations, where top / bottom, above / below, over / below, up / down, and left / right may be interchanged depending on the orientation.

[0026] Figure 1A is a side cross-sectional view of a semiconductor device 100 ("device 100") configured in accordance with an embodiment of the present technology. Device 100 may include a semiconductor die 102 including a semiconductor substrate 104 (eg, a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.).

[0027] In the illustrated embodiment, the semiconductor substrate 104 (e.g., a silicon substrate, a gallium arsenide substrate, an organic laminate substrate, etc.) has a first side or surface 106a and a second side or surface 106b opposite the first side 106a. In some embodiments, the first side 106a may be at an upper side of the semiconductor substrate 104, and the second side 106b may be a lower side of the semiconductor substrate 104. The first and / or second sides 106a-b of the semiconductor substrate 104 may be active sides or regions including one or more circuit elements (e.g., wires, traces, interconnects, transistors, etc.) formed in and / or on the respective first and / or second sides 106a-b. The circuit elements may include, for example, memory circuits (e.g., dynamic random access memory (DRAM) or other types of memory circuits), controller circuits (e.g., DRAM controller circuits), logic circuits, and / or other circuits. In other embodiments, the semiconductor substrate 104 may be a "blank" substrate that does not include integrated circuit components and is formed of, for example, crystalline, semi-crystalline and / or ceramic substrate materials such as silicon, polysilicon, aluminum oxide (Al2O3), or the like. 2 O 3), sapphire and / or other suitable materials.

[0028] In the illustrated embodiment, the first side 106a of the semiconductor substrate 104 may be electrically connected to a plurality of first side metal structures 108a-b, and the second side 106b of the semiconductor substrate 104 may be electrically connected to a plurality of second side metal structures 108c-d (the first and second side metal structures 108a-d are collectively referred to as "metal structures 108"). Each of the metal structures 108 may be positioned at or near an edge (e.g., a lateral edge, periphery, outer perimeter, etc.) of the semiconductor die 102 and / or near a lateral surface 113 of the semiconductor die 102. The metal structures 108 may be configured to electrically couple the device 100 to another semiconductor device, as described in further detail below. The first side metal structures 108a-b may correspond to the second side metal structures 108c-d, such that each metal structure on the first side 106a may be aligned (e.g., vertically) with a metal structure on the second side 106b (e.g., 108a is aligned with 108c, 108b is aligned with 108d). Each of metal structures 108 may each have any suitable dimensions, such as a width and / or a diameter less than or equal to 5 μm, 2 μm, 1 μm, 500 nm, 200 nm, or 100 nm.

[0029] In the illustrated embodiment, the first side metal structures 108a-b may be electrically connected to the corresponding second side metal structures 108c-d through a plurality of connectors 110. The connectors 110 may be or include, for example, one or more through silicon vias (TSVs) extending through the semiconductor substrate 104 to electrically couple the first side metal structures 108a-b to the corresponding second side metal structures 108c-d. Figure 1A As shown in , connector 110 can be electrically coupled to metal structure 108 via routing elements 111 (e.g., redistribution layers (RDLs), metallization layers, traces, and / or other conductive elements). In some embodiments, connector 110 is located at an interior and / or central portion of semiconductor die 102, and routing elements 111 can transmit signals from connector 110 to metal structure 108 at or near a lateral surface 113 of semiconductor die 102.

[0030] In some embodiments, connector 110 and / or routing element 111 may be electrically coupled to one or more circuit elements (not shown) formed in and / or on first and / or second sides 106a-b of semiconductor substrate 104. Thus, connector 110 may transmit signals generated by one or more circuit elements to metal structure 108 through corresponding routing element 111. Metal structure 108, connector 110, and / or routing element 111 may be made of any suitable conductive material, such as copper, nickel, gold, silicon, tungsten, conductive epoxy, any other suitable material, and combinations thereof.

[0031] The semiconductor die 102 further includes a first insulating material 112a formed over at least a portion of the first side 106a of the semiconductor substrate 104, and a second insulating material 112b formed over at least a portion of the second side 106b of the semiconductor substrate 104 (collectively referred to as "insulating material 112"). The insulating material 112 may further be formed between the semiconductor substrate 104 and the plurality of metal structures 108 on the first and second sides 106a-b of the semiconductor substrate 104. In some embodiments, one or more lateral surfaces 113 of the semiconductor substrate 104 may be at least partially or completely covered by a lateral insulating material 116 (e.g., a passivation material).

[0032] The insulating material 112 and / or the lateral insulating material 116 may each include one or more layers of a suitable dielectric material (e.g., a passivation material, a polyimide material, and / or other material used to cover the surface of a semiconductor device). For example, the insulating material 112 may include silicon oxide, silicon nitride, polycrystalline silicon nitride, polycrystalline silicon oxide, tetraethyl orthosilicate (TEOS), etc. In some embodiments, the insulating material 112 and / or the lateral insulating material 116 may at least partially include a dielectric material having a dielectric constant that is smaller than that of silicon oxide (a "low-κ dielectric material"). Such low-κ dielectric materials may include fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, organic polymer dielectrics, silicon-based polymer dielectrics, etc. In some embodiments, the insulating material 112 may be a dielectric material suitable for direct dielectric bonding (e.g., oxide-oxide bonding, nitride-nitride bonding, etc.) to a dielectric material on another semiconductor device, as further described below.

[0033] In the illustrated embodiment, the insulating material 112 includes a plurality of recesses 114a-d (collectively referred to as "recesses 114") extending inwardly from edges (e.g., lateral edges, peripheries, outer perimeters, etc.) of the first and second sides 106a-b of the semiconductor substrate 104. The orientation and / or geometry of the recesses 114 may correspond to the orientation and / or geometry of the metal structures 108 so that each recess 114 may at least partially or completely expose one of the metal structures 108. As described in further detail below, the recesses 114 may provide space for forming a plating structure to connect the metal structure 108 to another device. The recesses 114 may have any suitable dimensions, such as a height H of at least 50 nm, 100 nm, 200 nm, 400 nm, 500 nm, 1 μm, 2 μm, or 5 μm; and / or a depth D of at least 1 μm, 5 μm, 10 μm, 20 μm, or 25 μm. In some embodiments, each of the recesses 114 extends inwardly an equal amount (eg, from respective edges of the first and second sides 106a - b ).

[0034] Figure 1B yes Figure 1A 1. A top view of the device 100 of FIG. 1. Each of the metal structures 108 may be spaced apart and / or electrically isolated from each other by non-recessed areas of the insulating material 112. In the illustrated embodiment, the metal structures 108 and recesses 114 are distributed along all four lateral sides of the device 100. In other embodiments, the metal structures 108 and / or recesses 114 may be distributed along one, two, or three lateral sides of the device 100. Each of the recesses 114 may have a width W of at least 1 μm, 5 μm, 10 μm, 20 μm, 25 μm, or any other suitable width. As best shown in FIG. 1, the metal structures 108 and recesses 114 may be spaced apart and / or electrically isolated from each other by non-recessed areas of the insulating material 112. In the illustrated embodiment, the metal structures 108 and recesses 114 are distributed along all four lateral sides of the device 100. In other embodiments, the metal structures 108 and / or recesses 114 may be distributed along one, two, or three lateral sides of the device 100. Each of the recesses 114 may have a width W of at least 1 μm, 5 μm, 10 μm, 20 μm, 25 μm, or any other suitable width. Figure 1B As seen in FIG. 1 , the recess 114 may have a square or rectangular shape and expose a correspondingly shaped portion 109 of the metal structure 108. In another embodiment, the recess 114 and / or the metal structure 108 may have a circular, triangular, pentagonal, hexagonal, or any other suitable shape. Figure 1A and 1B In some embodiments, the first and second sides 106a-b of the semiconductor substrate 104 (the second side 106b is Figure 1B The recesses 114 on the first side 104 and / or the second side 106a-b (eg, obscured in FIG. 1 ) may each have the same geometry (e.g., size and / or shape). In other embodiments, some or all of the recesses 114 on the first side and / or the second side 106a-b may have different geometries. Additionally, while the device 100 is depicted as having eight metal structures 108 and corresponding recesses 114 on each side 106a-b, in other embodiments, the device 100 may include fewer or more metal structures 108 and corresponding recesses 114. For example, the device 100 may include one, two, three, four, five, six, seven, nine, ten, or more metal structures 108 and corresponding recesses 114 arranged between the semiconductor substrate 104 and the insulating material 112.

[0035] Figure 1C 1 is a side cross-sectional view of a semiconductor assembly 150 ("assembly 150") at an initial stage in a manufacturing process according to an embodiment of the present technology. Assembly 150 includes a plurality of die stacks 152a-d (e.g., "first die stack 152a," "second die stack 152b," "third die stack 152c," and "fourth die stack 152d") coupled to an assembly substrate 154. In the illustrated embodiment, each of the die stacks 152a-d includes a respective plurality of vertically arranged semiconductor devices (e.g., first semiconductor device 100a, second semiconductor device 100b, third semiconductor device 100c, and fourth semiconductor device 100d, collectively referred to as "devices 100"). Figure 1C Each of the devices 100 in the assembly 150 may be connected to Figure 1A and 1BFor example, each of the devices 100 may include respective first and second sides 106a-b, metal structures 108, insulating material 112, and recesses 114, as previously described in conjunction with Figure 1A and 1B Described (reference numbers for these components are shown for only semiconductor devices 158a-b in the first die stack 152a for clarity).

[0036] For each of the die stacks 152a-d, the device 100 can be arranged vertically such that the insulating materials 112 on the surfaces of adjacent semiconductor devices 158a-d are in direct contact with each other. In the illustrated embodiment, for example, the first insulating material 112a on the first side 106a of the lower semiconductor device 158a ("lower device 158a") contacts the second insulating material 112b on the second side 106b of the upper semiconductor device 158b ("upper device 158b"), as illustrated by the dashed lines in the inset. The first insulating material 112a on the lower device 158a can be mechanically coupled (e.g., via a dielectric-to-dielectric bond) to the second insulating material 112b on the upper device 158a. Thus, the lower device and the upper device 158a-b can be mechanically coupled to each other via the bond between the first and second insulating materials 112a-b.

[0037] In some embodiments, the device 100 may be arranged such that the recesses 114 and / or metal structures 108 of adjacent dies are aligned with each other. Figure 1C As shown in , the recesses 114a and / or metal structures 108a on the first side 106a of the lower device 158a can be vertically aligned with the corresponding recesses 114c and / or metal structures 108c on the second side 106b of the upper device 158b. Each pair of aligned recesses 114a, 114c can form a gap 115 that separates the corresponding metal structures 108a, 108c of the lower device and the upper device 158a-b. The gap 115 can provide space for forming a plated structure that electrically couples the upper device and the lower device 158a-b, as further described below.

[0038] In addition, if Figure 1C, the lowermost device 100 in each die stack 152a-d can be mechanically and electrically coupled to the assembly substrate 154. In the illustrated embodiment, for example, the second side 106b and / or the second insulating material 112b of the lower device 158a can be mechanically coupled to the assembly substrate 154 (e.g., via an adhesion layer, a dielectric-dielectric bond to an insulating layer on the assembly substrate 154, etc.), and any metal structures 108 on the second side 106b can be electrically and / or mechanically coupled to the assembly substrate 154 (e.g., coupled to corresponding metal structures or other electrical contacts on the assembly substrate 154, Figure 1C 1 . The assembly substrate 154 may be any structure suitable for supporting the die stacks 152a-d, and may be or include a redistribution layer, an interposer, a printed circuit board, a dielectric spacer, another semiconductor die (eg, a logic die), or another suitable substrate.

[0039] Although the illustrated embodiment depicts the assembly 150 as having four die stacks 152a-d, with each stack including four devices 100, in other embodiments, the assembly 150 may include fewer or more die stacks (e.g., one, two, three, five, six, seven, eight, nine, ten, or more die stacks), and each die stack may include fewer or more devices 100 (e.g., one, two, three, five, six, seven, eight, nine, ten, or more devices).

[0040] Figure 1D yes Figure 1C 1 is a side cross-sectional view of an assembly 150 at a later stage in a manufacturing process. In the illustrated embodiment, the assembly 150 includes a plurality of plating structures 160 that electrically couple adjacent semiconductor devices 100 (e.g., devices 158a-b) to one another. Each plating structure 160 can be positioned in a respective gap 115 between corresponding alignment recesses 114a, 114c so as to bridge and / or electrically couple a corresponding metal structure 108a of a lower device 158a with a metal structure 108c of an upper device 158b. This configuration of recesses 114, gaps 115, and / or plating structures 160 can advantageously reduce the vertical spacing between individual devices 100. For example, because each plated structure 160 may be formed (eg, plated) within the alignment recesses 114a, 114c and / or gaps 115 formed when the lower device 158a is directly joined to the upper device 158b, the plated structures 160 do not contribute to the overall height of the two joined devices 158a-b.

[0041] The plating structures 160 may be made of any suitable conductive material, such as copper, nickel, gold, silicon, tungsten, conductive epoxy, any other suitable material, and combinations thereof. The plating structures 160 may be formed using any suitable technique, such as by depositing conductive material into corresponding recesses 114 and / or gaps 115 using an electroless plating process. The electroless plating process may deposit a continuous volume of conductive material on the metal structure 108 and in the recesses 114 and / or gaps 115 to form electrical connections with no or minimal voiding, gaps, gaps, etc. This may be advantageous for embodiments where the size of the metal structure 108, recesses 114, and / or gaps 115 is relatively small. Additionally, the electroless plating process may be performed at or near the end of the manufacturing process (e.g., after the die stacks 152a-d have been assembled) and multiple plating structures 160 may be formed in a single plating process. However, in other embodiments, the conductive material may be deposited using other techniques known to those skilled in the art, such as electroplating, chemical vapor deposition, physical vapor deposition, atomic layer deposition, and / or other suitable techniques.

[0042] In some embodiments, the process of forming the plated structures 160 may preferentially deposit the conductive material on the metal structures 108 and in the corresponding recesses 114 and / or gaps 115 rather than on the lateral surfaces 113 of the device 100. Any of the conductive materials deposited on the lateral surfaces 113 may be removed after the formation process is completed, for example, using etching or techniques known to those skilled in the art. Alternatively, the amount of conductive material deposited on the lateral surfaces 113 may be sufficiently small and / or electrically isolated from each other so that they do not interfere with the electrical coupling of the device 100 (e.g., do not electrically short adjacent plated structures 160). However, in other embodiments, the lateral surfaces 113 of the device 100 may be at least partially or completely covered with an insulating material (e.g., Figure 1A The lateral insulating material 116 is covered with the lateral surface 113 to at least reduce or prevent deposition of conductive material on the lateral surface 113. In such embodiments, the insulating material may be deposited on the lateral surface 113 using a lateral surface passivation process prior to forming the plating structure 160, as described in more detail below.

[0043] In some embodiments, the assembly 150 includes a plurality of channels 170a-c (collectively referred to as "channels 170") between the die stacks 152a-d so that each of the die stacks 152a-d is spaced apart from each other. For example, in the illustrated embodiment, the assembly 150 includes a first channel 170a between the first and second die stacks 152a-b, a second channel 170b between the second and third die stacks 152b-c, and a third channel 170c between the third and fourth die stacks 152c-d. The assembly 150 may optionally include one or more bridging structures 180 (shown in dashed lines) within each channel 170. The bridging structures 180 may be made of a conductive material (e.g., copper, nickel, gold, silicon, tungsten, conductive epoxy, any other suitable material, and combinations thereof) configured to electrically couple adjacent die stacks to each other. As Figure 1D As shown in , the bridge structure 180 can bridge the metal structures 108 of the lowermost devices 100 in adjacent die stacks (eg, 152a - b , 152b - c , and / or 152c - d ) so that the die stacks can be directly connected to each other.

[0044] The bridge structure 180 may be formed before, during, or after the formation of the plating structure 160. In some embodiments, the bridge structure 180 is formed using the same or similar techniques as the techniques for forming the plating structure 160, such as via an electroless plating process. In such embodiments, the channel 170 may have a size small enough to allow the bridge structure 180 to be formed between the die stacks. For example, the channel 170 may have a width W of no greater than 500 μm, 400 μm, 300 μm, 250 μm, 200 μm, 150 μm, 100 μm, 50 μm, 20 μm, or 10 μm. Optionally, a portion of the assembly substrate 154 near the channel 170 may include grooves, cutouts, etc. (not shown) formed therein to provide additional surface area for depositing the material forming the bridge structure 180. However, in other embodiments, the bridge structure 180 is omitted, and the die stacks may instead be connected to each other via the assembly substrate 154.

[0045] In some embodiments, after forming the plating structure 160, the assembly 150 can be incorporated into a semiconductor package. For example, the assembly substrate 154 can be coupled to conductive elements (e.g., solder balls, conductive bumps, conductive pillars, conductive epoxy, and / or other suitable conductive elements, not shown) configured to electrically couple the assembly 150 to an external device. In addition, the assembly 150 can be encapsulated in a molding material such as a resin, epoxy, silicone-based material, polyimide, or any other material suitable for protecting the various components of the assembly 150 from contamination and / or physical damage.

[0046] Figure 2A and2B are respective cross-sectional views of semiconductor devices 200 , 220 according to embodiments of the present technology. Figure 2A and 2B The components of the semiconductor devices 200 and 220 may be substantially similar to Figure 1A and 1B Therefore, similar or identical components are identified using similar reference numerals (e.g., semiconductor substrate 104 and semiconductor substrates 204, 224), and Figure 2A and 2B The discussion of the semiconductor devices 200, 220 is generally limited to different Figure 1A and 1B Those features of the device 100 of , and other similar features necessary for the context. In addition, Figure 2A and 2B Any of the features of the semiconductor devices 200, 220 may be compared with each other and / or with Figure 1A and 1B The device 100 is combined.

[0047] First reference Figure 2A , a semiconductor device 200 ("device 200") includes a plurality of recesses 214a-b (collectively referred to as "recesses 214") in a first insulating material 212a on a first side or surface 206a (eg, upper side) of a semiconductor substrate 204. The recesses 214 may be Figure 1A and 1B The recesses 114 in the embodiment of the present invention may be the same or substantially similar (e.g., with respect to height, depth, shape, etc.). The orientation and / or geometry of the recesses 114 may correspond to the orientation and / or geometry of the plurality of metal structures 208a-b (collectively referred to as “metal structures 208”) such that each recess 114 may at least partially or completely expose the metal structure 208.

[0048] The apparatus 200 also includes a plurality of conductive protrusions 218a-b (collectively referred to as "protrusions 218") extending from a second side or surface 206b (e.g., the bottom side) of the semiconductor substrate 204 and / or a second insulating material 212b thereon. Each of the protrusions 218 may be located at or near an edge and / or a lateral surface 213 of the apparatus 200. Each protrusion 218 may be or include a conductive element suitable for forming an electrical interconnection to another semiconductor device such that each protrusion 218 may be coupled to a corresponding one of the metal structures 208c-d on the second side 206b of the semiconductor substrate 204. For example, in the illustrated embodiment, protrusion 218a is electrically coupled to metal structure 208c and protrusion 218b is electrically coupled to metal structure 208d. Each of the plurality of protrusions 218a-b may include a conductive region 219a and an insulating region 219b. The conductive region 219a may be electrically coupled to the metal structures 208c-d on the second side 206b of the semiconductor substrate. The insulating region 219b may be coupled to the second insulating material 212b. In other embodiments, the plurality of protrusions 218a-b may include only the conductive region 219a.

[0049] The orientation and / or geometry of the protrusions 218 may correspond to the orientation and / or geometry of the recesses 214, e.g., to facilitate alignment during die stacking as further described below with reference to Figure 2C In some embodiments, the recesses 214 have a shape complementary to the corresponding protrusions 218. For example, the recesses 214 may have a shape similar to that of the recesses 114 of Figure 1A-1B (e.g., square, rectangular, circular, triangular, pentagonal, hexagonal, or any other suitable shape), and the protrusions 218 may have a corresponding shape such that the protrusions 218 may fit at least partially within the recesses 214 of another semiconductor device, as described in detail below.

[0050] The recesses 214 may have a height and / or depth (e.g., height H and depth D) selected as previously discussed for the recesses 114 of Figure 1A and 1B or any other suitable height and / or depth. The protrusions 218 may have dimensions similar to those of the recesses 214. For example, the protrusions 218 may have a height H of at least 50 nm, 100 nm, 200 nm, 400 nm, 500 nm, 1 μm, 2 μm, or 5 μm P ; and / or a length L of at least 1 μm, 5 μm, 10 μm, 20 μm, or 25 μm. In some embodiments, the dimensions of the protrusions 218 may be sufficiently smaller than the dimensions of the recesses 214 (e.g., L < D; and / or H P < H) such that the protrusions 218 may fit at least partially within the corresponding recesses 214 of another semiconductor device.

[0051] Next reference Figure 2B , the semiconductor device 220 ("device 220") may be substantially similar to Figure 2A The device 200 of FIG. 220 is different in that the recess 234 and the protrusion 238 of the device 220 include inclined (eg, beveled) surfaces. Figure 2B As shown in FIG. 1 , the device 220 includes a plurality of recesses 234a-b in a first insulating material 232a on a first side 226a (e.g., an upper side) of a semiconductor substrate 224 and exposing a plurality of metal structures 228a-b. The device 220 also includes a plurality of conductive protrusions 238a-b (collectively referred to as "protrusions 238") extending from a second side 226b of the semiconductor substrate 224 and electrically coupled to respective metal structures 228c-d. Each of the protrusions 238 may include a first conductive protrusion 238a-b and a second conductive protrusion 238b. Figure 2A Conductive region 239a similar or substantially identical to conductive region 219a of Figure 2A The recesses 234a-b may have a similar structure to the insulating region 219b. Figure 1A and 1B The protrusions 238a-b may have dimensions similar to the dimensions of the recesses 234a-b, so the protrusions 238a-b may at least partially fit within corresponding recesses 234a-b of another semiconductor device.

[0052] In the illustrated embodiment, the first insulating material 232a further includes a first bevel 240 at an edge of the first insulating material 232a that surrounds (e.g., abuts, adjoins, is adjacent to) the recessed portions 234a-b. Additionally, the device 220 may include a metal structure bevel 244 aligned below and corresponding to the first bevel 240. The metal structure bevel 244 may be part of the metal structure 228, or may be electrically and / or mechanically coupled to the metal structure 228. The insulating region 239b and / or the second insulating material layer 232b may further include a second bevel 242 that corresponds to the first bevel 240 in the first insulating material 232a. The orientation and / or geometry of the second bevel 242 may correspond to the orientation and / or geometry of the first bevel 240, for example to facilitate reference to the metal structure 228 as described below. Figure 2CAlignment during the formation of the die stack further described. The first bevel 240, the second bevel 242 and the metal structure bevel 244 may have any suitable geometric shape. For example, the first bevel 240 may have an angle A, the metal structure bevel 244 may have an angle B, and the second bevel 242 may have an angle C. Angles A, B and C may each be at least 10°, 20°, 30°, 40°, 50°, 60°, 70°, 80°, 90°, or any other suitable angle. In some embodiments, angles A, B and C may each be the same angle, or some or all of angles A, B and C may be different angles. In addition, the first bevel 240, the second bevel 242 and / or the metal structure bevel 244 may be chamfered, tapered, concave, convex or any other suitable shape.

[0053] Figure 2C and 2D is a side cross-sectional view of a semiconductor assembly 250 (“assembly 250 ”) at various stages of a fabrication process in accordance with an embodiment of the present technology. Figure 2A and 2D The components of the assembly may be substantially similar to Figure 1C and 1D Therefore, similar or identical components are identified using similar reference numerals (e.g., assembly 150 and assembly 250), and Figure 2C and 2D The discussion of the assembly 250 will be limited to different Figure 1C and 1D Those features of the assembly 150, and other similar features as the context requires. In addition, Figure 2C and 2D Any of the features of assembly 250 may be combined with each other and / or with Figure 1C and 1D The assembly 150 is combined.

[0054] First reference Figure 2C , at an initial stage in the manufacturing process, assembly 250 includes a plurality of semiconductor die stacks 252a-d, and each of die stacks 252a-d may include a corresponding plurality of semiconductor devices 200a-d (collectively referred to as "devices 200"). Although devices 200a-d are depicted as Figure 2A The device 200 of FIG. 1 is the same as or similar to the device 200 of FIG. 1 , but in other embodiments, the devices 200a-d may be the same as or similar to the device 200a-d of FIG. Figure 2B Optionally, at least one of the die stacks 252a-d may include a device 220 that is the same as or similar to the device 220. Figure 2A The device 200 is the same as or similar to the device 200, and at least a second die stack in the die stacks 252a-d may include a device similar to the device 200. Figure 2B The device 220 is the same as or similar to the device.

[0055] Each of the devices 200 may include a plurality of metal structures 208, a plurality of recesses 214, and a plurality of conductive protrusions 218 (for clarity, only reference numbers for devices 258a-b of die stack 252a are shown). The devices 200 may be arranged so that the recesses 214 and protrusions 218 of adjacent dies are aligned with each other. For example, Figure 2C , the recess 214a and / or the metal structure 208a of the lower device 258a can be vertically aligned with the corresponding protrusion 218a of the upper device 258b. In some embodiments, the protrusion 218a can occupy at least a portion of the corresponding recess 214a so that the metal structure 208a remains at least partially exposed. However, in other embodiments, the protrusion 218a can completely fill the corresponding recess 214a and / or directly contact the metal structure 208a. The complementary orientation and / or geometry of the recess 214 and the protrusion 218 can facilitate the alignment of adjacent (e.g., vertically aligned) devices 200. For example, the protrusion 218 of the upper device 258b can at least partially fit within the recess 214 of the lower device 258a so that the upper device 258b can be at least partially mechanically coupled to the lower device 258a.

[0056] Reference again Figure 2C , the lowermost device 200 in each die stack 252a-d can be mechanically and electrically coupled to the assembly substrate 254. In the illustrated embodiment, for example, the second side 206b and / or second insulating material 212b of the lower device 258a can be mechanically coupled to the assembly substrate 254 (e.g., via an adhesive layer, dielectric-dielectric bonding to an insulating layer on the assembly substrate 254, etc.), and any metal structures 208 and / or protrusions 218 on the second side 206b can be electrically and / or mechanically coupled to the assembly substrate 254 (e.g., to corresponding metal structures or other electrical contacts on the assembly substrate 254, Figure 2C not shown).

[0057] Next reference Figure 2D At a later stage of the manufacturing process, the assembly 250 includes a plurality of plated structures 260, which may be substantially similar to Figure 1DThe plating structures 260 may electrically couple adjacent semiconductor devices 200 to each other. Each plating structure 260 may be positioned between corresponding recesses 214a and protrusions 218a of the lower and upper devices 258a-b so as to bridge and / or electrically couple the metal structure 208a of the lower device 258a to the corresponding protrusion 218a of the upper device 258b. The plating structures 260 may be made of any suitable conductive material, such as copper, nickel, gold, silicon, tungsten, conductive epoxy, any other suitable material, and combinations thereof. The plating structures 260 may be formed using techniques that are the same or substantially similar to those previously described with respect to FIGS. 1C and 1D and the plating structures 160.

[0058] In some embodiments, the assembly 250 may further include a plurality of channels 270a-c between the die stacks 252a-d to space each of the die stacks 252a-d apart from each other. The channels 270a-c may be spaced apart from each other. Figure 1D The channels 170a-c are the same or substantially similar. The assembly 250 may optionally include one or more bridging structures 280 (shown in phantom) within each channel 270. The bridging structures 280 may be connected to Figure 1D The bridging structures 180 are the same or substantially similar.

[0059] Although Figure 2C and 2D The assembly 250 described in the embodiment includes a Figure 2A In another embodiment, the assembly 250 may include a protrusion 218 configured according to Figure 2B For example, the conductive protrusions are configured in accordance with an embodiment of the present invention. Figure 2E As shown in FIG. 1 , the lower device 258a has a recess 234a including a first slope 240, and the upper device 258b has a protrusion 238a including a second slope 242. The first slope 240 of the lower device 258a can be vertically aligned with the second slope 242 of the upper device. Figure 2B As discussed, the first bevel 240 and the second bevel 242 may have the same angle. The complementary orientation and / or geometry of the first and second bevels 240, 242 facilitates alignment of the devices 258a-b. For example, the angled surfaces of the first and second bevels 240, 242 may guide (e.g., lead, direct, etc.) the partially aligned protrusions 238a toward the corresponding recesses 234a. This may advantageously facilitate die stack alignment during the manufacturing process. Subsequently, a plating structure (not shown) may be formed in the recesses 234a to electrically couple the metal structures 228a, 228c of the devices 258a-b, as previously described with respect to Figure 2D In other embodiments, the assembly 250 may include Figure 2A and 2BThe present invention also provides a combination of conductive protrusions and may further include conductive protrusions having any other suitable configuration.

[0060] Figures 3A to 3D 1 is a side cross-sectional view illustrating various stages of a process or method for manufacturing a plurality of semiconductor devices according to an embodiment of the present technology. The method can be used to manufacture the semiconductor devices described herein (e.g., Figure 1A and 1B The device 100, Figure 2A The device 200 and Figure 2B Any embodiment of the device 220) and / or one or more components thereof. Although Figures 3A-3D The fabrication method is described for five semiconductor devices, but in practice, the method may be scaled or otherwise adapted for any suitable number of semiconductor devices (eg, a single semiconductor device, tens or hundreds of semiconductor devices, etc.).

[0061] First reference Figure 3A , the method includes forming a plurality of connectors 310 on and / or at least partially through a first side 306a of a semiconductor substrate 304. The connectors 310 may be or include, for example, one or more through silicon vias (TSVs) extending at least partially through the semiconductor substrate 304. The method may further include forming a plurality of metal structures 308a on the first side 306a of the semiconductor substrate 304. The metal structures 308 may be electrically coupled to the connectors 310 via routing elements 311 (e.g., RDLs, metallization layers, traces, and / or other conductive elements). The method may further include forming a first insulating material 312a on and / or at least partially over the metal structures 308a according to semiconductor manufacturing techniques known to those skilled in the art. The method may also include forming a first plurality of recesses 314a in the first insulating material 312a to partially or completely expose the metal structures 308a. For example, the first insulating material 312a may be deposited over part or all of the metal structure 308a, and then the recess 314 may be formed by selectively removing some or all of the first insulating material 312a over the metal structure 308a, for example, using etching or other suitable material removal techniques. Alternatively, the first insulating material 312a may be selectively deposited at a location on the first side 306a away from the metal structure 308a so that the metal structure 308a remains exposed. The first insulating material 312a may be any suitable insulating material, including those insulating materials discussed herein (e.g., Figure 1A and 1B The insulating material 112a-b) may be formed using techniques known to those skilled in the art, such as a chemical vapor deposition (CVD) process.

[0062] Next reference Figure 3B , the method further includes bonding the first side 306a of the semiconductor substrate 304 and the first insulating material 312a to a first carrier substrate 382 using an adhesive 380. The adhesive 380 can be any suitable adhesive material known to those skilled in the art. The first carrier substrate 382 can be a wafer or other structure made of silicon, glass, ceramic, or any other suitable material.

[0063] Next reference Figure 3C , the method further includes thinning the second side 306b of the semiconductor substrate 304. Thinning the second side 306b of the semiconductor substrate 304 can be achieved using techniques known to those skilled in the art, such as a chemical mechanical planarization (CMP) process. After thinning, the method can then include forming a plurality of second metal structures 308b, a plurality of routing elements 311, a second insulating material 312b, and a second plurality of recesses 314b on the second side 306b. The connector 310 can electrically couple the routing elements 311 and the plurality of second metal structures 308b. The routing elements 311 and / or the plurality of second metal structures 308b can be formed of the same and / or different conductive materials and can be formed using techniques known to those skilled in the art. The second insulating material 312b can be any suitable insulating material, including those insulating materials discussed herein (e.g., Figure 1A and 1B The insulating material 112a-b) may be formed using techniques known to those skilled in the art, such as a chemical vapor deposition (CVD) process.

[0064] Next reference Figure 3D The method further includes coupling the second side 306b of the semiconductor substrate 304 and the second insulating material 312b to the second carrier substrate 384, and coupling the first side 306a of the semiconductor substrate 304 and the first insulating material 312a to the second carrier substrate 384. Figure 3C The first carrier substrate 382 is separated from the first side 306a and the first insulating material 312a by, for example, dissolving, peeling off, or otherwise decoupling the adhesive 380 using a suitable stimulus (e.g., heat, light) or reagent (e.g., solvent, water). In some embodiments, the second carrier substrate 384 can be a dicing tape mounted on a film frame 386. The semiconductor substrate 304 can then be diced to form a plurality of singulated semiconductor devices (not shown).

[0065] Figures 4A-4L 1 is a side cross-sectional view illustrating various stages of a process or method for manufacturing a plurality of semiconductor devices according to an embodiment of the present technology. The method can be used to apply a passivation material to a semiconductor device (e.g., Figure 1A The device 100, Figure 2AThe device 200 and / or Figure 2B The lateral surface of the device 220). In manufacturing the semiconductor device described herein (e.g., Figure 1A and 1B The device 100, Figure 2A The device 200 and / or Figure 2B The method is used during any embodiment of the device 220) and / or one or more components thereof. Optionally, Figures 4A-4L Some or all of the method steps may be Figures 3A-3D Some or all of the steps of the method are combined.

[0066] First reference Figure 4A , the method includes forming a plurality of trenches 401 in a first side 406a of a semiconductor substrate 404. The semiconductor substrate 404 may include functional elements as previously described, such as circuit elements, connectors (e.g., vias), etc. (omitted for clarity). The trenches 401 may be formed in the semiconductor substrate 404 according to techniques known to those skilled in the art. For example, the trenches 401 may be formed by depositing a photoresist 402 on the first side 406a, selectively removing portions of the photoresist 402 that are above the desired locations of the trenches 401, and then selectively removing portions of the semiconductor substrate 404 that are not covered by the photoresist 402 (e.g., using dry etching) to form the trenches 401. The photoresist 402 may be removed after the trenches 401 are formed.

[0067] Next reference Figure 4B , the method further includes forming a first insulating material 412a on the first side 406a and in the trench 401 of the semiconductor substrate 404. The first insulating material 412a can be any insulating material as previously discussed and can be deposited using any suitable technique known to those skilled in the art. For example, the first insulating material 412a can be a nitride or oxide material and can be deposited using a chemical vapor deposition (CVD) process.

[0068] Next reference Figure 4C , the method further includes selectively removing portions of the first insulating material 412a that are on horizontal surfaces of the semiconductor substrate 404 (e.g., the first side 406a and / or the bottom surface 403 of the trench 401), while retaining portions of the first insulating material 412a that are on the vertical surface 405 of the trench 401. This can be achieved using any suitable technique known to those skilled in the art, such as by dry etching.

[0069] Next reference Figure 4D (relative to Figures 4A-4CThe method further includes depositing an adhesive 480 to at least partially cover the first side 406a of the semiconductor substrate 404 and at least partially or completely fill the trench 401. The adhesive 480 may be a thermosetting adhesive (e.g., a thermosetting adhesive manufactured by Nissan Chemical), or any other suitable adhesive. The adhesive 480 may be deposited using any suitable technique known to those skilled in the art, such as spin coating, dip coating, spray coating, etc.

[0070] Next reference Figure 4E , the method further includes bonding the semiconductor substrate 404 to a carrier substrate 482 using an adhesive 480. The carrier substrate 482 may be a wafer or other structure made of silicon, glass, ceramic, or any other suitable material.

[0071] Next reference Figure 4F , the method further includes removing at least a portion of the semiconductor substrate 404 from the second side 406 b of the semiconductor substrate 404. The portion of the semiconductor substrate 404 may be removed using, for example, a CMP process or any suitable technique known to one skilled in the art. In some embodiments, the amount of semiconductor substrate 404 removed may be small enough so that the first insulating material 412 a and the adhesive 480 are not exposed and remain covered by a portion of the semiconductor substrate 404. However, in other embodiments, the amount of semiconductor substrate 404 removed may be large enough so that at least some of the first insulating material 412 a and the adhesive 480 are exposed at the second side 406 b of the semiconductor substrate 404.

[0072] Next reference Figure 4G The method further includes selectively removing an additional portion of the second side 406b of the semiconductor substrate 404 to expose a second side 406b of the semiconductor substrate 404 ( Figure 4G 406b). The semiconductor substrate 404 may be formed by a plurality of discrete dies 400a-g (collectively, “dies 400”) in the semiconductor substrate 404. ...

[0073] Next reference Figure 4H, the method further includes depositing a second insulating material 412b on the second side 406b of the die 400 to at least partially cover the die 400, the first insulating material 412a, and / or the adhesive 480 between the die 400. The second insulating material 412b can be the same as or different from the first insulating material 412a, and can be any suitable insulating material, including the materials discussed previously (e.g., oxide or nitride materials). The second insulating material 412b can be deposited using any suitable technique known to those skilled in the art.

[0074] Next reference Fig. 4I , the method further includes removing a portion of the second insulating material 412b to expose a via (not shown) on the second side 406b of the die 400. In the illustrated embodiment, this further includes removing a portion of the second insulating material 412b positioned over the adhesive 480 to at least partially expose the adhesive 480 between the individual dies 400. The portion of the second insulating material 412b may be removed using any suitable technique known to those skilled in the art, such as an oxide CMP process.

[0075] Next reference Figure 4J The method further includes removing at least a portion of the adhesive 480 from between the dies 400 so that the upper surface of the adhesive 480 is recessed from the upper surface of the second insulating material 412b. This may involve using a cleaning process based on the chemical properties of the adhesive 480, or any suitable process or technique known to those skilled in the art.

[0076] Next reference Figure 4K , the method further includes separating the die 400 from the adhesive 480 and the carrier substrate 482, and mounting the second insulating material 412b on the die 400 on the second carrier substrate 486 (e.g., a dicing tape or film is mounted in a frame. The adhesive 480 and the carrier substrate 482 may be removed using any suitable technique known to those skilled in the art. In the illustrated embodiment, the portion of the adhesive 480 between the die 400 may remain after the die 400 has been mounted on the second carrier substrate 486. In other embodiments, the adhesive 480 may be completely removed from between the die 400 when the die 400 is mounted to the second carrier substrate 486.

[0077] Next reference Figure 4L The method further includes removing any remaining adhesive 480 (not shown) from between the die 400. This can be done using the same method as previously described with respect to Figure 4JThe die 400 may be implemented by the same process as discussed above, or any suitable process or technique known to those skilled in the art. In the illustrated embodiment, the die 400 may have a lateral surface 413 at least partially covered by a first insulating material 412a (e.g., a lateral surface passivation material). In some embodiments, the die 400 may be separated from the second carrier substrate 486 and used in the manufacture of semiconductor devices (e.g., respectively) according to embodiments of the present technology. Figure 1A-1B , 2A and 2B devices 100, 200 and / or 220) are used.

[0078] Figure 5 5 is a block diagram illustrating a method 500 for manufacturing a semiconductor assembly according to an embodiment of the present technology. The method 500 may be used to manufacture the semiconductor assemblies described herein (eg, Figure 1C-1D The assembly 150, Figure 2C-2D Any embodiment of the assembly 250) and / or one or more components thereof.

[0079] At block 510, method 500 may include forming a plurality of recesses in a first dielectric layer on a first side or surface of a first semiconductor device. The recesses may expose (e.g., as previously described with respect to Figure 1A , 2A 2B) at an edge (e.g., periphery, outer periphery, etc.) of a first side of a first semiconductor device. In some embodiments, the plurality of metal structures are a plurality of first metal structures. For example, the above reference Figures 3A-3D The described process forms a recess.

[0080] At block 520, the method 500 may further include coupling the first dielectric layer of the first semiconductor device to a second dielectric layer on a second side or surface of the second semiconductor device. In some embodiments, the first semiconductor device may be an upper device, the first side may be a lower side, the second semiconductor device may be a lower device, and the second side may be an upper side. The second side of the semiconductor device may include a plurality of conductive elements (e.g., as previously described with respect to the embodiment of the present invention) that may be aligned (e.g., vertically aligned) with the metal structure and recess of the first semiconductor device. Figure 1C-1D and Figure 2C-2D In some embodiments, the plurality of conductive elements include a plurality of second metal structures, and the second dielectric layer includes a plurality of recesses that at least partially expose the plurality of second metal structures (e.g., as previously described with respect to Figure 1A In other embodiments, the plurality of conductive elements include a plurality of conductive protrusions extending from the second dielectric layer (e.g., as previously described with respect to Figure 2A and 2B In such embodiments, coupling the first and second dielectric layers may include inserting a plurality of conductive protrusions of the second semiconductor device into a corresponding plurality of recesses of the first semiconductor device.

[0081] At block 530, method 500 may further include depositing a conductive material in the recess to electrically couple the metal structure of the first semiconductor device to the conductive element of the second semiconductor device (eg, as previously described with respect to Figure 1C , 1D , 2C, and 2D). As discussed above, the conductive material may form an interconnect structure that electrically couples the first and second semiconductor devices to each other.

[0082] With above reference Figure 1A-5 Any of the semiconductor devices and / or assemblies of the described features may be incorporated into any of a number of larger and / or more complex systems, a representative example of which is Figure 6 Schematically shown in the system 600. The system 600 may include a processor 602, a memory 604 (eg, SRAM, DRAM, flash and / or other memory devices), an input / output device 606 and / or other subsystems or components 608. Figure 1A-5 The semiconductor devices and / or assemblies described may be included in Figure 6 In any one of the elements shown in . The resulting system 600 can be configured to perform any of a variety of appropriate calculations, processing, storage, sensing, imaging and / or other functions. Accordingly, representative examples of system 600 include but are not limited to computers and / or other data processors, such as desktop computers, portable computers, network appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multi-processor systems, processor-based or programmable consumer electronic devices, network computers and microcomputers. Additional representative examples of system 600 include lights, cameras, vehicles, etc. With respect to these and other examples, system 600 can be housed in a single unit or distributed over multiple interconnected units, such as through a communication network. Accordingly, the components of system 600 can include any one of local and / or remote memory storage devices and a variety of suitable computer-readable media.

[0083] It will be appreciated from the foregoing that specific embodiments of the present invention have been described herein for purposes of illustration, but that various modifications may be made without departing from the spirit and scope of the present invention. Accordingly, the present invention is not limited except as defined by the appended claims.

Claims

1. A semiconductor assembly comprising: A first semiconductor device comprising: an upper surface comprising a plurality of first metal structures at a first lateral edge of the upper surface, and a first dielectric layer above the upper surface, the first dielectric layer comprising a plurality of first recesses extending inwardly from the first lateral edge, the plurality of first recesses at least partially exposing the first metal structure; a second semiconductor device mounted on the first semiconductor device, the second semiconductor device comprising: a lower surface comprising a plurality of second metal structures at a second lateral edge of the lower surface, wherein each second metal structure is aligned with a corresponding first metal structure of the first semiconductor device, and a second dielectric layer over the lower surface, the second dielectric layer comprising a plurality of second recesses extending inwardly from the second lateral edge, the plurality of second recesses at least partially exposing the second metal structure, wherein the second dielectric layer is bonded to the first dielectric layer of the first semiconductor device; and A plurality of plated structures are positioned within the first and second recesses, wherein each plated structure electrically couples a first metal structure of the first semiconductor device to a corresponding second metal structure of the second semiconductor device.

2. The semiconductor assembly according to claim 1, wherein: Each first recess and the corresponding second recess together form a gap, The corresponding first metal structure and the corresponding second metal structure respectively exposed by the first and second recesses are spaced apart from each other by the gap, and A corresponding plated structure electrically coupling the first and second metal structures bridges the gap.

3. The semiconductor assembly of claim 1, further comprising a passivation material over one or more lateral surfaces of the first and second semiconductor devices. 4 . The semiconductor assembly of claim 1 , wherein the exposed portion of each of the first and second metal structures has a rectangular shape. 5 . The semiconductor assembly of claim 1 , wherein the plurality of first and second recesses each have a height in the range from 200 nm to 2 μm and a depth less than or equal to 25 μm. The semiconductor assembly of claim 1 , wherein each plated structure comprises copper.

7. The semiconductor assembly of claim 1, wherein each plated structure does not extend beyond the first and second lateral edges. The semiconductor assembly of claim 1 , wherein the first recess and the second recess extend inwardly by the same amount.

9. The semiconductor assembly of claim 1, wherein the first and second dielectric layers each comprise at least one of silicon oxide, silicon nitride, polysilicon nitride, polysilicon oxide, and tetraethyl orthosilicate (TEOS).

10. A semiconductor assembly comprising: A first semiconductor device comprising: an upper surface comprising a plurality of metal structures at a first lateral edge of the upper surface, and a first dielectric layer over the upper surface, the first dielectric layer comprising a plurality of recesses extending inwardly from the first lateral edge, the plurality of recesses at least partially exposing the metal structure; A second semiconductor device mounted on the first semiconductor device, the second semiconductor device comprising: comprising a lower surface of a second dielectric layer, wherein the second dielectric layer is bonded to the first dielectric layer of the first semiconductor device, and a plurality of conductive protrusions at a second lateral edge of the lower surface, the plurality of conductive protrusions extending from the second dielectric layer, wherein each conductive protrusion is aligned with a corresponding metal structure of the first semiconductor device; and A plurality of plated structures are positioned within the recess, wherein each plated structure electrically couples the metal structure of the first semiconductor device to the conductive protrusion of the second semiconductor device. The semiconductor assembly according to claim 10 , wherein the first dielectric layer comprises a plurality of first inclined surfaces, each of the first inclined surfaces being close to a corresponding recess. 12 . The semiconductor assembly of claim 11 , wherein each metal structure comprises a metal structure slope aligned with a corresponding first slope in the first dielectric layer. 13 . The semiconductor assembly according to claim 11 , wherein the second dielectric layer comprises a plurality of second inclined surfaces, each second inclined surface being close to a corresponding conductive protrusion.

14. The semiconductor assembly of claim 13, wherein: Each first inclined surface is vertically aligned with the corresponding second inclined surface, and Each first bevel is configured to receive a corresponding second bevel.

15. The semiconductor assembly of claim 10, wherein each recess is configured to receive a corresponding conductive protrusion.

16. The semiconductor assembly of claim 15, wherein each recess has a shape complementary to the corresponding conductive protrusion. 17 . The semiconductor assembly of claim 10 , wherein each of the plurality of conductive protrusions comprises a first portion formed of a first conductive material and a second portion formed of the second dielectric layer.

18. A method for manufacturing a semiconductor assembly, the method comprising: forming a plurality of recesses in a first dielectric layer on a first side of a first semiconductor device, wherein the semiconductor device includes a plurality of metal structures at a first lateral edge of the first side that are at least partially exposed by the recesses; coupling the first dielectric layer of the first semiconductor device to a second dielectric layer on a second side of a second semiconductor device, wherein the second side of the semiconductor device includes a plurality of conductive elements aligned with the metal structure and the recess of the first semiconductor device; and A conductive material is plated in the recess to electrically couple the metal structure of the first semiconductor device to the conductive element of the second semiconductor device.

19. The method according to claim 18, wherein: The plurality of metal structures are a plurality of first metal structures; The plurality of conductive elements include a plurality of second metal structures; and The second dielectric layer includes a plurality of second recesses at least partially exposing the second metal structure.

20. The method of claim 18, wherein the plurality of conductive elements comprises a plurality of conductive protrusions extending from the second dielectric layer.

21. The method of claim 20, wherein coupling the first and second dielectric layers further comprises inserting the plurality of conductive protrusions of the second semiconductor device into a corresponding plurality of recesses of the first semiconductor device.

22. The method of claim 18, wherein the conductive material comprises copper deposited in the recess by electroless plating.

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