Differential metal oxide thin film transistor array substrate and method of manufacturing the same

Abstract

This invention provides a differentiated metal-oxide-slim thin-film transistor array substrate and its fabrication method. The substrate includes two back-channel metal-oxide-slim TFTs with different structures. A first metal layer is disposed on the substrate, and a first insulating layer is disposed on the first metal layer. A second metal layer is disposed on the first insulating layer, and a second insulating layer is disposed on the second metal layer. An active layer is disposed on the second insulating layer, and a third metal layer is disposed on the active layer. The third metal layer is electrically connected to the first metal layer and / or the second metal layer through a first via. A third insulating layer is disposed on the third metal layer. The first and second insulating layers have different thicknesses. This invention employs a differentiated structural design for the different operating states of the TFTs in their respective circuits, ensuring that each TFT maintains consistent Vth even during long-term operation, thus preventing circuit failure.

Description

[Technical Field]

[0001] This invention relates to the field of display panels, and more specifically to a differentiated metal oxide thin-film transistor array substrate and its fabrication method. [Background Technology]

[0002] With the diversification of consumer market demands, AMOLED, Mini-LED, Micro-LED, VR devices, and other equipment are gradually becoming mainstream, and display technology is further developing towards higher color saturation, higher resolution, and higher refresh rates. Along with the development of display technology, higher demands are placed on the performance and stability of the film transistor devices driving the display panels. Therefore, metal oxide TFTs are favored due to their advantages such as low leakage current, high field-effect mobility, and large regional uniformity.

[0003] Metal-oxide-semiconductor (MTBF) TFT devices possess excellent electrical characteristics, but for high-end display devices, manufacturing stable and reliable thin-film transistor (TFT) devices remains a significant challenge. For example, to reduce bezel width in display panels, driving circuits are typically placed on both sides of the panel to replace traditional wiring and achieve a narrow bezel design. These driving circuits contain multiple sets of MTBF TFTs of different sizes, metal circuitry, and capacitors, commonly referred to as GIP (Gate Driver In Panel) or GOA (Gate Driver On Array). Alternatively, in active-matrix display panels, each pixel may have a voltage regulator circuit composed of multiple MTBF TFTs to ensure the current stability of the light-emitting device; this is called a voltage regulator circuit. To ensure the normal operation of these circuits, the characteristics of the MTBF TFTs must meet certain requirements. Specifically, the MTBF TFTs cannot have large threshold voltage (Vth) deviations or fluctuations in on / off current. Furthermore, the tolerance for device characteristic deviations varies considerably depending on the function of the MTBF TFT in the circuit. However, in actual panel operation, due to the different functions of the circuitry within the metal oxide TFT, the operating states of the devices vary significantly. Some devices may remain in an off state for extended periods, while others require frequent activation. Furthermore, devices operating under high voltage in certain circuits also need to have minimal Vth deviation. Given these differences in device operating pressure, even if the Vth of the metal oxide TFT devices are initially identical, after prolonged use or stress testing in harsh environments, differences in Vth offset will inevitably appear. If these differences exceed the operating range allowed by the driving circuit or voltage regulator circuit, display abnormalities will occur.

[0004] The discrepancy between the functional characteristics of the circuit and the actual operating state of the device leads to variations in electrical degradation, placing higher demands on the stability of metal-oxide-semiconductor (MEO) TFT devices. Current development strategies focus on improving overall stability; however, given the trend towards miniaturization of MEO TFTs driven by high resolution, the short-channel effect caused by reduced channel length makes it even more difficult to maintain stable device characteristics during long-term operation. [Summary of the Invention]

[0005] The technical problem to be solved by the present invention is to provide a differentiated metal oxide thin film transistor array substrate and its preparation method. The invention makes structural differences for the different operating states of TFTs in the circuit, so that different TFTs have different gate metal materials, gate metal thicknesses, gate insulating layer thicknesses, gate insulating layer materials and parasitic capacitances, so that each TFT can maintain the consistency of Vth under long-term operation and avoid circuit failure.

[0006] This invention is implemented as follows:

[0007] A differentiated metal oxide thin film transistor array substrate includes two back channel metal oxide TFTs with different structures disposed on the substrate, namely a first metal oxide TFT and a second metal oxide TFT.

[0008] The substrate is provided with a first metal layer, the first metal layer including a first gate and a driving signal line;

[0009] A first insulating layer is disposed on the first metal layer;

[0010] A second metal layer is disposed on the first insulating layer, and the second metal layer includes a second gate; the material of the second metal layer may be the same as that of the first metal layer.

[0011] A second insulating layer is disposed on the second metal layer, and an active layer is disposed on the second insulating layer. The active layer includes a first active layer and a second active layer. The first active layer corresponds to a first gate, and the second active layer corresponds to a second gate. A first through-hole is also formed on the first insulating layer and / or the second insulating layer to expose the surface of the first metal layer and / or the second metal layer.

[0012] The active layer is provided with a third metal layer, the third metal layer including a first source and a first drain electrically connected to the first active layer, a second source and a second drain electrically connected to the second active layer, and a data signal line; wherein, the third metal layer is electrically connected to the first metal layer and / or the second metal layer through the first via;

[0013] A third insulating layer is provided on the third metal layer;

[0014] Wherein, the film structure corresponding to the first gate is the first metal oxide TFT;

[0015] The film structure corresponding to the second gate is the second metal oxide TFT;

[0016] The first insulating layer and the second insulating layer have different thicknesses.

[0017] Furthermore, the thicknesses of the first insulating layer and the second insulating layer are...

[0018] Furthermore, the first insulating layer and the second insulating layer are made of a single layer of silicon oxide, silicon nitride, silicon oxynitride, titanium oxide or aluminum oxide, or a multilayer structure composed of two or more of the above materials; the materials and structures of the first insulating layer and the second insulating layer may be the same or different.

[0019] Furthermore, the first gate and the second gate have different thicknesses and materials, and the thicknesses of the first gate and the second gate can be selected within a certain range.

[0020] Furthermore, when the first metal layer adopts a single-layer structure, its material is aluminum, molybdenum, titanium, nickel, copper, silver, niobium, tantalum, tungsten or their alloys; when the first metal layer adopts a sandwich structure, its material is a stacked structure containing Al or Cu metal.

[0021] Furthermore, the stacked structure containing Al or Cu is Al / Mo, Mo / Al / Mo, Al / MoTi, Al / MoAlTi, Al / Ti, Ti / Al / Ti, Cu / Mo, Mo / Cu / Mo, or Cu / Ti.

[0022] This invention also relates to a method for fabricating a differentiated metal oxide thin-film transistor array substrate.

[0023] Includes the following steps:

[0024] S1. A first metal layer is formed on the substrate to serve as a first gate or driving signal line; the first metal layer may be a single-layer or sandwich structure.

[0025] S2. Form a first insulating layer on top of the first metal layer;

[0026] S3. Form a second metal layer on the first insulating layer. The material of the second metal layer can be the same as that of the first metal layer.

[0027] S4. Form a second insulating layer on top of the second metal layer;

[0028] S5. An active layer is formed on the second insulating layer, the active layer including a first active layer and a second active layer, the first active layer corresponding to a first gate and the second active layer corresponding to a second gate.

[0029] After the active layer is fabricated, a first through-hole is formed on the first insulating layer and / or the second insulating layer to expose the surface of the first metal layer or the second metal layer.

[0030] S6. A third metal layer is formed on the active layer, the third metal layer including a first source and a first drain electrically connected to the first active layer, a second source and a second drain electrically connected to the second active layer, and a data signal line; wherein the third metal layer is electrically connected to the first metal layer or the second metal layer through the first via.

[0031] S7. A third insulating layer is formed on the third metal as a passivation layer, and the material selection is the same as that of the first insulating layer.

[0032] The first insulating layer and the second insulating layer have different thicknesses.

[0033] Furthermore, the thicknesses of the first insulating layer and the second insulating layer are...

[0034] The first insulating layer and the second insulating layer are made of a single layer of silicon oxide, silicon nitride, silicon oxynitride, titanium oxide or aluminum oxide, or a multilayer structure composed of two or more of the above materials; the materials and structures of the first insulating layer and the second insulating layer may be the same or different.

[0035] Furthermore, the first gate and the second gate have different thicknesses and materials, and the thicknesses of the first gate and the second gate can be selected within a certain range. .

[0036] Furthermore, when the first metal layer adopts a single-layer structure, its material is aluminum, molybdenum, titanium, nickel, copper, silver, niobium, tantalum, tungsten or their alloys. When the first metal layer adopts a sandwich structure, its material is a stacked structure containing Al or Cu metal, and the stacked structure containing Al or Cu is Al / Mo, Mo / Al / Mo, Al / MoTi, Al / MoAlTi, Al / Ti, Ti / Al / Ti, Cu / Mo, Mo / Cu / Mo, or Cu / Ti.

[0037] The present invention has the following advantages:

[0038] This invention proposes a differentiated metal-oxide-slim thin-film transistor array substrate structure design. Targeting the different operating states of TFTs within their respective circuits, the structure of certain TFTs is optimized. A first insulating layer is disposed on a first metal layer, a second metal layer is disposed on the first insulating layer, and a second insulating layer is disposed on the second metal layer. This allows different TFTs to have different gate metal materials, gate metal thicknesses, gate insulating layer thicknesses, gate insulating layer materials, and optimized parasitic capacitances. This ensures that each TFT maintains consistent Vth even during long-term operation, preventing circuit failure. The designed display panel exhibits higher stability, improving the problem of inconsistent Vth offset caused by differences in the operating states of different devices in existing circuits, and addressing the different allowable electrical deviation ranges for each TFT device in the circuit. [Attached Image Description]

[0039] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0040] Figure 1 This is a diagram showing the film structure of a differentiated metal oxide thin-film transistor array substrate according to the present invention.

[0041] Figure 2 This is a flowchart of a method for fabricating a differentiated metal oxide thin-film transistor array substrate according to the present invention.

[0042] Explanation of reference numerals in the attached figures:

[0043] substrate1;

[0044] First metal layer 2, first gate 21, drive signal line 22;

[0045] First insulating layer 3;

[0046] Second metal layer 4, second gate 41;

[0047] Second insulating layer 5, first through hole 51;

[0048] Active layer 6, first active layer 61, second active layer 62;

[0049] Third metal layer 7, first source 71, first drain 72, second source 73, second drain 74, data signal line 75;

[0050] Third insulating layer 8;

[0051] First metal oxide TFT100;

[0052] Second metal oxide TFT200.

Detailed Implementation Methods

[0053] The following will be combined with the appendix Figure 1-2 The technical solution of the present invention will be clearly and completely described in detail with specific embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments used, unless otherwise specified, are all commercially available conventional products.

[0054] In the description of this invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0055] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0056] See Figure 1-2 This invention relates to a differentiated metal oxide thin film transistor array substrate, comprising two back channel metal oxide TFTs with different structures disposed on the substrate, namely a first metal oxide TFT and a second metal oxide TFT; in practical use, differentiated design can be carried out for the different operating states of each metal oxide TFT, so that each metal oxide TFT can maintain Vth consistency under different operating states, thus avoiding circuit failure.

[0057] The substrate is provided with a first metal layer, the first metal layer including a first gate and a driving signal line;

[0058] A first insulating layer is disposed on the first metal layer;

[0059] A second metal layer is disposed on the first insulating layer, and the second metal layer includes a second gate; the material of the second metal layer may be the same as that of the first metal layer.

[0060] A second insulating layer is disposed on the second metal layer, and an active layer is disposed on the second insulating layer. The active layer includes a first active layer and a second active layer. The first active layer corresponds to a first gate, and the second active layer corresponds to a second gate. A first through-hole is also formed on the first insulating layer and / or the second insulating layer to expose the surface of the first metal layer and / or the second metal layer.

[0061] The active layer is provided with a third metal layer, the third metal layer including a first source and a first drain electrically connected to the first active layer, a second source and a second drain electrically connected to the second active layer, and a data signal line; wherein, the third metal layer is electrically connected to the first metal layer and / or the second metal layer through the first via;

[0062] A third insulating layer is provided on the third metal layer;

[0063] Wherein, the film structure corresponding to the first gate is the first metal oxide TFT;

[0064] The film structure corresponding to the second gate is the second metal oxide TFT;

[0065] The first insulating layer and the second insulating layer have different thicknesses.

[0066] In a preferred embodiment, the thicknesses of the first insulating layer and the second insulating layer are: The thickness of the gate insulating layer is also an important parameter for adjusting the characteristics of the TFT. The first and second insulating layers with the thickness range specified above are beneficial to improving the on-state current of the TFT and the gate's control over the TFT, while avoiding gate leakage current and improving the TFT bias stability.

[0067] In a preferred embodiment, the first and second insulating layers are made of a single layer of silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, or aluminum oxide, or a multilayer structure composed of two or more of the above materials; the materials and structures of the first and second insulating layers may be the same or different. The gate insulating layer selected from the above materials has better insulation properties and density, a larger dielectric constant, and better interface characteristics with the active layer;

[0068] In another structure of the array substrate of the present invention, while the first gate and the second gate are made of different metal materials, the TFT may have a first insulating layer and a second insulating layer. The first insulating layer and the second insulating layer may be made of the same material, such as silicon oxide, silicon nitride, or silicon oxynitride, that is, the gate insulating layer of the TFT is thicker than that of existing TFTs. The first insulating layer and the second insulating layer may also be made of different materials, such as using silicon nitride for the first insulating layer and silicon oxide for the second insulating layer;

[0069] In the array substrate of the present invention, the first insulating layer or the second insulating layer can be a multilayer structure composed of two or more materials, such as the first insulating layer being composed of a silicon nitride and silicon oxynitride double film, and the second insulating layer being silicon oxide.

[0070] In a preferred embodiment, the first gate and the second gate have different thicknesses and materials, and the thicknesses of the first gate and the second gate are selected within a certain range. By changing the material or thickness of the gate metal, differentiated designs can be implemented for different operating states, thereby maintaining Vth consistency and preventing circuit failure. In practice, the gate metals of different back-channel metal-oxide TFTs can be made of different materials, have different thicknesses, or both, which broadens the range of choices for differentiated designs.

[0071] In a preferred embodiment, when the first metal layer adopts a single-layer structure, its material is aluminum, molybdenum, titanium, nickel, copper, silver, niobium, tantalum, tungsten or their alloys; when the first metal layer adopts a sandwich structure, its material is a stacked structure containing Al or Cu metal.

[0072] In a preferred embodiment, the Al or Cu-containing stacked structure is Al / Mo, Mo / Al / Mo, Al / MoTi, Al / MoAlTi, Al / Ti, Ti / Al / Ti, Cu / Mo, Mo / Cu / Mo, or Cu / Ti. The gate metal needs to possess good conductivity, good contact with the gate insulating layer, and a similar coefficient of thermal expansion. Metals such as Al and Cu have low impedance and are good conductive materials, but their coefficients of thermal expansion differ significantly from those of the gate insulating layer materials such as silicon oxide and silicon nitride. After high-temperature processing, the threshold voltage of metal oxide TFTs with different channel aspect ratios (W / L) is not easily kept consistent. Long-term use or environmental stress testing will cause the TFT to deteriorate further. The coefficient of thermal expansion of Mo is close to that of SiOx and SiNx, which can effectively overcome the Vth deviation of devices with different W / L ratios. However, its relatively high impedance can easily lead to increased panel power consumption. Therefore, in specific implementations, a more suitable gate metal is selected according to different operating states to maintain consistent Vth and avoid circuit failure under different operating conditions.

[0073] In the traditional array substrate structure using back-channel TFT, the data signal lines and drive signal lines are separated only by the gate insulating layer. Due to the overall development of different W / L devices, the thickness of the gate insulating layer cannot be set too thick, resulting in a large parasitic capacitance at the intersection of the data signal lines and drive signal lines, which increases RC delay and increases panel power consumption, affecting the development of high-resolution display panels.

[0074] In this invention, a first insulating layer and a second insulating layer are disposed between the driving signal line of the first metal layer and the data signal line of the third metal layer, and are separated by the first insulating layer and the second insulating layer. Furthermore, the thickness of the first insulating layer and the second insulating layer in this invention can be designed according to the operating state of the TFT in the driving circuit, without having to consider the overall influence effect, so that the gate insulating layer film thickness limit is smaller. Increasing the thickness of the insulating layer between the gate driving line and the data signal line can reduce the generation of parasitic capacitance and improve the coverage of the gate insulating layer, thereby reducing the probability of electrostatic breakdown generated by the upper and lower metals.

[0075] This invention also relates to a method for fabricating a differentiated metal oxide thin-film transistor array substrate, comprising the following steps:

[0076] S1. A first metal layer is formed on the substrate to serve as the first gate and driving signal line; S2. A first insulating layer is formed on the first metal layer.

[0077] S3. Form a second metal layer on the first insulating layer. The material of the second metal layer can be the same as that of the first metal layer.

[0078] Preferably, the first gate and the second gate have different thicknesses and materials, and the thicknesses of the first gate and the second gate can be selected within a certain range.

[0079] S4. A second insulating layer is formed on the second metal layer; at this time, the first gate has a first insulating layer and a second insulating layer together forming a device gate, and the second gate has a second insulating layer as a device gate.

[0080] Preferably, the thickness of the first insulating layer and the second insulating layer is The first insulating layer and the second insulating layer are made of a single layer of silicon oxide, silicon nitride, silicon oxynitride, titanium oxide or aluminum oxide, or a multilayer structure composed of two or more of the above materials; the materials and structures of the first insulating layer and the second insulating layer may be the same or different.

[0081] S5. An active layer is formed on the second insulating layer. The active layer includes a first active layer and a second active layer. The first active layer corresponds to a first gate, and the second active layer corresponds to a second gate. The active layer is made of a metal oxide semiconductor material, such as ZnO, IGZO, IGZTO, ITZO, Pr-IZO, etc.

[0082] After the active layer is fabricated, a first via is formed on the first insulating layer and / or the second insulating layer to expose the surface of the first metal layer or the second metal layer, thereby achieving the effect of signal connection.

[0083] S6. A third metal layer is formed on the active layer. The third metal layer includes a first source and a first drain electrically connected to the first active layer, a second source and a second drain electrically connected to the second active layer, and a data signal line. The third metal layer can also be designed as a touch sensing signal line or a common electrode signal line according to the circuit design. The third metal layer is electrically connected to the first metal layer or the second metal layer through the first via.

[0084] S7. A third insulating layer is formed on the third metal as a passivation layer, and the material selection is the same as that of the first insulating layer.

[0085] The first insulating layer and the second insulating layer have different thicknesses.

[0086] In summary, this invention proposes a differentiated metal-oxide-slim thin-film transistor array substrate structure design. Targeting the different operating states of TFTs within their respective circuits, the structure of certain TFTs is optimized. A first insulating layer is disposed on a first metal layer, a second metal layer is disposed on the first insulating layer, and a second insulating layer is disposed on the second metal layer. This allows different TFTs to have different gate metal materials, gate metal thicknesses, gate insulating layer thicknesses, gate insulating layer materials, and optimized parasitic capacitances. This ensures that each TFT maintains consistent Vth even during long-term operation, preventing circuit failure. The designed display panel exhibits higher stability, improving the problem of inconsistent Vth offset caused by differences in the operating states of different devices in existing circuits, and addressing the different allowable electrical deviation ranges for each TFT device in the circuit.

[0087] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A differential metal oxide thin film transistor array substrate, characterized by: The substrate is provided with two back channel metal oxide TFTs with different structures, i.e. a first metal oxide TFT and a second metal oxide TFT; The substrate is provided with a first metal layer, which includes a first gate and a driving signal line; The first metal layer is provided with a first insulating layer; The first insulating layer is provided with a second metal layer, which includes a second gate; the material of the second metal layer is the same as or different from that of the first metal layer; The second metal layer is provided with a second insulating layer, and the second insulating layer is provided with an active layer, which includes a first active layer corresponding to the first gate and a second active layer corresponding to the second gate; the first insulating layer and / or the second insulating layer is also provided with a first through hole, which exposes the surface of the first metal layer and / or the second metal layer; The active layer is provided with a third metal layer, which includes a first source and a first drain electrically connected to the first active layer, a second source and a second drain electrically connected to the second active layer, and a data signal line; the third metal layer is electrically connected to the first metal layer and / or the second metal layer through the first through hole; The third metal layer is provided with a third insulating layer; The film layer structure corresponding to the first gate is the first metal oxide TFT; The film layer structure corresponding to the second gate is the second metal oxide TFT; The thicknesses of the first insulating layer and the second insulating layer are different; The thicknesses of the first insulating layer and the second insulating layer are 100Å-6000Å; The materials of the first insulating layer and the second insulating layer are single-layer silicon oxide, silicon nitride, silicon oxynitride, titanium oxide or aluminum oxide, or a multi-layer structure composed of two or more of the above materials; the materials and structures of the first insulating layer and the second insulating layer can be the same or different.

2. The differential metal oxide thin film transistor array substrate of claim 1, wherein: The thicknesses and materials of the first gate and the second gate are different, and the thicknesses of the first gate and the second gate are selected in the range of 50Å-6000Å.

3. The differential metal oxide thin film transistor array substrate of claim 1, wherein: When the first metal layer adopts a single-layer structure, the material thereof is aluminum, molybdenum, titanium, nickel, copper, silver, niobium, tantalum, tungsten or an alloy thereof; when the first metal layer adopts a sandwich structure, the material thereof is a laminated structure containing Al or Cu metal.

4. The differential metal oxide thin film transistor array substrate of claim 3, wherein: The laminated structure containing Al or Cu is Al / Mo, Mo / Al / Mo, Al / MoTi, Al / MoAlTi, Al / Ti, Ti / Al / Ti, Cu / Mo, Mo / Cu / Mo or Cu / Ti.

5. A method for fabricating a differentiated metal oxide thin-film transistor array substrate, characterized in that: The method comprises the following steps: S1. Forming a first metal layer on the substrate as a first gate or a driving signal line; the first metal layer can adopt a single-layer or sandwich structure; S2. Forming a first insulating layer on the first metal layer; S3. Forming a second metal layer on the first insulating layer; the material of the second metal layer is the same as that of the first metal layer; S4. Forming a second insulating layer on the second metal layer; S5, fabricating an active layer on the second insulating layer, the active layer comprising a first active layer and a second active layer, the first active layer corresponding to the first gate, and the second active layer corresponding to the second gate; After the active layer is fabricated, a first via hole is prepared on the first insulating layer and / or the second insulating layer to expose the surface of the first metal layer or the second metal layer; S6, fabricating a third metal layer on the active layer, the third metal layer comprising a first source electrode and a first drain electrode electrically connected to the first active layer, a second source electrode and a second drain electrode electrically connected to the second active layer, and a data signal line; wherein the third metal layer is electrically connected to the first metal layer or the second metal layer through the first via hole; S7, fabricating a third insulating layer on the third metal layer as a passivation layer, the material of which is the same as that of the first insulating layer; The thickness of the first insulating layer and the second insulating layer is different.

6. The method of claim 5, wherein the method further comprises: The thickness of the first insulating layer and the second insulating layer is 100Å~6000Å. The material of the first insulating layer and the second insulating layer is single-layer silicon oxide, silicon nitride, silicon oxynitride, titanium oxide or aluminum oxide, or a multi-layer structure composed of two or more of the above materials; the material and structure of the first insulating layer and the second insulating layer can be the same or different.

7. The method of claim 5, wherein the method further comprises: depositing a first metal oxide layer on the substrate; and depositing a second metal oxide layer on the first metal oxide layer. The thickness and material of the first gate and the second gate are different, and the thickness of the first gate and the second gate is selected in the range of 50Å~6000Å.

8. The method of claim 5, wherein the method further comprises: depositing a first metal oxide layer on the substrate; and depositing a second metal oxide layer on the first metal oxide layer. When the first metal layer adopts a single-layer structure, its material is aluminum, molybdenum, titanium, nickel, copper, silver, niobium, tantalum, tungsten or an alloy thereof; when the first metal layer adopts a sandwich structure, its material is a laminated structure containing Al or Cu metal, and the laminated structure containing Al or Cu is Al / Mo, Mo / Al / Mo, Al / MoTi, Al / MoAlTi, Al / Ti, Ti / Al / Ti, Cu / Mo, Mo / Cu / Mo, or Cu / Ti.

Images