Pre-sum nonlinear activation neural network in-memory computing system based on floating gate transistor and training method of pre-sum nonlinear activation neural network in-memory computing system

Abstract

The invention belongs to the related technical field of hardware implementation of neural networks, and discloses a floating gate transistor-based and pre-nonlinear activated neural network in-memory computing system and a training method thereof, the in-memory computing system comprises a plurality of neural network hierarchies connected in series, and each hierarchy comprises a computing array, an input module and an output module; the calculation array is a transistor array formed by floating gate transistors; the input module obtains analog voltage and applies the analog voltage to the floating gate transistor; the floating gate transistor realizes non-linear activation and weighted calculation to obtain current and gathers and outputs the current through a bit line; and the output module is used for reading the current on the bit line, converting the current into a voltage signal and outputting the voltage signal from the output end of the corresponding level. According to the subversive calculation normal form, the non-linear activation step is arranged in front of the summation step, the normal form fundamentally eliminates the requirements for an independent non-linear activation function circuit and an analog-digital converter in the middle of the non-linear activation function circuit, and therefore the system architecture is greatly simplified, and the circuit area and power consumption are remarkably reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of hardware implementation of neural networks, and more particularly relates to a floating gate transistor-based and pre-nonlinear activation neural network in-memory computing system and a training method thereof. BACKGROUND

[0002] In neural network computing centered on matrix vector multiplication, the traditional von Neumann architecture causes huge data transfer overhead due to the physical separation of processing and storage units, forming the so-called "von Neumann bottleneck". To solve this problem, the in-memory computing architecture emerges as the times require. It uses a cross array of resistive storage elements to integrate computing and storage into one, directly performing MVM operations in the storage array, thereby greatly improving the efficiency and energy consumption performance of AI computing.

[0003] Currently, neural network computing technology generally follows an operation paradigm of "multiplication and addition first and activation later". In the corresponding in-memory computing system: first, linear matrix vector multiplication is completed in the storage cross array in the analog domain; then, the obtained analog signal is converted into a digital signal through an analog-to-digital converter; finally, the digital signal is sent to an independent special circuit for calculation of the non-linear activation function. This two-step process of strictly separating linear core computation and non-linear activation processing constitutes the basic framework of the existing neural network in-memory computing system, which has a complex structure. However, this architecture has a complex structure and a large area.

[0004] Therefore, how to simplify the architecture of the neural network in-memory computing system is a technical problem to be solved at present. SUMMARY

[0005] In view of the above defects or improvement needs of the prior art, the present application provides a floating gate transistor-based and pre-nonlinear activation neural network in-memory computing system and a training method thereof, which aims to simplify the architecture of the neural network in-memory computing system.

[0006] To achieve the above-mentioned purpose, the following technical solutions are proposed.

[0007] According to a first aspect of the present application, a floating gate transistor-based and pre-nonlinear activation neural network in-memory computing system is provided, which includes a plurality of neural network levels connected in series, the input end of a subsequent level is connected to the output end of a previous level, the first level is an input layer, the last level is an output layer, and the levels in the middle are hidden layers; Among them, a single level includes a computing array, an input module and an output module. The computing array is a transistor array composed of floating gate transistors, each word line in the array is connected to the gate of all floating gate transistors in the corresponding row, each bit line in the array is connected to the drain of all floating gate transistors in the corresponding column, and the threshold voltage of each floating gate transistor represents the analog value of the neural network weight; The input module is configured to obtain an analog voltage representing an input signal from the input end of the corresponding level and apply the analog voltage to the gate of the corresponding floating gate transistor through the word line; after the gate of the floating gate transistor receives the analog voltage applied through the word line, the gate realizes nonlinear activation and weighted calculation to obtain a current and outputs the current through the bit line; The output module is configured to read the current on the bit line and convert the current into a voltage signal and then output the voltage signal from the output end of the corresponding level.

[0008] According to a second aspect of the present application, a training method of a floating gate transistor-based and previous nonlinear activation neural network memory computing system is provided, the training method comprising a forward propagation, a backward propagation and a weight update process, wherein, The forward propagation comprises: inputting an analog voltage representing a training sample into the input end of the input layer; in each level, after the analog voltage of the input end is applied to the computing array through the input module to realize nonlinear activation and weighted calculation to obtain a current and output the current through the bit line, the output module outputs a voltage signal and inputs the voltage signal into the input end of the next level; after the operation of each level, a prediction result is outputted at the output layer; The backward propagation comprises: calculating the deviation between the prediction result and a sample label to obtain an output layer error term, and propagating the output layer error term back layer by layer to obtain error terms of other levels; The weight update comprises: calculating the threshold voltage increment of the floating gate transistor in each level based on the error term, and adjusting the threshold voltage of the floating gate transistor representing the weight.

[0009] According to a third aspect of the present application, an electronic device is provided, comprising a memory and a processor, the memory stores a computer program, wherein the processor implements the steps of the above method when executing the computer program.

[0010] According to a fourth aspect of the present application, a computer readable storage medium is provided, which stores a computer program, wherein the computer program is executed by a processor to implement the steps of the above method.

[0011] According to a fifth aspect of the present application, a computer program product is provided, comprising a computer program or instructions, wherein the computer program or instructions are executed by a processor to implement the steps of the above method.

[0012] Overall, compared with the prior art, the above technical solutions conceived by the present application mainly have the following beneficial effects: The floating gate transistor-based and pre-activation nonlinear neural network in-memory computing system proposed in the present application, a single level includes a computing array, an input module and an output module, the computing array is a transistor array composed of floating gate transistors, after the level input end receives an analog voltage representing an input signal, the signal is applied to the gate of the floating gate transistor connected to the word line through the word line, and the signal enters the core of the system, the computing array, which is composed of a plurality of floating gate transistors, each transistor has two functions: its threshold voltage is used to store a weight value, and it also serves as an integrated operation unit, based on its inherent nonlinear current-voltage transfer characteristic based on the transistor EKV model, the weighting and nonlinear activation functions are integrated and realized in a single device at the moment of receiving the input voltage, and the output current directly represents the result of nonlinear activation and weighting processing, and after the collected current on the same bit line is converted into a voltage, it can be directly output to the next level, which is equivalent to summing the results of nonlinear activation and weighting processing, thereby realizing the activation and weighting summation operation in the neural network. Compared with the traditional "multiplication and addition first and then activation" operation paradigm, which first performs weighting summation based on a storage array and then uses an additional nonlinear activation circuit for activation, the present application breaks the conventional paradigm and proposes a revolutionary computing paradigm that places the nonlinear activation step before the summation step. The inherent and programmable nonlinear current-voltage physical characteristics of a single floating gate transistor are used to simultaneously serve as a weight storage unit and a nonlinear activation function, and the device nonlinearity, which is traditionally considered as a source of error, is transformed into a highly efficient computing resource. By integrating computation and activation in a single device, this paradigm fundamentally eliminates the need for independent nonlinear activation function circuits and analog-to-digital converters, thereby greatly simplifying the system architecture and significantly reducing circuit area and power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is the overall framework diagram of the floating gate transistor-based and pre-activation nonlinear neural network in-memory computing system in an embodiment of the present application; Figure 2 is a structural schematic diagram of a single neural network level in an embodiment of the present application; Figure 3 is a structural schematic diagram of a transistor array composed of floating gate transistors in an embodiment of the present application; Figure 4 is an integrated operation function schematic diagram of a single floating gate transistor in an embodiment of the present application; Figure 5 is a step flowchart of the in-memory computing system training method in an embodiment of the present application; Figure 6 is a trend chart of the system accuracy and training period in an embodiment of the present application. DETAILED DESCRIPTION

[0014] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0015] In-memory computing architectures integrate computation and storage by utilizing cross-arrays composed of memory elements, performing operations directly within the memory array, thereby significantly improving the efficiency of AI computing. However, current mainstream in-memory computing technologies generally follow a "multiply-add-then-activate" operational paradigm. This paradigm completes linear matrix-vector multiplication in the analog domain memory array, then converts the resulting analog signal into a digital signal via a high-power, large-area analog-to-digital converter (ADC), before feeding it into a separate dedicated circuit for calculating the nonlinear activation function. This design not only turns the ADC into a new performance bottleneck but also treats the inherent physical nonlinearity of the device itself as a serious defect that must be corrected, requiring complex compensation circuitry and increasing system overhead.

[0016] Based on this, the present invention proposes a new operating paradigm that greatly simplifies the system architecture and further reduces power consumption.

[0017] Example 1 like Figure 1 The diagram shown is an overall framework diagram of an in-memory computing system based on a floating gate transistor and a nonlinear activation neural network according to an embodiment of the present invention. The in-memory computing system includes multiple neural network layers connected in series, which are typically divided into an input layer, multiple hidden layers and an output layer. The input of the next layer is connected to the output of the previous layer. The first layer is the input layer, the last layer is the output layer, and the middle layer is the hidden layer.

[0018] like Figure 2 The diagram shown is a structural schematic of a single neural network layer in one embodiment of the present invention. The single neural network layer includes a computing array, an address decoding circuit, an input driving circuit, and a readout and conversion circuit.

[0019] The computing array is a transistor array composed of floating-gate transistors, such as... Figure 3 The diagram shows a schematic of a transistor array composed of floating gate transistors in one embodiment of the present invention. Each word line in the array is connected to the gate of all floating gate transistors in the corresponding row, and each bit line in the array is connected to the drain of all floating gate transistors in the corresponding column. The threshold voltage of each floating gate transistor represents the analog value of the neural network weight.

[0020] The input module is used to acquire an analog voltage representing the input signal from the input terminal of its respective level and apply it to the gate of the corresponding floating-gate transistor via a word line. Upon receiving the analog voltage applied via the word line, the gate of the floating-gate transistor undergoes nonlinear activation and weighted calculation to obtain a current, which is then aggregated and output via a bit line. Specifically, the input module may include an address decoding circuit and an input driving circuit. The address decoding circuit is connected to the computing array and is used to select the floating-gate transistor in the computing array according to control instructions. The input driving circuit is used to acquire an analog voltage representing the input signal from the input terminal of its respective level and apply it to the gate of the selected floating-gate transistor according to the selection by the address decoding circuit. (Continue to refer to...) Figure 3 Let's take a 5x5 computing array as an example. This array consists of 25 floating-gate transistors arranged in 5 rows and 5 columns, each storing a unique weight value. During computation, the analog voltage representing the input signal... via the Line lines are applied to the first The gate of the row transistor, each floating gate transistor utilizes its inherent, EKV-based nonlinear current-voltage transfer characteristics to achieve weighted and nonlinear activation functions within a single device.

[0021] The output module, as a peripheral circuit module, is electrically connected to the computing array. It reads the current on the bit lines, converts it into a voltage signal, and outputs it from the output terminal of its respective layer. Based on Hough's current law, the output currents from multiple transistors in the same column are summed online to a common bit line. Specifically, the output module includes a transimpedance amplifier. The output module reads the current on the bit lines, converts it into a voltage signal, and outputs it from the output terminal of its respective layer. When the layer is not an output layer, the output voltage at its output terminal serves as the input voltage for the next layer. When the layer is an output layer, the output voltage at its output terminal represents the output result of the in-memory computing system.

[0022] The signal flow and collaborative working process of the entire system are as follows: No. After the hierarchical input terminal receives the analog voltage representing the input signal, its first... A simulated voltage via the The root word line is applied to the gates of all floating-gate transistors connected to that word line. Next, the signal enters the core of the system—the computing array, which consists of multiple floating-gate transistors. For example... Figure 4The diagram illustrates the integrated computational function of a single floating-gate transistor in one embodiment of the present invention. Each transistor performs two functions: its threshold voltage stores a weight value, and it is also an integrated computational unit. This unit utilizes its inherent nonlinear current-voltage transfer characteristics based on the transistor EKV model to integrate weighting and nonlinear activation functions within a single device at the instant the input voltage is received. Its output current directly represents the result of nonlinear activation and weighting processing. Finally, the summed currents on the same bit lines are collected and converted into voltage, which can then be directly output to the next level. This is equivalent to summing the results of nonlinear activation and weighting processing, thereby realizing the activation and weighted summation operations in the neural network. Compared to the traditional method of first performing weighted summation based on the storage array and then using an additional nonlinear activation circuit for activation, the present invention breaks the conventional signal processing process. It directly uses the floating-gate transistors in the array to perform nonlinear activation and weighting operations on the input signal before summation. This eliminates the need for an additional nonlinear activation circuit, thereby simplifying the hardware structure, reducing latency, and significantly improving computational efficiency.

[0023] Example 2 This invention also proposes a training method for an in-memory computing system based on a floating-gate transistor and a pre-nonlinear activation neural network, such as... Figure 5 The diagram shows a flowchart of the training method for an in-memory computing system according to an embodiment of the present invention. The training method includes forward propagation, backpropagation, and weight update processes.

[0024] The forward propagation process includes: inputting the analog voltage representing the training sample into the input terminal of the input layer; in each layer, the analog voltage at its input terminal is applied to the computing array through the input module to achieve nonlinear activation and weighted calculation to obtain the current, which is then aggregated and output through the bit line and output through the output module to output the voltage signal and input to the input terminal of the next layer; after the operation of each layer, the prediction result is output at the output layer.

[0025] Specifically, initial weights are pre-programmed, meaning they are directly programmed into the threshold voltage of the floating-gate transistor as analog values. During forward propagation (i.e., inference), the analog voltage representing the input signal is directly applied to the transistor gate, and the transistor generates a nonlinear analog output current representing the activation result based on its programmed threshold voltage (i.e., weight). Subsequently, the output currents from multiple transistors in the array are linearly summed on a common bit line using Kirchhoff's current law and read out by a transimpedance amplifier. Since the "multiplication" and "activation" steps in matrix multiplication are completed instantaneously at the physical level of a single transistor without the need for ADC conversion, the circuit operation method for neural network inference proposed in this invention can complete calculations with extremely low latency and energy consumption, efficiently realizing the edge deployment and inference of neural network models.

[0026] With the first Taking the layer as an example, its input analog voltage Input one-to-one to each line of its character line, where the first... The analog voltage applied to the line is denoted as , For hierarchical indexes, To calculate the row index of the array, simulate the voltage. via the The row word line is applied to the gate of its floating gate transistor, utilizing the physical characteristics of the floating gate transistor to generate an output current representing the weighted and activated result, which is then transmitted via the first... The output current is obtained by summing the output currents of the column lines. , To calculate the column index of the array, the output current is converted into an analog voltage for output and used as the input analog voltage for the next layer. .

[0027] Specifically, based on the inherent nonlinear current-voltage transfer characteristics of the floating-gate transistor, which is based on the EKV model, the bit line sums the output current. Follow the following mathematical relationship: ; In the formula, hierarchical The Middle The output current of each line is summed to obtain the total output current. To be applied to the hierarchy The first computing array The analog voltage of the line, The bulk effect modulation coefficient, hierarchical The first computing array Line number The threshold voltage of the floating gate transistor in the column, Subthreshold slope factor, Given the known thermal voltage, The drain voltage is known.

[0028] As can be seen from the above expression, it involves weighting, nonlinear activation, and summation operations. Furthermore, weighting and nonlinear activation are performed first, followed by summation. Therefore, this invention eliminates the need for an additional nonlinear activation circuit, directly summing the output current on the bit lines. After being converted to an analog voltage, it is output from the j-th output port as the input to the next level and applied to the corresponding word line.

[0029] Unlike traditional digital NOR Flash in-memory computing architectures, this invention utilizes analog signals and amplitude encoding to directly program weights into the threshold voltage of the floating-gate transistor in the form of analog values. During computation, a single transistor receives the analog input voltage and, leveraging its inherent nonlinear physical characteristics, performs a one-step fusion calculation of weighting and nonlinear activation within the device, directly outputting an analog current representing the final result. This new paradigm of "activation before fusion" cleverly transforms device nonlinearity from a design challenge into a computational resource. Its core advantage lies in fundamentally eliminating the need for independent activation function circuits and intermediate analog-to-digital converters, thereby greatly simplifying the system architecture and significantly reducing circuit area and power consumption.

[0030] The backpropagation process includes: calculating the deviation between the prediction result and the sample label to obtain the output layer error term, and backpropagating the output layer error term layer by layer to obtain the error terms of other layers.

[0031] For example, assuming the output layer is the Nth level, the output layer error term is denoted as... The output layer error term Backpropagation is performed layer by layer to obtain the results of other layers. Error term .

[0032] Specifically, the calculation of error terms at each level based on the backpropagation algorithm follows the following mathematical process: ; ; ; ; ; In the formula, hierarchical The The error at each output terminal, The bulk effect modulation coefficient, Subthreshold slope factor, Given the thermal voltage, R is the resistance of the transimpedance amplifier in the output module. Drain voltage hierarchical The The error at each output terminal, and All are Softplus functions. and Both are Sigmoid functions. hierarchical The The voltage of the word line, which is also the level. The The voltage output from each output terminal, hierarchical The Line number The threshold voltage of the floating gate transistor in the column.

[0033] The weight update process includes: calculating the threshold voltage increment of the floating gate transistor in each level based on the error term, and adjusting the threshold voltage of the floating gate transistor representing the weight.

[0034] With the first Taking the layer as an example, the threshold voltage increment Based on the error term of the current layer and output current For threshold voltage The partial derivative is used to determine this, and the specific calculation formula is as follows: ; In the formula, hierarchical The Line number The threshold voltage increment of the floating gate transistor in the column, For machine learning rate.

[0035] Repeat the above training process until the output loss converges to the preset level, and you will get a trained system.

[0036] like Figure 6 The figure shown is a trend graph of the system accuracy versus training cycle in one embodiment of the present invention. It can be seen that the system accuracy increases rapidly with the increase of training cycle, the growth rate slows down after about 10 cycles, and gradually converges to a high level close to 100%. This shows that the training method used in the present invention is effective and can significantly improve the system performance and achieve a high accuracy through training.

[0037] In summary, the core of this invention lies in proposing a disruptive "pre-sum nonlinear activation" computational paradigm to address the power consumption and area bottlenecks caused by the traditional "multiply-add then activate" architecture. This "pre-sum nonlinear activation" paradigm relies on a computational array design based on floating-gate transistors (FTMTs). In this design, each FTMT not only stores an analog weight value through its programmable threshold voltage but also leverages its inherent nonlinear physical characteristics to integrate weighting and nonlinear activation computations within a single device. Based on this design, the system of this invention can efficiently realize the entire process of forward propagation, backward propagation, and weight update in a neural network. In forward propagation, the input analog voltage is directly converted into an output current representing the activated result via the array; in backward propagation and weight update, the threshold voltages of each transistor are adjusted based on the calculated error term. By integrating computation and activation functions into a single device, this invention fundamentally eliminates the need for independent activation circuits and intermediate analog-to-digital converters, transforming device nonlinearity from a design challenge into a computational resource, ultimately achieving a significant simplification of the system architecture and a substantial reduction in power consumption and area.

[0038] Example 3 The present invention also relates to an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described above.

[0039] The electronic device can be a desktop computer, laptop, handheld computer, or cloud server, etc. The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The memory can be used to store computer programs and / or modules. The processor implements various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory, and by accessing data stored in the memory.

[0040] Example 4 The present invention also relates to a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0041] Specifically, the memory may include high-speed random access memory, as well as non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart media cards (SMC), secure digital (SD) cards, flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.

[0042] Example 5 This invention provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps of the method described in the above embodiments of this invention.

[0043] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification. It should be noted that the terms "in one embodiment," "for example," and "again" are intended to illustrate the present invention and are not intended to limit the present invention.

[0044] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention.

Claims

1. A floating gate transistor based and pre-nonlinear activation neural network in-memory computing system, comprising: The in-memory computing system comprises a plurality of neural network layers connected in series, the input end of a subsequent layer is connected to the output end of a previous layer, the first layer is an input layer, the last layer is an output layer, and the layers in between are hidden layers; The single layer comprises a computing array, an input module and an output module; The computing array is a transistor array composed of floating gate transistors, each word line in the array is connected to the gate of all floating gate transistors in the corresponding row, each bit line in the array is connected to the drain of all floating gate transistors in the corresponding column, and the threshold voltage of each floating gate transistor represents the analog value of the neural network weight; The input module is configured to obtain the analog voltage representing the input signal from the input end of the layer and apply it to the gate of the corresponding floating gate transistor through the word line; after the gate of the floating gate transistor receives the analog voltage applied through the word line, it realizes nonlinear activation and weighted calculation to obtain a current and outputs the current through the bit line; The output module is configured to read the current on the bit line and convert it into a voltage signal before outputting from the output end of the layer.

2. The floating gate transistor-based and formerly non-linearly activated neural network in-memory computing system of claim 1, wherein, The input module comprises an address decoding circuit and an input driving circuit; The address decoding circuit is connected to the computing array and is configured to select the floating gate transistor in the computing array; The input driving circuit is configured to obtain the analog voltage representing the input signal from the input end of the layer and apply it to the gate of the selected floating gate transistor.

3. The floating gate transistor-based and formerly non-linearly activated neural network compute-in-memory system of claim 1, wherein, The output module comprises a transimpedance amplifier, and the output module is configured to read the current on the bit line and convert it into a voltage signal through the transimpedance amplifier before outputting from the output end of the layer.

4. A method of training a floating gate transistor-based and pre-nonlinearly activated neural network in-memory computing system according to any one of claims 1 to 3, characterized in that, The training method comprises a forward propagation, a backward propagation and a weight updating process, wherein, The forward propagation comprises: inputting the analog voltage representing the training sample into the input end of the input layer, in each layer, after the analog voltage of the input end is applied to the computing array through the input module to realize nonlinear activation and weighted calculation to obtain a current and output the current through the bit line, the output module outputs a voltage signal and inputs the voltage signal into the input end of the next layer, and after the operation of each layer, a prediction result is output at the output layer; The backward propagation comprises: calculating the deviation between the prediction result and the sample label to obtain an output layer error term, and propagating the output layer error term back layer by layer to obtain error terms of other layers; The weight updating comprises: calculating the threshold voltage increment of the floating gate transistor in each layer based on the error term, and adjusting the threshold voltage of the floating gate transistor representing the weight.

5. The training method of claim 4, wherein, The current output through the bit line satisfies the following relationship: ； wherein is the level in the middle of the column sums up the output currents of the column bit lines to obtain a summed output current, is the applied voltage to the level in the middle of the column computes the analog voltage of the row word line in the middle of the column is the body effect modulation factor, is the level in the middle of the column computes the threshold voltage of the floating gate transistor in the middle of the column in the middle of the column is the subthreshold slope factor, is the known thermal voltage, is the known drain voltage.

6. The training method of claim 4, wherein, The calculation formula of the error term of each layer is: ； ； ； ； ； wherein is the error of the th output of the th layer, is the bulk effect modulation factor, is the sub-threshold slope factor, is the known thermal voltage, R is the resistance value in the output module, is the drain voltage, is the error of the th output of the th layer, and are both Softplus functions, and are both Sigmoid functions, is the voltage of the th word line of the th layer, which is also the voltage output by the th output of the th layer, is the threshold voltage of the floating gate transistor in the th row and the th column of the th layer.

7. The training method of claim 6, wherein, The calculation formula of the threshold voltage increment is: ； wherein is a threshold voltage increment of a floating gate transistor in row i and column j of tier k, is a threshold voltage increment of a floating gate transistor in row i and column j of tier k, is a threshold voltage increment of a floating gate transistor in row i and column j of tier k, is a threshold voltage increment of a floating gate transistor in row i and column j of tier k, is a machine learning rate, is an analog voltage applied to a word line in row i of a compute array in tier k, is an analog voltage applied to a word line in row i of a compute array in tier k, is a threshold voltage increment of a floating gate transistor in row i and column j of tier k, is a threshold voltage increment of a floating gate transistor in row i and column j of tier k, is a threshold voltage increment of a floating gate transistor in row i and column j of tier k, is a threshold voltage increment of a floating gate transistor in row i and column j of tier k, is a threshold voltage increment of a floating gate transistor in row i and column j of tier k. 8.An electronic device comprising a memory and a processor, the memory storing a computer program, wherein, The processor executes the computer program to realize the steps of the method of any one of claims 4 to 7.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to realize the steps of the method of any one of claims 4 to 7.

10. A computer program product comprising computer programs or instructions, characterized in that, The computer program or instructions are executed by the processor to realize the steps of the method of any one of claims 4 to 7.

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