High electron mobility transistor

Abstract

A high electron mobility transistor (HEMT) includes an active region in which a channel is formed and a field region surrounding the active region. The HEMT can include a channel layer, a barrier layer on the channel layer and configured to induce a two-dimensional electron gas (2DEG) in the channel layer, a source and a drain in the active region on the barrier layer, and a gate on the barrier layer. The gate can protrude on the barrier layer from the active region to the field region. The gate can include a first gate and a second gate. The first gate can be in the active region and the second gate can be in a border region between the active region and the field region. A work function of the second gate can be different from a work function of the first gate.

Description

Technical Field

[0001] The present disclosure relates to high electron mobility transistors. Background Art

[0002] Various power conversion systems may require power devices that control current flow by turning on / off switches. In power conversion systems, the efficiency of the power devices may affect the efficiency of the entire system.

[0003] Improving the efficiency of silicon (Si)-based power devices can be difficult due to limitations in silicon's physical properties and / or manufacturing process limitations. To overcome these limitations, research and development are underway to improve conversion efficiency by applying III-V compound semiconductors, such as gallium nitride, to power devices. Recently, high electron mobility transistors (HEMTs) using heterojunction structures of compound semiconductors have been studied. Summary of the Invention

[0004] A high electron mobility transistor is provided.

[0005] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0006] According to one embodiment, a high electron mobility transistor (HEMT) is provided, including an active region in which a channel is formed and a field region surrounding the active region. The HEMT includes: a channel layer; a barrier layer on the channel layer and configured to induce a two-dimensional electron gas (2DEG) in the channel layer; a source and a drain on the barrier layer in the active region; and a gate on the barrier layer, the gate protruding from the active region into the field region. The gate includes a first gate and a second gate. The first gate is in the active region. The second gate is located in a boundary region of the HEMT between the active region and the field region. The work function of the second gate is different from the work function of the first gate.

[0007] In some embodiments, the material of the second gate may have a work function lower than that of the material of the first gate.

[0008] In some embodiments, the material of the first gate and the material of the second gate may have a work function of about 4.0 eV to about 6.0 eV.

[0009] In some embodiments, the first gate and the second gate may include a material that forms a Schottky barrier with underlying layers.

[0010] In some embodiments, the first gate and the second gate may independently include at least one of titanium nitride (TiN), nickel (Ni), tungsten (W), molybdenum (Mo), palladium (Pd), and platinum (Pt).

[0011] In some embodiments, the channel layer may include a gallium nitride (GaN)-based material, and the barrier layer may include a nitride including at least one of aluminum (Al), gallium (Ga), indium (In), and boron (B).

[0012] In some embodiments, the HEMT may further include a depletion-forming layer between the channel layer and the gate. The depletion-forming layer may be configured to form a depletion region in the 2DEG.

[0013] In some embodiments, the depletion-forming layer may include a p-type Group III-V based nitride semiconductor.

[0014] In some embodiments, the gate electrode can be between the source electrode and the drain electrode. The gate electrode can be parallel to the source electrode and the drain electrode.

[0015] In some embodiments, the gate can surround the source.

[0016] In some embodiments, the first gate may cover the second gate. Alternatively, in some embodiments, the first gate may not cover the second gate.

[0017] According to another embodiment, a high electron mobility transistor (HEMT) is provided, comprising an active region in which a channel is formed and a field region surrounding the active region. The HEMT includes: a channel layer; a barrier layer on the channel layer and configured to induce a two-dimensional electron gas (2DEG) in the channel layer; a source and a drain on the barrier layer in the active region; a gate on the barrier layer, the gate protruding from the active region into the field region; and a depletion-forming layer between the channel layer and the gate, the depletion-forming layer configured to form a depletion region in the 2DEG. The thickness of the depletion-forming layer in the active region may be different from the thickness of the depletion-forming layer in the boundary region between the active region and the field region of the HEMT.

[0018] In some embodiments, a thickness of the depletion-forming layer in the active region may be smaller than a thickness of the depletion-forming layer in a boundary region between the active region and the field region.

[0019] In some embodiments, the channel layer may include a gallium nitride (GaN)-based material, and the barrier layer may include a nitride including at least one of aluminum (Al), gallium (Ga), indium (In), and boron (B).

[0020] In some embodiments, the depletion-forming layer may include a p-type Group III-V based nitride semiconductor.

[0021] In some embodiments, the gate may include a first gate and a second gate. The first gate may be in the active region. The second gate may be in the boundary region between the active region and the field region. The work function of the first gate may be different from the work function of the second gate.

[0022] In some embodiments, the second gate may include a material having a lower work function than that of the first gate.

[0023] In some embodiments, the gate electrode and the depletion-forming layer may be between the source electrode and the drain electrode. The gate electrode and the depletion-forming layer may be parallel to the source electrode and the drain electrode.

[0024] In some embodiments, the gate and the depletion-forming layer can surround the source.

[0025] According to another embodiment, a high electron mobility transistor (HEMT) is provided, including an active region in which a channel is formed and a field region surrounding the active region. The HEMT includes: a channel layer; a barrier layer on the channel layer and configured to induce a two-dimensional electron gas (2DEG) in the channel layer; a source and a drain on the barrier layer in the active region; and a gate on the barrier layer. The gate extends from the active region to the field region. The gate includes a first portion above the active region and a second portion above a boundary region of the HEMT between the active region and the field region. The first portion and the second portion of the gate have at least one of different work functions and different vertical distances from an upper surface of the barrier layer.

[0026] In some embodiments, the HEMT may further include a depletion-forming layer between the gate and the channel layer. The depletion-forming layer may be configured to form a depletion region in the 2DEG.

[0027] In some embodiments, the thickness of the depletion-forming layer in the active region may be different from the thickness of the depletion-forming layer in the boundary region between the active region and the field region of the HEMT.

[0028] In some embodiments, the gate may include a first gate and a second gate. The first portion of the gate may be the first gate. The second portion of the gate may be the second gate. The first gate and the second gate may have different work functions.

[0029] In some embodiments, the gate can surround the source. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a plan view of a high electron mobility transistor (HEMT) according to an example embodiment;

[0032] Figure 2 It is the HEMT along Figure 1 A cross-sectional view taken along line AA';

[0033] Figure 3 It is the HEMT along Figure 1 A cross-sectional view taken along line BB';

[0034] Figure 4 It is the HEMT along Figure 1 A cross-sectional view taken along line CC';

[0035] Figure 5 The current (I d )-voltage (V g ) characteristic curve;

[0036] Figure 6A shows the current (I d )-voltage (V g ) characteristic curve;

[0037] Figure 6B shows an energy diagram of a HEMT according to the work function of the gate material;

[0038] Figure 7 is a cross-sectional view of a HEMT according to another example embodiment;

[0039] Figure 8 is a cross-sectional view of a HEMT according to another example embodiment;

[0040] Figure 9 is a plan view of a HEMT according to another example embodiment;

[0041] Figure 10 It is the HEMT along Figure 9 A cross-sectional view taken along line AA';

[0042] Figure 11 It is the HEMT along Figure 9 A cross-sectional view taken along line BB';

[0043] Figure 12 It is the HEMT along Figure 9 A cross-sectional view taken along line CC';

[0044] Figure 13 It is the HEMT along Figure 9 A cross-sectional view taken along line D-D';

[0045] Figure 14 is a plan view of a HEMT according to another example embodiment;

[0046] Figure 15 It is the HEMT along Figure 14A cross-sectional view taken along line AA';

[0047] Figure 16 It is the HEMT along Figure 14 A cross-sectional view taken along line BB';

[0048] Figure 17 It is the HEMT along Figure 14 A cross-sectional view taken along line CC';

[0049] Figure 18A shows the distribution of Mg doping concentration according to the etching depth of the depletion forming layer;

[0050] Figure 18B The current (I d )-voltage (V g ) characteristic curve;

[0051] Figure 19 is a plan view of a HEMT according to another example embodiment;

[0052] Figure 20 It is the HEMT along Figure 19 A cross-sectional view taken along line BB';

[0053] Figure 21 is a plan view of a HEMT according to another example embodiment;

[0054] Figure 22 It is the HEMT along Figure 21 A cross-sectional view taken along line AA';

[0055] Figure 23 It is the HEMT along Figure 21 A cross-sectional view taken along line BB';

[0056] Figure 24 It is the HEMT along Figure 21 A cross-sectional view taken along line CC';

[0057] Figure 25 It is the HEMT along Figure 21 A cross-sectional view taken along line D-D';

[0058] Figure 26 is a plan view of a HEMT according to another example embodiment;

[0059] Figure 27 It is the HEMT along Figure 26 a cross-sectional view taken along line BB'; and

[0060] Figure 28is a schematic diagram of an electronic device according to one embodiment. DETAILED DESCRIPTION

[0061] Reference will now be made in detail to the embodiments, examples of which are shown in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below with reference to the accompanying drawings only to illustrate various aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of," when following a list of elements, modify the entire list of elements and do not modify the individual elements in the list. For example, "at least one of A, B, and C," "at least one of A, B, or C," "one of A, B, C, or a combination thereof," and "one of A, B, C, and a combination thereof" may each be construed to cover any of the following combinations: A; B; A and B; A and C; B and C; and A, B, and C."

[0062] Hereinafter, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals represent the same elements, and for the sake of clarity and convenience of explanation, the size of each element in the drawings may be exaggerated. On the other hand, the following embodiments are merely examples, and various modifications can be made from these embodiments.

[0063] Hereinafter, the term "above..." or "on..." may include not only those that are directly above, below, to the left of, and to the right of... in a contact manner, but also those that are above, below, to the left of, and to the right of... in a non-contact manner. In other words, a first element "above" or "on" a second element may be directly on the second element (or directly above the second element), but the first element may also be on (or above) an intermediate element between the first and second elements. The singular forms "a", "an", and "the" as used herein are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be understood that the terms "comprising", "including", or "having" as used herein specify the presence of the elements mentioned, but do not exclude the presence or addition of one or more other elements.

[0064] The use of the term "the" and similar referents may correspond to both the singular and the plural. The steps comprising a method may be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context, and are not necessarily limited to the order recited.

[0065] Furthermore, terms such as “unit” and “module” described in the specification refer to units that process at least one function or operation and can be implemented as hardware, software, or a combination of hardware and software.

[0066] The connecting lines or connecting members shown in the drawings are intended to represent example functional relationships and / or physical or logical connections between the various elements. It should be noted that many alternative or additional functional relationships, physical connections or logical connections may exist in a practical device.

[0067] All illustrations or illustrative terms are used in the embodiments only to describe the embodiments in detail, and the scope of the present disclosure is not limited by the illustrations or illustrative terms unless they are limited by the claims.

[0068] A high electron mobility transistor (HEMT) includes semiconductor layers with different electrical polarization characteristics. In a HEMT, a semiconductor layer with a relatively large polarizability can induce a two-dimensional electron gas (2DEG) in another semiconductor layer bonded to it. The 2DEG can have very high electron mobility.

[0069] On the other hand, when a HEMT is in a normally-on state, where current flows due to the low resistance between the drain and source electrodes when the gate voltage is 0V, current and power consumption may occur. To shut off the current between the drain and source electrodes, a negative voltage must be applied to the gate. As a solution to these problems, a depletion-forming layer is provided to achieve a normally-off characteristic that shuts off the current between the drain and source electrodes when the gate voltage is 0V.

[0070] Figure 1 is a plan view of a HEMT 100 according to an example embodiment. Figure 2 HEMT 100 is along Figure 1 A cross-sectional view taken along line AA', Figure 3 HEMT 100 is along Figure 1 A cross-sectional view taken along line BB'. Figure 4 HEMT 100 is along Figure 1 A cross-sectional view taken along line CC'.

[0071] Reference Figures 1 to 4 , the HEMT 100 includes an active region R1 in which a channel is formed, and a field region R2 provided as an inactive region to surround the active region R1 .

[0072] The HEMT 100 includes a channel layer 110 , a barrier layer 120 provided on the channel layer 110 , a source 131 and a drain 132 provided on the barrier layer 120 , a depletion-forming layer 140 provided on the barrier layer 120 between the source 131 and the drain 132 , and a gate 150 provided on the depletion-forming layer 140 .

[0073] The channel layer 110 may be provided on a substrate (not shown). The substrate may include, for example, sapphire, Si, SiC, or GaN, but the present disclosure is not limited thereto, and the substrate may include various other materials.

[0074] The channel layer 110 may include a III-V compound semiconductor material. For example, the channel layer 110 may include a GaN-based material layer. As a specific example, the channel layer 110 may include a GaN layer. In this case, the channel layer 110 may include an undoped GaN layer. In some cases, the channel layer 110 may include a GaN layer doped with certain impurities.

[0075] A buffer layer (not shown) may be further provided between the channel layer 110 and the substrate. The buffer layer reduces the difference in lattice constant and thermal expansion coefficient between the substrate and the channel layer 110. The buffer layer may include a nitride containing at least one of aluminum (Al), gallium (Ga), indium (In), and boron (B), and may have a single-layer structure or a multilayer structure. For example, the buffer layer may include at least one of AlN, GaN, AlGaN, InGaN, AlInN, and AlGaInN. A seed layer (not shown) for buffer layer growth may be further provided between the substrate and the buffer layer.

[0076] The barrier layer 120 may be provided on the channel layer 110. The barrier layer 120 may induce 2DEG in the channel layer 110. The 2DEG may be formed in the channel layer 110 under the interface between the channel layer 110 and the barrier layer 120. The barrier layer 120 may include a semiconductor material different from that of the channel layer 110.

[0077] The barrier layer 120 may include, for example, a nitride containing at least one of Al, Ga, In, and B. As a specific example, the barrier layer 120 may include at least one of AlGaN, AlInN, InGaN, AlN, and AlInGaN. However, the present disclosure is not limited thereto. The barrier layer 120 may include an undoped layer, but may also include a layer doped with certain impurities.

[0078] On the barrier layer 120, the source electrode 131 and the drain electrode 132 are separated from each other. The source electrode 131 and the drain electrode 132 are provided in the active region R1 of the barrier layer 120. The source electrode 131 and the drain electrode 132 can be provided parallel to each other in the y-axis direction. The source electrode 131 and the drain electrode 132 can include, for example, a conductive material such as Ti or Al. On the other hand, the source electrode 131 and the drain electrode 132 can be provided in contact with the channel layer 110.

[0079] The depletion forming layer 140 is provided on the barrier layer 120 between the source 131 and the drain 132. The depletion forming layer 140 may be provided in parallel with the source 131 and the drain 132 in the y-axis direction. The depletion forming layer 140 may be provided to protrude from the active region R1 to the field region R2.

[0080] The depletion-forming layer 140 may include a p-type semiconductor material. The depletion-forming layer 140 may include a III-V-based nitride semiconductor. The depletion-forming layer 140 may include, for example, a material in which at least one of GaN, AlGaN, InN, AlInN, InGaN, and AlInGaN is doped with p-type impurities. As a specific example, the depletion-forming layer 140 may include a p-GaN layer.

[0081] Because the depletion forming layer 140 can increase the energy band gap of the portion of the barrier layer 120 located thereunder, a depletion region of the 2DEG can be formed in the portion of the channel layer 110 corresponding to the depletion forming layer 140. Therefore, the portion of the 2DEG corresponding to the depletion forming layer 140 may be destroyed, or may have characteristics (e.g., electron concentration, etc.) different from those of the remaining portion. The region where the 2DEG is destroyed may be referred to as a "disconnected region." Due to the disconnected region, the power device may have a normally-off characteristic, wherein when the gate voltage is 0V, the current between the drain 132 and the source 131 is turned off.

[0082] The gate 150 is provided on the depletion forming layer 140. The gate 150 may be provided in parallel with the source 131 and the drain 132 in the y-axis direction. The gate 150 may be provided to protrude from the active region R1 to the field region R2. A gate contact 170 may be provided at an end of the gate 150.

[0083] The gate 150 may include a first gate 151 and a second gate 152. The first gate 151 may be provided in the active region R1, and the second gate 152 may be provided in the boundary region R3 between the active region R1 and the field region R2. Alternatively, the first gate 151 may be provided in the field region R2. However, the present disclosure is not limited thereto, and the second gate 152 may be provided in the field region R2.

[0084] The first gate 151 and the second gate 152 may be provided to form a Schottky barrier with the depletion forming layer 140 located thereunder. Specifically, the first gate 151 may form a Schottky barrier with the depletion forming layer 140 in the active region R1, and the second gate 152 may form a Schottky barrier with the depletion forming layer 140 in the boundary region R3 between the active region R1 and the field region R2. Figure 3 As shown, the first gate 151 may be provided to cover the second gate 152. However, the present disclosure is not limited thereto. As will be described later, the first gate 151 may be provided so as not to cover the second gate 152.

[0085] The first gate 151 and the second gate 152 may include materials having different work functions from each other. Specifically, the second gate 152 may include a material having a work function lower than the work function of the first gate 151. The first gate 151 and the second gate 152 may include different types of materials having different work functions from each other. However, the present disclosure is not limited thereto, and the first gate 151 and the second gate 152 may include the same type of material having different work functions from each other. The first gate 151 and the second gate 152 may include, for example, a material having a work function of about 4.0 eV to about 6.0 eV. For example, the first gate 151 and the second gate 152 may include titanium nitride (TiN), nickel (Ni), tungsten (W), molybdenum (Mo), palladium (Pd) or platinum (Pt). However, the present disclosure is not limited thereto.

[0086] In the present embodiment, because the gate 150 includes the first gate 151 and the second gate 152, and the first gate 151 and the second gate 152 include materials having different work functions from each other, as will be described later, the threshold voltage of the edge transistor formed in the boundary region R3 between the active region R1 and the field region R2 can be increased, and thus a current-voltage characteristic curve without a hump can be obtained.

[0087] Figure 5 The current (I d )-voltage (V g ) characteristic curve. Figure 5 In the embodiment, the GaN layer is used as the channel layer, the AlGaN layer is used as the barrier layer, and the p-GaN layer is used as the depletion forming layer.

[0088] In a general HEMT, when a voltage is applied to the gate, the gate electric field is less distributed in the active region R1 (specifically, the active region R1 between the boundary region R3) than in the boundary region R3 between the active region R1 and the field region R2. Due to the uneven distribution of the gate electric field, the current (I d )-voltage (V g) A convex peak may appear in the characteristic curve.

[0089] Since the gate electric field is more distributed in the boundary region R3 between the active region R1 and the field region R2 than in the active region R1, even when the current (I d ) does not flow in the active region R1, the current (I d ) may also begin to flow in the boundary region R3. That is, when the voltage applied to the gate increases, the current (I d ) can be formed earlier in the boundary region R3 than in the active region R1. Therefore, the edge transistor formed in the boundary region R3 can have a first threshold voltage (V' th ), and the main transistor formed in the active region R1 may have a voltage higher than the first threshold voltage (V' th )The second threshold voltage (V th ).exist Figure 5 In the first threshold voltage (V' th ) and the second threshold voltage (V th ) between (ΔV th ) is measured to be approximately 1.2 V. Thus, when the HEMTs have different first threshold voltages (V' th ) and the second threshold voltage (V th ), it is difficult to design the operating characteristics of the HEMT as desired, and therefore, it may be difficult to apply the HEMT to power devices.

[0090] Figure 6A shows the current (I d )-voltage (V g ) characteristic curve. Figure 6B The energy diagram of a HEMT is shown according to the work function of the gate material. Figure 6A and Figure 6B In the embodiment, the GaN layer is used as the channel layer, the AlGaN layer is used as the barrier layer, and the p-GaN layer is used as the depletion forming layer.

[0091] Reference Figure 6A and Figure 6B , it can be seen that the threshold voltage increases as the work function of the gate material decreases, and the threshold voltage decreases as the work function of the gate material increases. In this way, the threshold voltage can be adjusted by changing the work function of the gate material.

[0092] In the HEMT 100 according to the present embodiment, a first gate 151 is provided in the active region R1, and a second gate 152 having a work function different from that of the first gate 151 is provided in the boundary region R3 between the active region R1 and the field region R2. The second gate 152 may include a material having a lower work function than that of the first gate 151. In this case, since the threshold voltage of the edge transistor formed in the boundary region R3 between the active region R1 and the field region R2 can be increased, a current-voltage characteristic curve with a peak eliminated therefrom can be obtained.

[0093] For example, in the above Figure 5 In the example, the first threshold voltage (V') of the edge transistor formed in the boundary region R3 between the active region R1 and the field region R2 is th ) and the second threshold voltage (V th ) between (ΔV th ) is measured to be approximately 1.2 V. When the first threshold voltage (V' th ) and the second threshold voltage (V th ) between (ΔV th )and Figure 6A When comparing the data shown, it can be seen that there is a difference of approximately 1.2V (ΔV th ) corresponds to a work function difference of about 0.4 eV. Therefore, the second gate 152 provided in the boundary region R3 between the active region R1 and the field region R2 is made of a material having a work function lower by about 0.4 eV than the work function of the first gate 151 provided in the active region R1, and a current-voltage characteristic curve without a convex peak can be obtained.

[0094] As described above, in the HEMT 100 according to the example embodiment, by providing the first gate 151 in the active region R1 and providing the second gate 152 having a work function different from that of the first gate 151 in the boundary region R3 between the active region R1 and the field region R2, the effect of the edge transistor formed in the boundary region R3 between the active region R1 and the field region R2 can be limited and / or suppressed. Therefore, a current-voltage characteristic curve without a convex peak can be obtained. As a result, a HEMT 100 having desired operating characteristics can be realized.

[0095] Figure 7 is a cross-sectional view of a HEMT 100 ′ according to another example embodiment, corresponding to a cross-sectional view taken along Figure 1 The cross section is taken along the line BB'. Figure 7The gate 150' includes a first gate 151' provided in the active region R1 and a second gate 152' provided in the boundary region R3 between the active region R1 and the field region R2. Unlike the above embodiment, the first gate 151' may be provided so as not to cover the second gate 152'.

[0096] Figure 8 is a cross-sectional view of a HEMT 100" according to another example embodiment, corresponding to a cross-sectional view taken along Figure 1 The cross section is taken along the line BB'. Figure 8 , the above depletion formation layer ( Figure 2 140 in the active region R1) is not provided on the barrier layer 120, and the gate 150 may be provided directly on the barrier layer 120. The gate 150 includes a first gate 151 provided in the active region R1 and a second gate 152 provided in the boundary region R3 between the active region R1 and the field region R2. The first gate 151 and the second gate 152 may include a material that forms a Schottky barrier with the barrier layer 120 thereunder.

[0097] Figure 9 is a plan view of a HEMT 200 according to another example embodiment. Figure 10 HEMT 200 is along Figure 9 A cross-sectional view taken along line AA', Figure 11 HEMT 200 is along Figure 9 A cross-sectional view taken along line BB'. Figure 12 HEMT 200 is along Figure 9 The cross-sectional view taken along line CC' is Figure 13 HEMT 200 is along Figure 9 Hereinafter, differences from the above-described embodiment will be mainly described.

[0098] Reference Figures 9 to 13 The HEMT 200 includes a channel layer 210, a barrier layer 220 provided on the channel layer 210, a source 231 and a drain 232 provided on the barrier layer 220, a depletion-forming layer 240 provided on the barrier layer 220, and a gate 250 provided on the depletion-forming layer 240. Since the channel layer, the barrier layer, the source, and the drain have been described above, their description is omitted.

[0099] A depletion forming layer 240 is provided on the barrier layer 220, and a gate 250 is provided on the depletion forming layer 240. The depletion forming layer 240 and the gate 250 may be provided to surround the source 231. The depletion forming layer 240 and the gate 250 may be provided to protrude from the active region R1 to the field region R2.

[0100] The gate 250 may include a first gate 251 and a second gate 252. The first gate 251 may be provided in the active region R1, and the second gate 252 may be provided in the boundary region R3 between the active region R1 and the field region R2. The first gate 251 and the second gate 252 may be provided to form a Schottky barrier with the depletion-forming layer 240 thereunder. The first gate 251 may be provided to cover the second gate 252. However, the present disclosure is not limited thereto. Alternatively, the first gate 251 may be provided so as not to cover the second gate 252.

[0101] The first gate 251 and the second gate 252 may include materials having different work functions. Specifically, the second gate 252 may include a material having a lower work function than the first gate 251. The first gate 251 and the second gate 252 may include, for example, a material having a work function of about 4.0 eV to about 6.0 eV. For example, the first gate 251 and the second gate 252 may include TiN, Ni, W, Mo, Pd, or Pt. However, the present disclosure is not limited thereto.

[0102] In the HEMT 200 according to this embodiment, the first gate 251 is provided in the active region R1, and the second gate 252 having a work function different from that of the first gate 252 is provided in the boundary region R3 between the active region R1 and the field region R2, thereby limiting and / or suppressing the effect of the edge transistor. In addition, because the depletion-forming layer 240 is provided so as to surround the source 231, the effect of the edge transistor formed in the boundary region between the active region R1 and the field region R2 can be more effectively limited and / or suppressed.

[0103] Figure 14 is a plan view of a HEMT 300 according to another example embodiment. Figure 15 It is a HEMT 300 along Figure 14 A cross-sectional view taken along line AA', Figure 16 It is a HEMT 300 along Figure 14 A cross-sectional view taken along line BB'. Figure 17 It is the same as HEMT300 Figure 14 Hereinafter, differences from the above-described embodiment will be mainly described.

[0104] Reference Figures 14 to 17 The HEMT 300 includes a channel layer 310, a barrier layer 320 provided on the channel layer 310, a source 331 and a drain 332 provided on the barrier layer 320, a depletion-forming layer 340 provided on the barrier layer 320 between the source 331 and the drain 332, and a gate 350 provided on the depletion-forming layer 340. Since the channel layer, the barrier layer, the source, and the drain have been described above, their description is omitted.

[0105] The depletion-forming layer 340 is provided on the barrier layer 320 between the source 331 and the drain 332. The depletion-forming layer 340 may be provided parallel to the source 331 and the drain 332 in the y-axis direction. The depletion-forming layer 340 may include a p-type semiconductor material. For example, the depletion-forming layer 340 may include a p-GaN layer.

[0106] The depletion-forming layer 340 may be provided so as to protrude from the active region R1 to the field region R2. The depletion-forming layer 340 may include a first depletion-forming layer 340a provided in the active region R1 and a second depletion-forming layer 340b provided in the boundary region R3 between the active region R1 and the field region R2. The first depletion-forming layer 340a may have a thickness different from that of the second depletion-forming layer 340b. Specifically, the first depletion-forming layer 340a provided in the active region R1 may have a first thickness (t1), and the second depletion-forming layer 340b provided in the boundary region R3 between the active region R1 and the field region R2 may have a second thickness (t2) greater than the first thickness (t1).

[0107] The depletion-forming layer 340 can be formed by the following method. A material layer for forming depletion is formed on the barrier layer 320 to a second thickness (t2). The material layer formed in the active region R1 is etched to a specific depth to have a first thickness (t1). Thus, a first depletion-forming layer 340a having a first thickness (t1) can be formed in the active region R1, and a second depletion-forming layer 340b having a second thickness (t2) can be formed in the boundary region R3 between the active region R1 and the field region R2.

[0108] A gate 350 is provided on the depletion-forming layer 340. The gate 350 may be provided in parallel with the source 331 and the drain 332 in the y-axis direction. Like the depletion-forming layer 340, the gate 350 may be provided so as to protrude from the active region R1 to the field region R2. The gate 350 may include a material that forms a Schottky barrier with the depletion-forming layer 340 thereunder. For example, the gate 350 may include TiN, Ni, W, Mo, Pd, or Pt, but the present disclosure is not limited thereto.

[0109] In this embodiment, the first depletion-forming layer 340a provided in the active region R1 is formed to be thinner than the second depletion-forming layer 340b provided in the boundary region R3 between the active region R1 and the field region R2. Therefore, as will be described later, the threshold voltage of the main transistor formed in the active region R1 can be lowered, and a current-voltage characteristic curve without a peak can be obtained.

[0110] Figure 18A The distribution of Mg doping concentration according to the etching depth of the depletion forming layer is shown. Figure 18BThe current (I d )-voltage (V g ) characteristic curve. Figure 18A and Figure 18B In the CMOS process, the GaN layer is used as the channel layer, the AlGaN layer is used as the barrier layer, and the Mg-doped p-GaN layer is used as the depletion forming layer.

[0111] Reference Figure 18A , as the etching depth of the p-GaN depletion forming layer increases, the Mg doping concentration decreases. It can be seen that as the etching depth of the p-GaN depletion forming layer increases and thus the thickness of the p-GaN depletion forming layer decreases, the Mg doping concentration decreases.

[0112] Reference Figure 18B As the etching depth of the p-GaN depletion forming layer increases, the threshold voltage of the main transistor formed in the active region decreases. It can be seen that as the etching depth of the p-GaN depletion forming layer increases and the thickness of the p-GaN depletion forming layer decreases, the threshold voltage of the main transistor formed in the active region R1 decreases. As described above, the threshold voltage of the main transistor can be adjusted by changing the thickness of the p-GaN depletion forming layer formed in the active region R1.

[0113] In the HEMT 300 according to the present embodiment, the first depletion-forming layer 340a provided in the active region R1 can be formed to be thinner than the second depletion-forming layer 340b provided in the boundary region R3 between the active region R1 and the field region R2. Therefore, since the threshold voltage of the main transistor formed in the active region R1 can be lowered, a current-voltage characteristic curve with a peak eliminated therefrom can be obtained.

[0114] For example, when comparing Figure 5 The threshold voltage difference (ΔVth) and Figure 18B The data shown in FIG. 1 can be used to determine the etching depth corresponding to the threshold voltage difference (ΔVth) (i.e., the difference between the first thickness (t1) and the second thickness (t2)). When the first depletion-forming layer 340a provided in the active region R1 is formed to have a first thickness (t1) smaller than the second thickness (t2) based on the etching depth, a current-voltage characteristic curve with a peak removed therefrom can be obtained.

[0115] Figure 19 is a plan view of a HEMT 400 according to another example embodiment. Figure 20 HEMT 400 is along Figure 19 Hereinafter, differences from the above-described embodiment will be mainly described.

[0116] Reference Figure 19 and Figure 20 , the depletion-forming layer 340 may be provided to protrude from the active region R1 to the field region R2. The depletion-forming layer 340 may include a first depletion-forming layer 340a provided in the active region R1 and a second depletion-forming layer 340b provided in the boundary region R3 between the active region R1 and the field region R2. As described above, the first depletion-forming layer 340a provided in the active region R1 may have a thickness smaller than that of the second depletion-forming layer 340b provided in the boundary region R3 between the active region R1 and the field region R2.

[0117] The gate 450 is provided on the depletion forming layer 340. The gate 450 may be provided to protrude from the active region R1 to the field region R2. The gate 450 may include a first gate 451 provided in the active region R1 and a second gate 452 provided in the boundary region R3 between the active region R1 and the field region R2.

[0118] The first gate 451 and the second gate 452 may be provided to form a Schottky barrier with the depletion forming layer 340 thereunder. As described above, the first gate 451 and the second gate 452 may include materials having different work functions from each other. Specifically, the second gate 452 may include a material having a lower work function than that of the first gate 451. The first gate 451 and the second gate 452 may include, for example, a material having a work function of about 4.0 eV to about 6.0 eV. For example, the first gate 451 and the second gate 452 may include TiN, Ni, W, Mo, Pd, or Pt. However, the present disclosure is not limited thereto.

[0119] In the HEMT 400 according to this embodiment, because the first depletion-forming layer 340a provided in the active region R1 can be formed thinner than the second depletion-forming layer 340b provided in the boundary region R3 between the active region R1 and the field region R2, the threshold voltage of the main transistor formed in the active region R1 can be reduced. In addition, because the gate 450 includes the first gate 451 and the second gate 452, which are made of materials having different work functions, the threshold voltage of the edge transistor formed in the boundary region R3 between the active region R1 and the field region R2 can be increased. As a result, a current-voltage characteristic curve without a peak can be obtained.

[0120] Figure 21 is a plan view of a HEMT 500 according to another example embodiment. Figure 22 HEMT 500 is along Figure 21 A cross-sectional view taken along line AA', Figure 23 HEMT 500 is along Figure 21 A cross-sectional view taken along line BB'. Figure 24 It is the HEMT500 Figure 21 The cross-sectional view taken along line CC' is Figure 25 HEMT 500 is along Figure 21 A cross-sectional view taken along line D-D'.

[0121] Reference Figures 21 to 25 , the HEMT 500 includes a channel layer 510, a barrier layer 520 provided on the channel layer 510, a source 531 and a drain 532 provided on the barrier layer 520, a depletion-forming layer 540 provided on the barrier layer 520, and a gate 550 provided on the depletion-forming layer 540. Since the channel layer, the barrier layer, the source, and the drain have been described above, their description is omitted.

[0122] The depletion forming layer 540 is provided on the blocking layer 520, and the gate 550 is provided on the depletion forming layer 540. The depletion forming layer 540 and the gate 550 may be provided to surround the source 531.

[0123] The depletion-forming layer 540 may be provided to protrude from the active region R1 to the field region R2. The depletion-forming layer 540 may include a first depletion-forming layer 540a provided in the active region R1 and a second depletion-forming layer 540b provided in the boundary region R3 between the active region R1 and the field region R2. The first depletion-forming layer 540a may have a thickness different from that of the second depletion-forming layer 540b. Specifically, the first depletion-forming layer 540a provided in the active region R1 may have a first thickness (t1), and the second depletion-forming layer 540b provided in the boundary region R3 between the active region R1 and the field region R2 may have a second thickness (t2) greater than the first thickness (t1).

[0124] The gate 550 is provided on the depletion-forming layer 540. Like the depletion-forming layer 540, the gate 550 may be provided to protrude from the active region R1 to the field region R2. The gate 550 may include a material that forms a Schottky barrier with the depletion-forming layer 540 thereunder. For example, the gate 550 may include TiN, Ni, W, Mo, Pd, or Pt, but the present disclosure is not limited thereto.

[0125] In the HEMT 500 according to this embodiment, the first depletion-forming layer 540a provided in the active region R1 is formed to be thinner than the second depletion-forming layer 540b provided in the boundary region R3 between the active region R1 and the field region R2. Therefore, the threshold voltage of the main transistor formed in the active region R1 can be lowered, and a current-voltage characteristic curve without a peak can be obtained. In addition, because the depletion-forming layer 540 is provided so as to surround the source 531, the effects of the edge transistor formed in the boundary region between the active region R1 and the field region R2 can be more effectively limited and / or suppressed.

[0126] Figure 26 is a plan view of a HEMT 600 according to another example embodiment. Figure 27 It is a HEMT 600 along Figure 26 Hereinafter, differences from the above-described embodiment will be mainly described.

[0127] Reference Figure 26 and Figure 27 , a depletion forming layer 540 is provided on the blocking layer 520, and a gate 650 is provided on the depletion forming layer 540. The depletion forming layer 540 and the gate 650 may be provided to surround the source 531.

[0128] The depletion-forming layer 540 may be provided to protrude from the active region R1 to the field region R2. The depletion-forming layer 540 may include a first depletion-forming layer 540a provided in the active region R1 and a second depletion-forming layer 540b provided in the boundary region R3 between the active region R1 and the field region R2. As described above, the first depletion-forming layer 540a provided in the active region R1 may have a thickness smaller than that of the second depletion-forming layer 540b provided in the boundary region R3 between the active region R1 and the field region R2.

[0129] The gate 650 is provided on the depletion forming layer 540. Like the depletion forming layer 540, the gate 650 may be provided to protrude from the active region R1 to the field region R2. The gate 650 may include a first gate 651 provided in the active region R1 and a second gate 652 provided in the boundary region R3 between the active region R1 and the field region R2.

[0130] The first gate 651 and the second gate 652 may be provided to form a Schottky barrier with the depletion forming layer 540 therebelow. As described above, the first gate 651 and the second gate 652 may include materials having different work functions from each other. Specifically, the second gate 652 may include a material having a lower work function than that of the first gate 651. The first gate 651 and the second gate 652 may include, for example, a material having a work function of about 4.0 eV to about 6.0 eV. For example, the first gate 651 and the second gate 652 may include TiN, Ni, W, Mo, Pd, or Pt. However, the present disclosure is not limited thereto.

[0131] In the HEMT 600 according to this embodiment, because the first depletion-forming layer 540a provided in the active region R1 can be formed thinner than the second depletion-forming layer 540b provided in the boundary region R3 between the active region R1 and the field region R2, the threshold voltage of the main transistor formed in the active region R1 can be reduced. In addition, because the gate 650 includes the first gate 651 and the second gate 652, which include materials having different work functions, the threshold voltage of the edge transistor formed in the boundary region R3 between the active region R1 and the field region R2 can be increased. Because the depletion-forming layer 540 is provided to surround the source 531, the effect of the edge transistor formed in the boundary region between the active region R1 and the field region R2 can be more effectively limited and / or suppressed.

[0132] Figure 28 is a schematic diagram of an electronic device according to one embodiment.

[0133] Reference Figure 28 , the electronic device 1000 includes one or more electronic device components, including a processing circuit 1020 and a memory 1030 communicatively coupled together via a bus 1010 .

[0134] The processing circuit 1020 may be implemented by one or more instances of a processing circuit (such as hardware including logic circuits, a hardware / software combination such as a processor executing software, or a combination thereof). For example, the processing circuit 1020 may include a central processing unit (CPU), an application processor (AP), an arithmetic logic unit (ALU), a graphics processing unit (GPU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, or an application-specific integrated circuit, etc., but is not limited thereto. In some example embodiments, the memory 1030 may include a non-transitory computer-readable storage device storing an instruction program, such as a solid-state drive (SSD), and the processing circuit 1020 may be configured to execute the instruction program to implement the functions of the electronic device 1000.

[0135] In some example embodiments, the electronic device 1000 may include one or more additional components 1040 coupled to the bus 1010 , which may include, for example, a power supply, a light sensor, a light emitting device, any combination thereof, etc. In some example embodiments, one or more of the processing circuit 1020 , the memory 1030 , or the one or more additional components 1040 may include a HEMT according to any of the HEMTs described herein.

[0136] HEMTs according to example embodiments can be used in components requiring transistors, including radio frequency integrated circuits (RFICs) and RF devices using radio frequencies such as mobile communications and satellite communications, and power management integrated circuits (PMICs) and power semiconductor devices that control power. HEMTs according to example embodiments can be used in power semiconductor components such as emergency chargers for mobile phones, switching converters for servers for power, chargers for vehicles, light detection and ranging sensors (LiDAR) for vehicles, and robots.

[0137] Although the embodiments have been described above, these are merely examples and various modifications can be made thereto by one of ordinary skill in the art.

[0138] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope defined by the appended claims.

[0139] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2021-0064214 filed in the Korean Intellectual Property Office on May 18, 2021, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A high electron mobility transistor comprising an active region in which a channel is formed and a field region surrounding the active region, the high electron mobility transistor comprising: channel layer; a barrier layer on the channel layer and configured to induce a two-dimensional electron gas in the channel layer; a source electrode and a drain electrode on the barrier layer in the active region, the source electrode and the drain electrode being spaced apart from each other in a first direction; as well as a gate on the barrier layer, the gate protruding from the active region to the field region, wherein The gate includes a first gate and a second gate, The first gate is in the active region, The second gate is in a boundary region of the high electron mobility transistor between the active region and the field region, The first side wall and the second side wall of the second gate are opposite to each other in a second direction, and the second direction intersects the first direction. The first gate contacts the first sidewall of the second gate at a position above the active region, The work function of the second gate is different from the work function of the first gate, and The first gate contacts the second sidewall of the second gate.

2. The high electron mobility transistor according to claim 1, The material of the second gate has a work function lower than that of the material of the first gate.

3. The high electron mobility transistor according to claim 1, The first gate and the second gate include a material that forms a Schottky barrier with underlying layers.

4. The high electron mobility transistor according to claim 1 , further comprising: A depletion forming layer between the channel layer and the gate, wherein The depletion-forming layer is configured to form a depletion region in the two-dimensional electron gas.

5. The high electron mobility transistor according to claim 1, wherein the gate is between the source and the drain, and The gate is parallel to the source and the drain.

6. The high electron mobility transistor according to claim 1, The gate surrounds the source.

7. The high electron mobility transistor according to claim 4, The thickness of the depletion-forming layer in the active region is different from the thickness of the depletion-forming layer in the boundary region.

8. The high electron mobility transistor according to claim 7, The thickness of the depletion-forming layer in the active region is smaller than the thickness of the depletion-forming layer in the boundary region between the active region and the field region.

9. The high electron mobility transistor according to claim 7, The material of the second gate has a lower work function than the material of the first gate.

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