Method of forming a semiconductor memory element

Abstract

A method of forming a semiconductor memory device includes forming an upper electrode layer on a magnetic tunnel junction stack; forming a patterned buffer layer covering only a logic circuit region; forming a hard mask layer on the upper electrode layer and the patterned buffer layer; forming a patterned photoresist layer on the hard mask layer; and performing a first etch fabrication process to etch the hard mask layer and the upper electrode layer in a memory region not covered by the patterned photoresist layer, and to etch the hard mask layer, the patterned buffer layer, and the upper electrode layer in the logic circuit region, thereby forming an upper electrode on the magnetic tunnel junction stack in the memory region and a remaining upper electrode layer on the magnetic tunnel junction stack covering only the logic circuit region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor memory element and a method for manufacturing the same. Background Technology

[0002] The magnetoresistive (MR) effect is an effect caused by changing the resistance of a material by altering an external magnetic field. Physically, it is defined as the change in resistance obtained by dividing the resistance difference under no magnetic interference by the original resistance. The characteristic of giant magnetoresistive (GMR) materials exhibiting different resistances under different magnetization states can be used to fabricate magnetoresistive random access memory (MRAM) elements, which have the advantage of retaining stored data even when the element is not connected to a power source.

[0003] The aforementioned MR effect has also been applied in the field of magnetic field sensors, including but not limited to electronic compass components used in, for example, the Global Positioning System (GPS) of mobile phones to provide users with information about their location. Currently, various magnetic field sensor technologies have been widely developed in the market, such as anisotropic magnetoresistive (AMR) sensors, gas magnetoresistive (GMR) sensors, and magnetic tunneling junction (MTJ) sensors. However, most of these products still suffer from many drawbacks, such as high chip area, high cost, high power consumption, limited sensitivity, and susceptibility to temperature variations. Therefore, an improved device is still needed in this technological field to address the problems of existing technologies. Summary of the Invention

[0004] The main objective of this invention is to provide a semiconductor device and a method for manufacturing the same, so as to overcome the shortcomings and disadvantages of the prior art.

[0005] This invention provides a method for forming a semiconductor memory element, comprising: providing a substrate, the substrate including a memory region and a logic circuit region; forming a first interlayer dielectric layer on the substrate; forming a second interlayer dielectric layer on the first interlayer dielectric layer; forming at least one via in the second interlayer dielectric layer within the memory region; forming a magnetic tunneling junction stacked layer on the at least one via and the second interlayer dielectric layer; forming an upper electrode layer on the magnetic tunneling junction stacked layer; forming a patterned buffer layer covering only the logic circuit region; and forming a patterned buffer layer covering only the memory region. A hard mask layer is formed on the top electrode layer and the patterned buffer layer; a patterned photoresist layer is formed on the hard mask layer; and a first etching process is performed to etch the hard mask layer and the top electrode layer in the memory region that are not covered by the patterned photoresist layer, and to etch the hard mask layer, the patterned buffer layer and the top electrode layer in the logic circuit region, thereby forming a top electrode on the magnetic tunneling junction stack layer in the memory region and a remaining top electrode layer located on the magnetic tunneling junction stack layer and covering only the logic circuit region.

[0006] According to an embodiment of the present invention, the first interlayer dielectric layer includes an ultra-low dielectric constant dielectric layer.

[0007] According to an embodiment of the present invention, the method further includes: forming an etch stop layer located between the first interlayer dielectric layer and the second interlayer dielectric layer.

[0008] According to an embodiment of the present invention, the etch stop layer comprises a nitrogen-doped silicon carbide layer.

[0009] According to an embodiment of the present invention, the second interlayer dielectric layer is in direct contact with the etch stop layer.

[0010] According to an embodiment of the present invention, the second interlayer dielectric layer comprises a tetraethoxysilane oxide layer.

[0011] According to an embodiment of the present invention, the at least one through hole is a tungsten through hole.

[0012] According to an embodiment of the present invention, the thickness of the upper electrode is greater than the thickness of the remaining upper electrode layer located on the magnetic tunneling junction stack layer and covering only the logic circuit area.

[0013] According to an embodiment of the present invention, the upper electrode layer comprises titanium nitride, the patterned buffer layer is a silicon nitride layer, and the hard mask layer is a silicon oxide layer.

[0014] According to an embodiment of the present invention, after performing the first etching process, the method further includes:

[0015] A second etching process is performed to etch the magnetic tunneling junction stack layer and the second interlayer dielectric layer in the memory region that are not covered by the top electrode, while simultaneously etching the remaining top electrode layer, the magnetic tunneling junction stack layer and the second interlayer dielectric layer in the logic circuit region.

[0016] Another aspect of the present invention provides a method for forming a semiconductor memory element, comprising: providing a substrate, the substrate including a memory region and a logic circuit region; forming a first interlayer dielectric layer on the substrate; forming a second interlayer dielectric layer on the first interlayer dielectric layer; forming at least one via in the second interlayer dielectric layer within the memory region; forming a magnetic tunneling junction stack layer on the at least one via and the second interlayer dielectric layer; forming an upper electrode layer on the magnetic tunneling junction stack layer, wherein the upper electrode layer has a first thickness; and partially removing the upper electrode layer from the memory region, wherein the upper electrode layer has a second thickness in the memory region. The second thickness is less than the first thickness, thereby forming a step height at the interface between the memory region and the logic circuit region; forming a hard mask layer covering the upper electrode layer; forming a patterned photoresist layer on the hard mask layer; and performing a first etching process to etch the hard mask layer and the upper electrode layer not covered by the patterned photoresist layer in the memory region, and to etch the hard mask layer and the upper electrode layer in the logic circuit region, thereby forming an upper electrode on the magnetic tunneling junction stack layer in the memory region and a remaining upper electrode layer on the magnetic tunneling junction stack layer that only covers the logic circuit region.

[0017] According to an embodiment of the present invention, the first interlayer dielectric layer includes an ultra-low dielectric constant dielectric layer.

[0018] According to an embodiment of the present invention, the method further includes: forming an etch stop layer located between the first interlayer dielectric layer and the second interlayer dielectric layer.

[0019] According to an embodiment of the present invention, the etch stop layer comprises a nitrogen-doped silicon carbide layer.

[0020] According to an embodiment of the present invention, the second interlayer dielectric layer is in direct contact with the etch stop layer.

[0021] According to an embodiment of the present invention, the second interlayer dielectric layer comprises a tetraethoxysilane oxide layer.

[0022] According to an embodiment of the present invention, the at least one through hole is a tungsten through hole.

[0023] According to an embodiment of the present invention, the first thickness is between Å, and the second thickness is between Angstrom.

[0024] According to an embodiment of the present invention, the upper electrode layer comprises titanium nitride, and the hard mask layer is a silicon oxide layer.

[0025] According to an embodiment of the present invention, after performing the first etching process, the method further includes:

[0026] A second etching process is performed to etch the magnetic tunneling junction stack layer and the second interlayer dielectric layer in the memory region that are not covered by the top electrode, while simultaneously etching the remaining top electrode layer, the magnetic tunneling junction stack layer and the second interlayer dielectric layer in the logic circuit region. Attached Figure Description

[0027] Figures 1 to 7 This is a schematic diagram illustrating a method for forming a semiconductor memory element according to an embodiment of the present invention;

[0028] Figures 8 to 14 This is a schematic diagram illustrating a method for forming a semiconductor memory element according to another embodiment of the present invention.

[0029] Explanation of main component symbols

[0030] 100 base

[0031] 110 First interlayer dielectric layer

[0032] 112, 114 Metallic interconnects

[0033] 120 Second interlayer dielectric layer

[0034] 122 Through Hole

[0035] 130 Etching Stop Layer

[0036] 140 magnetic tunneling junction stack

[0037] 141 Lower electrode layer

[0038] 142 Reference Layer

[0039] 143 Tunneling Layer

[0040] 144 Free Layer

[0041] 145 Upper Cover Layer

[0042] 150 Upper electrode layer

[0043] 150a upper electrode

[0044] 150b Remaining upper electrode layer

[0045] 160 Patterned Buffer Layer

[0046] 170 Hard Mask Layer

[0047] 180 protective layer

[0048] LA Logic Circuit Area

[0049] MA memory area

[0050] PR patterned photoresist layer

[0051] ST memory unit

[0052] t1 First Thickness

[0053] t2 Second thickness

[0054] t3 Third Thickness Detailed Implementation

[0055] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and which are depicted in a manner that describes specific examples in which the embodiments may be practiced. The embodiments described below are given sufficient detail to enable those skilled in the art to implement them.

[0056] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0057] Please see Figures 1 to 7 This is a schematic diagram illustrating a method for forming a semiconductor memory element according to an embodiment of the present invention. Figure 1 As shown, a substrate 100 is first provided, for example, a silicon substrate, but not limited thereto. According to an embodiment of the present invention, the substrate 100 includes a memory region MA and a logic circuit region LA. Next, a first interlayer dielectric layer 110 is formed on the substrate 100. According to an embodiment of the present invention, the first interlayer dielectric layer 110 may include an ultra-low dielectric constant (ULK) dielectric layer, for example, the dielectric constant of the ULK dielectric layer may be less than 2.5, but is not limited thereto. According to an embodiment of the present invention, metal interconnect layers 112 and 114 may be formed in the first interlayer dielectric layer 110, wherein the metal interconnect layer 112 is located in the memory region MA, and the metal interconnect layer 114 is located in the logic circuit region LA.

[0058] Next, a second interlayer dielectric layer 120 can be deposited on the first interlayer dielectric layer 110 using chemical vapor deposition (CVD). According to embodiments of the present invention, the second interlayer dielectric layer 120 may, for example, comprise a tetraethoxysilane (TEOS) oxide layer, but is not limited thereto. According to embodiments of the present invention, an etch stop layer 130 may be further formed between the first interlayer dielectric layer and the second interlayer dielectric layer. According to embodiments of the present invention, the etch stop layer 130 may, for example, comprise a nitrogen-doped silicon carbide (NDC) layer. According to embodiments of the present invention, the second interlayer dielectric layer 120 is in direct contact with the etch stop layer 130.

[0059] Then, at least one via 122 is formed in the second interlayer dielectric layer 120 within the memory region MA. According to an embodiment of the invention, the via 122 can be a tungsten via. According to an embodiment of the invention, the via 122 is electrically connected to the underlying metal interconnect layer 112. The formation of the via 122 is a well-known technique, and its details are not described further. For example, a hole can be formed in the second interlayer dielectric layer 120 and the etch stop layer 130 using photolithography and etching processes, then the hole can be filled with a tungsten metal layer, and finally, excess tungsten metal layer outside the hole can be removed using a chemical mechanical polishing (CMP) process.

[0060] like Figure 2 As shown, a magnetic tunnel junction (MTJ) stack 140 is then formed on the via 122 and the interlayer dielectric layer 120. According to an embodiment of the present invention, for example, the MTJ stack 140 may include a lower electrode layer 141, a reference layer 142, a tunnel barrier 143, a free layer 144, and a capping layer 145. The reference layer 142 and the free layer 144 may be made of ferromagnetic materials, and the tunnel barrier 143 may be made of an insulating material, but is not limited thereto. Next, an upper electrode layer 150 is formed on the MTJ stack 140. According to an embodiment of the present invention, the upper electrode layer 150 may include titanium nitride, but is not limited thereto.

[0061] like Figure 3 As shown, a patterned buffer layer 160 is then formed that covers only the logic circuit region LA. According to an embodiment of the invention, the patterned buffer layer 160 may be a silicon nitride layer, but is not limited thereto. At this time, the upper electrode layer 150 within the memory region MA is exposed.

[0062] like Figure 4As shown, a hard mask layer 170 is then formed on the upper electrode layer 150 and the patterned buffer layer 160. According to an embodiment of the present invention, the hard mask layer 170 may be a silicon oxide layer, but is not limited thereto.

[0063] like Figure 5 As shown, a patterned photoresist layer PR is then formed on the hard mask layer 170. According to an embodiment of the invention, the patterned photoresist layer PR is formed only on the hard mask layer 170 within the memory region MA. According to an embodiment of the invention, the patterned photoresist layer PR defines the location and pattern of the memory cells predetermined to be formed on the via 122.

[0064] like Figure 6 As shown, a first etching process, such as an anisotropic dry etching process, is performed to etch the hard mask layer 170 and the upper electrode layer 150 in the memory region MA that are not covered by the patterned photoresist layer PR, while simultaneously etching the hard mask layer 170, the patterned buffer layer 160, and the upper electrode layer 150 in the logic circuit region LA, thereby forming an upper electrode 150a on the magnetic tunneling junction stack layer 140 in the memory region MA and a remaining upper electrode layer 150b located on the magnetic tunneling junction stack layer 140 that only covers the logic circuit region.

[0065] According to an embodiment of the present invention, the thickness of the upper electrode 150a is greater than the thickness of the remaining upper electrode layer 150b located on the magnetic tunneling junction stack 140 and covering only the logic circuit region LA. According to an embodiment of the present invention, for example, the thickness of the remaining upper electrode layer 150b is approximately 600 angstroms.

[0066] like Figure 7 As shown, after the first etching process, a second etching process, such as ion beam etching, is performed to etch the magnetic tunneling junction stack 140 and the second interlayer dielectric layer 120 in the memory region MA that are not covered by the top electrode 150a. Simultaneously, the remaining top electrode layer 150b, the magnetic tunneling junction stack 140, and the second interlayer dielectric layer 120 in the logic circuit region LA are etched, thereby forming a memory cell ST in the memory region MA. Next, a protective layer 180 can be deposited conformally on the memory cell ST; for example, the protective layer 180 may be a silicon nitride layer.

[0067] The present invention utilizes the remaining upper electrode layer 150b formed on the magnetic tunneling junction stack layer 140 and covering only the logic circuit region to reduce the consumption of the second interlayer dielectric layer 120 in the second etching process. Therefore, it can avoid the excessive thickness difference between the second interlayer dielectric layer 120 in the logic circuit region LA and the second interlayer dielectric layer 120 in the memory region MA after the second etching process is completed.

[0068] Please see Figures 8 to 14This is a schematic diagram illustrating a method for forming a semiconductor memory element according to another embodiment of the present invention. Figure 8 As shown, a substrate 100 is also provided, for example, a silicon substrate, but not limited thereto. According to an embodiment of the present invention, the substrate 100 includes a memory region MA and a logic circuit region LA. A first interlayer dielectric layer 110 is then formed on the substrate 100. According to an embodiment of the present invention, the first interlayer dielectric layer 110 may include an ultra-low dielectric constant (ULK) dielectric layer, for example, the dielectric constant of the ULK dielectric layer may be less than 2.5, but is not limited thereto. According to an embodiment of the present invention, metal interconnect layers 112 and 114 may be formed in the first interlayer dielectric layer 110, wherein the metal interconnect layer 112 is located in the memory region MA, and the metal interconnect layer 114 is located in the logic circuit region LA.

[0069] Next, a second interlayer dielectric layer 120 can be deposited on the first interlayer dielectric layer 110 using chemical vapor deposition. According to an embodiment of the invention, the second interlayer dielectric layer 120 may, for example, comprise a tetraethoxysilane (TEOS) oxide layer, but is not limited thereto. According to an embodiment of the invention, an etch stop layer 130 may be formed between the first interlayer dielectric layer and the second interlayer dielectric layer. According to an embodiment of the invention, the etch stop layer 130 may, for example, comprise a nitrogen-doped silicon carbide (NDC) layer. According to an embodiment of the invention, the second interlayer dielectric layer 120 is in direct contact with the etch stop layer 130.

[0070] Then, at least one via 122 is formed in the second interlayer dielectric layer 120 within the memory region MA. According to an embodiment of the invention, the via 122 can be a tungsten via. According to an embodiment of the invention, the via 122 is electrically connected to the underlying metal interconnect layer 112. The formation of the via 122 is a well-known technique, and its details are not described further. For example, a hole can be formed in the second interlayer dielectric layer 120 and the etch stop layer 130 using photolithography and etching processes, then the hole can be filled with a tungsten metal layer, and finally, excess tungsten metal layer outside the hole can be removed using a chemical mechanical polishing (CMP) process.

[0071] like Figure 9As shown, a magnetic tunneling junction (MTJ) stacked layer 140 is then formed on the via 122 and the interlayer dielectric layer 120. According to an embodiment of the present invention, for example, the MTJ stacked layer 140 may include a lower electrode layer 141, a reference layer 142, a tunneling layer 143, a free layer 144, and a top cap layer 145, wherein the reference layer 142 and the free layer 144 may be made of ferromagnetic materials, and the tunneling layer 143 may be made of insulating materials, but is not limited thereto. Next, an upper electrode layer 150 is formed on the MTJ stacked layer 140. According to an embodiment of the present invention, the upper electrode layer 150 may include titanium nitride, but is not limited thereto. Then, an upper electrode layer 150 is formed on the MTJ stacked layer 140, wherein the upper electrode layer 150 has a first thickness t1. For example, the first thickness t1 is between... Angles, for example, about 1000 angstroms, but not limited to this.

[0072] like Figure 10 As shown, photolithography and etching processes are then performed to partially remove the upper electrode layer 150 from the memory region MA. The upper electrode layer 150 has a second thickness t2 in the memory region MA, where the second thickness t2 is less than the first thickness t1, thereby forming a step height H at the interface between the memory region MA and the logic circuit region LA. For example, the second thickness t1 is between... Angles, for example, about 600 angstroms, but not limited to this.

[0073] like Figure 11 As shown, a hard mask layer 170 is then formed covering the upper electrode layer 150. According to an embodiment of the present invention, the hard mask layer 170 may be a silicon oxide layer, but is not limited thereto.

[0074] like Figure 12 As shown, a patterned photoresist layer PR is formed on the hard mask layer 170. According to an embodiment of the present invention, the patterned photoresist layer PR is formed only on the hard mask layer 170 within the memory region MA. According to an embodiment of the present invention, the patterned photoresist layer PR defines the location and pattern of the memory cells predetermined to be formed on the via 122.

[0075] like Figure 13As shown, a first etching process, such as an anisotropic dry etching process, is performed to etch the hard mask layer 170 and the upper electrode layer 150 that are not covered by the patterned photoresist layer PR in the memory region MA, while simultaneously etching the hard mask layer 170 and the upper electrode layer 150 in the logic circuit region LA, thereby forming an upper electrode 150a on the magnetic tunneling junction stack layer 140 in the memory region MA and a remaining upper electrode layer 150b on the magnetic tunneling junction stack layer 140 that covers only the logic circuit region LA. According to an embodiment of the present invention, the remaining upper electrode layer 150b has a third thickness t3, wherein the third thickness t3 is less than or equal to the first thickness t1.

[0076] like Figure 14 As shown, after the first etching process, a second etching process, such as ion beam etching, is performed to etch the magnetic tunneling junction stack 140 and the second interlayer dielectric layer 120 in the memory region MA that are not covered by the top electrode 150a. Simultaneously, the remaining top electrode layer 150b, the magnetic tunneling junction stack 140, and the second interlayer dielectric layer 120 in the logic circuit region LA are etched, thereby forming a memory cell ST in the memory region MA. Next, a protective layer 180 can be deposited conformally on the memory cell ST; for example, the protective layer 180 may be a silicon nitride layer.

[0077] The present invention utilizes a relatively thick remaining upper electrode layer 150b formed on the logic circuit region to reduce the consumption of the second interlayer dielectric layer 120 in the second etching process. Therefore, it can avoid the excessive thickness difference between the second interlayer dielectric layer 120 in the logic circuit region LA and the second interlayer dielectric layer 120 in the memory region MA after the second etching process is completed.

[0078] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for forming a semiconductor memory element, comprising: A substrate is provided, the substrate comprising a memory area and a logic circuit area; A first interlayer dielectric layer is formed on the substrate; A second interlayer dielectric layer is formed on the first interlayer dielectric layer; At least one via is formed in the second interlayer dielectric layer within the memory region; A magnetic tunneling junction stack layer is formed on the at least one via and the second interlayer dielectric layer; An upper electrode layer is formed on the magnetic tunneling junction stack layer; Form a patterned buffer layer that only covers the logic circuit area; A hard mask layer is formed on the upper electrode layer and the patterned buffer layer; A patterned photoresist layer is formed on the hard mask layer; A first etching process is performed to etch the hard mask layer and the upper electrode layer in the memory region that are not covered by the patterned photoresist layer, and to etch the hard mask layer, the patterned buffer layer and the upper electrode layer in the logic circuit region, thereby forming an upper electrode on the magnetic tunneling junction stack layer in the memory region and a remaining upper electrode layer located on the magnetic tunneling junction stack layer that only covers the logic circuit region; After the first etching process, a second etching process is performed to etch the magnetic tunneling junction stack layer and the second interlayer dielectric layer in the memory region that are not covered by the top electrode, while simultaneously etching the remaining top electrode layer, the magnetic tunneling junction stack layer and the second interlayer dielectric layer in the logic circuit region.

2. The method according to claim 1, wherein, The first interlayer dielectric layer includes an ultra-low dielectric constant dielectric layer.

3. The method according to claim 1, wherein, Also includes: An etch stop layer is formed between the first interlayer dielectric layer and the second interlayer dielectric layer.

4. The method according to claim 3, wherein, The etch stop layer comprises a nitrogen-doped silicon carbide layer.

5. The method according to claim 4, wherein, The second interlayer dielectric layer is in direct contact with the etch stop layer.

6. The method according to claim 1, wherein, The second interlayer dielectric layer comprises a tetraethoxysilane oxide layer.

7. The method according to claim 1, wherein, The at least one through hole is a tungsten through hole.

8. The method according to claim 1, wherein, The thickness of the upper electrode is greater than the thickness of the remaining upper electrode layer located on the magnetic tunneling junction stack layer and covering only the logic circuit area.

9. The method according to claim 1, wherein, The upper electrode layer comprises titanium nitride, the patterned buffer layer is a silicon nitride layer, and the hard mask layer is a silicon oxide layer.

10. A method of forming a semiconductor memory element, comprising: A substrate is provided, the substrate comprising a memory area and a logic circuit area; A first interlayer dielectric layer is formed on the substrate; A second interlayer dielectric layer is formed on the first interlayer dielectric layer; At least one via is formed in the second interlayer dielectric layer within the memory region; A magnetic tunneling junction stack layer is formed on the at least one via and the second interlayer dielectric layer; An upper electrode layer is formed on the magnetic tunneling junction stack, wherein, The upper electrode layer has a first thickness; The upper electrode layer is partially removed from the memory region, wherein the upper electrode layer has a second thickness in the memory region, wherein the second thickness is less than the first thickness, thereby forming a step height at the interface between the memory region and the logic circuit region; Form a hard mask layer covering the upper electrode layer; A patterned photoresist layer is formed on the hard mask layer; A first etching process is performed to etch the hard mask layer and the upper electrode layer that are not covered by the patterned photoresist layer in the memory region, and to etch the hard mask layer and the upper electrode layer in the logic circuit region, thereby forming an upper electrode on the magnetic tunneling junction stack layer in the memory region and a remaining upper electrode layer on the magnetic tunneling junction stack layer that only covers the logic circuit region. as well as After the first etching process, a second etching process is performed to etch the magnetic tunneling junction stack layer and the second interlayer dielectric layer in the memory region that are not covered by the top electrode, while simultaneously etching the remaining top electrode layer, the magnetic tunneling junction stack layer and the second interlayer dielectric layer in the logic circuit region.

11. The method according to claim 10, wherein, The first interlayer dielectric layer includes an ultra-low dielectric constant dielectric layer.

12. The method according to claim 10, wherein, Also includes: An etch stop layer is located between the first interlayer dielectric layer and the second interlayer dielectric layer.

13. The method according to claim 12, wherein, The etch stop layer comprises a nitrogen-doped silicon carbide layer.

14. The method according to claim 13, wherein, The second interlayer dielectric layer is in direct contact with the etch stop layer.

15. The method according to claim 10, wherein, The second interlayer dielectric layer comprises a tetraethoxysilane oxide layer.

16. The method of claim 10, wherein, The at least one through hole is a tungsten through hole.

17. The method according to claim 10, wherein, The first thickness is between Å, and the second thickness is between Angstrom.

18. The method according to claim 10, wherein, The upper electrode layer comprises titanium nitride, and the hard mask layer is a silicon oxide layer.

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