single-ended receiver

Abstract

A single-ended receiver includes a current-mode logic circuit, a differential-to-single-ended amplifier, and a voltage detector. The current-mode logic circuit is configured to receive an input signal and a reference voltage value, and to output a first output signal. The differential-to-single-ended amplifier is coupled to the current-mode logic circuit, and is configured to receive the first output signal and to output a second output signal, wherein an internal signal of the differential-to-single-ended amplifier is generated based on the first output signal, and the second output signal is generated based on the internal signal of the differential-to-single-ended amplifier. The voltage detector is coupled to the differential-to-single-ended amplifier, and is configured to output a control signal to the differential-to-single-ended amplifier based on the reference voltage value. The differential-to-single-ended amplifier is further configured to adjust a voltage value of the internal signal of the differential-to-single-ended amplifier based on the control signal, such that a duty cycle of the second output signal is adjusted. The present implementation allows the duty cycle of the output signal to be the same or similar to the duty cycle of the input signal.

Description

TECHNICAL FIELD

[0001] Embodiments described herein relate to a single-ended receiver, and more particularly, to a single-ended receiver with improved duty cycle at different input bias levels. BACKGROUND

[0002] The reference voltage value can be adjusted in different applications. In a single-ended receiver, when transmitting from a current-mode logic circuit to a differential-to-single-ended amplifier, the duty cycle of the input signal is susceptible to the reference voltage value. Therefore, how to maintain the voltage value of the input cycle so that the threshold value of the output signal is not lost is a problem to be solved. SUMMARY

[0003] Some embodiments described herein relate to a single-ended receiver, comprising a current-mode logic circuit, a differential-to-single-ended amplifier, and a voltage detector. The current-mode logic circuit is configured to receive an input signal and a reference voltage value, and output a first output signal. The differential-to-single-ended amplifier is coupled to the current-mode logic circuit and configured to receive the first output signal and output a second output signal, wherein a differential-to-single-ended amplifier internal signal is generated according to the first output signal, and the second output signal is generated according to the differential-to-single-ended amplifier internal signal. The voltage detector is coupled to the differential-to-single-ended amplifier and configured to output a control signal to the differential-to-single-ended amplifier according to the reference voltage value. The differential-to-single-ended amplifier is further configured to adjust a voltage value of the differential-to-single-ended amplifier internal signal according to the control signal, so that a duty cycle of the second output signal is adjusted.

[0004] In some embodiments, when the reference voltage value is higher than a standard reference voltage value, the differential-to-single-ended amplifier is configured to decrease the voltage value of the differential-to-single-ended amplifier internal signal via a first node, and when the reference voltage value is lower than the standard reference voltage value, the differential-to-single-ended amplifier is configured to increase the voltage value of the differential-to-single-ended amplifier internal signal via a second node.

[0005] In some embodiments, the differential-to-single-ended amplifier comprises: a differential pair circuit configured to receive the first output signal; a first control circuit; a second control circuit coupled to an output terminal; a differential pair circuit; and a current mirror circuit comprising: a first sub-current mirror circuit coupled to the first control circuit and the differential pair circuit via a first node; and a second sub-current mirror circuit coupled to the second control circuit and the differential pair circuit via a second node.

[0006] In some embodiments, wherein when the reference voltage value is higher than a standard reference voltage value, the first control circuit is turned on and the second control circuit is not turned on to decrease the voltage value of the differential to single-ended amplifier internal signal via the first node, and when the reference voltage value is lower than the standard reference voltage value, the first control circuit is not turned on and the second control circuit is turned on to increase the voltage value of the differential to single-ended amplifier internal signal via the second node.

[0007] In some embodiments, wherein the first control circuit comprises: a first sub-control circuit, wherein the first sub-control circuit comprises: a first transistor and a second transistor in series with each other, wherein when the reference voltage value is higher than the standard reference voltage value, the first transistor is turned on and the second transistor is used to decrease the voltage value of the differential to single-ended amplifier internal signal via the first node.

[0008] In some embodiments, wherein the second control circuit comprises: a second sub-control circuit, wherein the second sub-control circuit comprises: a first transistor and a second transistor in series with each other, wherein when the reference voltage value is lower than the standard reference voltage value, the first transistor is turned on and the second transistor is used to increase the voltage value of the differential to single-ended amplifier internal signal via the second node.

[0009] In some embodiments, wherein a control terminal of the first transistor is used to receive the control signal.

[0010] In some embodiments, wherein the voltage detector is further used to output the control signal according to a voltage difference between the reference voltage value and the standard reference voltage value.

[0011] In some embodiments, wherein the second control circuit comprises a plurality of first sub-control circuits in parallel with each other, wherein when the reference voltage value is lower than a standard reference voltage value, a number of the first sub-control circuits is turned on, wherein when a voltage difference between the reference voltage value and the standard reference voltage value increases, the number increases.

[0012] In some embodiments, wherein the voltage detector further comprises a table, and the number is determined according to the table. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more obvious and easy to understand, the following is a description of the drawings:

[0014] Figure 1 is a schematic diagram of a single-ended receiver according to some embodiments of the present disclosure;

[0015] Figure 2 is a schematic diagram of a single-ended receiver according to some embodiments of the present disclosure;

[0016] Figure 3 is a diagram illustrating a relationship between a voltage difference and an adjusted voltage difference of an output signal according to some embodiments of the present disclosure; and

[0017] Figure 4 is a diagram illustrating another relationship between a voltage difference and an adjusted voltage difference of an output signal according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0018] As used herein, the word "coupled" can also mean "electrically coupled", and the word "connected" can also mean "electrically connected". "Coupled" and "connected" can also mean that two or more elements are in either physical or electrical contact with one another.

[0019] Referring to Figure 1 . Figure 1 is a diagram illustrating a single-ended receiver 100 according to some embodiments of the present disclosure. The single-ended receiver 100 includes a current-mode logic circuit 110, a differential-to-single-ended amplifier 130, and a voltage detector 150. In terms of connection, the current-mode logic circuit 110 is coupled to the differential-to-single-ended amplifier 130, and the differential-to-single-ended amplifier 130 is coupled to the voltage detector 150. As Figure 1 illustrated, the single-ended receiver is for illustrative purposes only, and embodiments of the present disclosure are not limited thereto.

[0020] In terms of operation, the current-mode logic circuit 110 receives an input signal SI and a reference voltage value VREF, and outputs an output signal SO1 according to the input signal SI and the reference voltage value VREF. The voltage detector 150 receives the reference voltage value VREF and outputs a control signal SC according to the reference voltage value VREF. The signal amplifier 130 receives the output signal SO1 and the control signal SC, and outputs an output signal SO2 according to the output signal SO1 and the control signal SC.

[0021] Referring to Figure 2 . Figure 2 is a diagram illustrating a single-ended receiver 100 according to some embodiments of the present disclosure.

[0022] The differential-to-single-ended amplifier 130 is also used to adjust a voltage value of a differential-to-single-ended amplifier internal signal SIN according to the control signal SC, so that a duty cycle of the output signal SO2 is adjusted to be close to the input signal SI. The differential-to-single-ended amplifier internal signal SIN is generated according to the output signal SO1, and the output signal SO2 is generated according to the differential-to-single-ended amplifier internal signal SIN.

[0023] In some embodiments, when the reference voltage value VREF is higher than the standard reference voltage value, the differential-to-single-ended amplifier 130 is also used to reduce the voltage value of the internal signal SIN of the differential-to-single-ended amplifier via node SO1_H. On the other hand, when the reference voltage value VREF is lower than the standard reference voltage value, the differential-to-single-ended amplifier 130 is used to increase the internal signal SIN of the differential-to-single-ended amplifier via node SO1_L.

[0024] like Figure 2 As illustrated, the differential-to-single-ended amplifier 130 includes a differential pair circuit 136, a control circuit 132A, a control circuit 132B, and a current mirror circuit 134. The current mirror circuit 134 includes sub-current mirror circuits 134A and 134B. In terms of connections, control circuit 132A is connected to current mirror circuit 134A, control circuit 132B is connected to sub-current mirror circuit 134B, and sub-current mirror circuits 134A and 134B are connected to the differential pair circuit 136. Control circuit 132B is coupled to the output terminal OT.

[0025] Differential pair circuit 136 includes transistors T9, T10, T11, T12, T13, T15, and T17. Sub-current mirror circuit 134A includes transistors T14 and T16. Sub-current mirror circuit 134B includes transistors T18 and T19. Control circuit 132A includes transistors T1, T2, T5, and T6. Control circuit 132B includes transistors T3, T4, T7, and T8.

[0026] In terms of operation, the differential pair circuit 136 is used to receive the output signal SO1. In some embodiments, the differential pair circuit 136 receives the output signal SO1 from the control terminals of transistors T11 and T12.

[0027] When the reference voltage VREF is lower than the standard reference voltage, control circuit 132A is not turned on while control circuit 132B is turned on, causing the voltage value of the differential signal SIN to the internal signal of the single-ended amplifier to increase via node SO1_L. Specifically, because the voltage value of node SO1_L increases when control circuit 132B is turned on, the voltage value of the differential signal SIN to the internal signal of the single-ended amplifier also increases.

[0028] On the other hand, when the reference voltage value VREF is higher than the standard reference voltage value, control circuit 132A is turned on while control circuit 132B is turned off, so that the voltage value of the differential signal SIN to the single-ended amplifier decreases via node SO1_H. Specifically, since the voltage value of node SO1_H increases when control circuit 132A is turned on, the voltage value of the differential signal SIN to the single-ended amplifier decreases accordingly.

[0029] In some embodiments, the control circuit 132A includes a sub-control circuit 133A1 and the control circuit 132B includes a sub-control circuit 133B1. The sub-control circuit 133A1 includes a transistor T1 and a transistor T2. The transistor T1 and the transistor T2 are in series with each other. The sub-control circuit 133B1 includes a transistor T3 and a transistor T4. The transistor T3 and the transistor T4 are in series with each other.

[0030] When the reference voltage value VREF is higher than the standard reference voltage value, the transistor T1 is turned on and the transistor T2 is used to pull up the voltage value of the node SO1_H. The transistor T3 and the transistor T4 are not turned on.

[0031] On the other hand, when the reference voltage value VREF is lower than the standard reference voltage value, the transistor T3 is turned on and the transistor T4 is used to pull up the voltage value of the node SO1_L. The transistor T1 is not turned on.

[0032] In some embodiments, the control terminal of the transistor T1 and the control terminal of the transistor T3 are used to receive a control signal SC to be turned on or not to be turned on.

[0033] In some embodiments, the control circuit 132A further includes a sub-control circuit 133A2 and the control circuit 132B further includes a sub-control circuit 133B2. The sub-control circuit 133A1 and the sub-control circuit 133A2 are in parallel with each other. The sub-control circuit 133B1 and the sub-control circuit 133B2 are in parallel with each other.

[0034] The sub-control circuit 133A2 includes a transistor T5 and a transistor T6. The sub-control circuit 133B2 includes a transistor T7 and a transistor T8.

[0035] In some embodiments, the voltage detector 150 is further used to output the control signal SC according to a voltage difference between the reference voltage value VREF and the standard reference voltage value.

[0036] In some embodiments, when the voltage difference increases, the number of the sub-control circuits that are turned on increases.

[0037] In some embodiments, the voltage detector 150 further includes a table. In some embodiments, when the voltage difference is lower than a first voltage difference threshold and the reference voltage value VREF is higher than the standard reference voltage value, the sub-control circuit 133A1 is turned on and the sub-control circuit 133A2, the sub-control circuit 133B1 and the sub-control circuit 133B2 are not turned on.

[0038] When the voltage difference is not lower than the first voltage difference threshold and is lower than a second voltage difference threshold and the reference voltage value VREF is higher than the standard reference voltage value, the sub-control circuit 133A1 and the sub-control circuit 133A2 are turned on and the sub-control circuit 133B1 and the sub-control circuit 133B2 are not turned on.

[0039] In some embodiments, when the voltage difference is lower than the first voltage difference threshold and the reference voltage value VREF is lower than the standard reference voltage value, the sub-control circuit 133B1 is turned on, and the sub-control circuit 133B2, the sub-control circuit 133A1 and the sub-control circuit 133A2 are not turned on.

[0040] When the voltage difference is not lower than the first voltage difference threshold and is lower than the second voltage difference threshold and the reference voltage value VREF is lower than the standard reference voltage value, the sub-control circuit 133B1 and the sub-control circuit 133B2 are turned on, and the sub-control circuit 133A1 and the sub-control circuit 133A2 are not turned on.

[0041] The more sub-control circuits are turned on, the more the voltage value of the node SO1_H or SO1_L increases.

[0042] The number of turned-on sub-control circuits is controlled by the control signal SC.

[0043] Referring to Figure 3 . Figure 3 is a graph 300 illustrating the relationship between the voltage difference and the adjusted voltage difference of the node SO1_H or SO1_L according to some embodiments of the present disclosure. VD is the voltage difference between the reference voltage value VREF and the standard reference voltage value. VS is the adjusted voltage difference of the node SO1_H or SO1_L. As Figure 3 illustrated, the voltage difference VD and the adjusted voltage difference VS are in a proportional relationship.

[0044] Referring to Figure 4 . Figure 4 is another graph 400 illustrating the relationship between the voltage difference and the adjusted voltage difference of the node SO1_H or SO1_L according to some embodiments of the present disclosure. As Figure 4 illustrated, the greater the voltage difference VD, the greater the adjusted voltage difference VS.

[0045] In some embodiments, the single-ended receiver 100 is located at the receiver of the I / O end of the DRAM memory.

[0046] It is noted that the P-type and N-type transistors are only illustrative in the above embodiments, and other transistors are within the scope of the present disclosure.

[0047] In summary, the embodiments of the present disclosure provide a single-ended receiver, when adjusting the voltage value of the node SO1_H or SO1_L, the voltage value of the differential-to-single-ended amplifier internal signal SIN also increases or decreases, so that the duty cycle of the output signal SO2 and the duty cycle of the input signal SI are the same or similar.

[0048] In addition, the above-described examples include exemplary steps that are performed in a particular order, but the steps do not have to be performed in the order shown. Performing the steps in a different order is within the scope of the present disclosure. Additional, substitute, alter, order, and / or omit steps can be included within the spirit and scope of embodiments of the present disclosure. The following claims define the scope of the disclosure.

[0049] While the present disclosure has been disclosed in connection with the embodiments presented, it should be understood that certain modifications can be made to the described embodiments and additional implementations can be implemented without departing from the spirit and scope of the disclosure, and that the terms disclosed herein are meant to be interpreted in a descriptive sense and not a limiting sense. Changes in or additions to the described embodiments can occur without departing from the scope of the present disclosure. The terms used herein are not meant to be interpreted as limiting, but are to be interpreted in a descriptive sense.

[0050] SYMBOL DESCRIPTION

[0051] 100: single-ended receiver

[0052] 110: current-mode logic circuit

[0053] 130: differential-to-single-ended amplifier

[0054] 150: voltage detector

[0055] SI: input signal

[0056] VREF: reference voltage value

[0057] SO1: output signal

[0058] SC: control signal

[0059] SO2: output signal

[0060] 132A, 132B: control circuit

[0061] 133A1, 133A2: sub-control circuit

[0062] 133B1, 133B2: sub-control circuit

[0063] 134: current mirror circuit

[0064] 134A, 134B: sub-current mirror circuit

[0065] 136: differential pair circuit

[0066] OT: output terminal

[0067] SIN: differential-to-single-ended amplifier internal signal

[0068] SO1_H, SO1_L: node

[0069] T1, T2, T3, T4, T5, T6, T7, T8, T9, T10: transistor

[0070] T11, T12, T13, T14, T15: transistors

[0071] T16, T17, T18, T19: transistors

[0072] 300: relationship chart

[0073] 400: relationship chart

[0074] VS: adjustment voltage difference

[0075] VD: voltage difference.

Claims

1. A single-ended receiver, characterized by Comprising: a current mode logic circuit to receive an input signal and a reference voltage value, and to output a first output signal; a differential to single ended amplifier coupled to the current mode logic circuit, and to receive the first output signal and output a second output signal, wherein a differential to single ended amplifier internal signal is generated according to the first output signal, and the second output signal is generated according to the differential to single ended amplifier internal signal; and a voltage detector coupled to the differential to single ended amplifier, and to output a control signal to the differential to single ended amplifier according to the reference voltage value, wherein the differential to single ended amplifier is further to adjust a voltage value of the differential to single ended amplifier internal signal according to the control signal, such that a duty cycle of the second output signal is adjusted, 2. A single-ended receiver, characterized by wherein the differential to single ended amplifier is to decrease the voltage value of the differential to single ended amplifier internal signal via a first node when the reference voltage value is higher than a standard reference voltage value, and to increase the voltage value of the differential to single ended amplifier internal signal via a second node when the reference voltage value is lower than the standard reference voltage value. Comprising: a current mode logic circuit to receive an input signal and a reference voltage value, and to output a first output signal; a differential to single ended amplifier coupled to the current mode logic circuit, and to receive the first output signal and output a second output signal, wherein a differential to single ended amplifier internal signal is generated according to the first output signal, and the second output signal is generated according to the differential to single ended amplifier internal signal; and a voltage detector coupled to the differential to single ended amplifier, and to output a control signal to the differential to single ended amplifier according to the reference voltage value, wherein the differential to single ended amplifier is further to adjust a voltage value of the differential to single ended amplifier internal signal according to the control signal, such that a duty cycle of the second output signal is adjusted, wherein the differential to single ended amplifier comprises: a differential pair circuit to receive the first output signal; a first control circuit; a second control circuit coupled to an output terminal; a differential pair circuit; and a current mirror circuit comprising: a first sub current mirror circuit coupled to the first control circuit and the differential pair circuit via a first node; and 3. The single-ended receiver of claim 2, wherein, a second sub current mirror circuit coupled to the second control circuit and the differential pair circuit via a second node.

4. The single-ended receiver of claim 2, wherein, wherein the first control circuit is turned on and the second control circuit is not turned on to decrease the voltage value of the differential to single ended amplifier internal signal via the first node when the reference voltage value is higher than a standard reference voltage value, and the first control circuit is not turned on and the second control circuit is turned on to increase the voltage value of the differential to single ended amplifier internal signal via the second node when the reference voltage value is lower than the standard reference voltage value. wherein the first control circuit comprises: a first sub control circuit, wherein the first sub control circuit comprises: The first transistor and the second transistor are connected in series with each other, wherein when the reference voltage value is higher than a standard reference voltage value, the first transistor is turned on and the second transistor is used to lower the voltage value of the differential to single-ended amplifier internal signal via the first node.

5. The single-ended receiver of claim 2, wherein, The second control circuit comprises: The second control circuit comprises: The first transistor and the second transistor are connected in series with each other, wherein when the reference voltage value is lower than a standard reference voltage value, the first transistor is turned on and the second transistor is used to pull up the voltage value of the differential to single-ended amplifier internal signal via the second node.

6. The single-ended receiver of claim 5, wherein, A control terminal of the first transistor is used to receive the control signal.

7. The single-ended receiver of claim 2, wherein, The second control circuit comprises a plurality of first sub-control circuits connected in parallel with each other, wherein when the reference voltage value is lower than a standard reference voltage value, a number of the first sub-control circuits are turned on, wherein when a voltage difference between the reference voltage value and the standard reference voltage value increases, the number increases.

8. The single-ended receiver of claim 7, wherein, The voltage detector further comprises a table, and the number is determined according to the table.

9. A single-ended receiver characterized by, Comprises: A current mode logic circuit is used to receive an input signal and a reference voltage value, and is used to output a first output signal; A differential to single-ended amplifier is coupled to the current mode logic circuit, and is used to receive the first output signal and output a second output signal, wherein a differential to single-ended amplifier internal signal is generated according to the first output signal, and the second output signal is generated according to the differential to single-ended amplifier internal signal; and A voltage detector is coupled to the differential to single-ended amplifier, and is used to output a control signal to the differential to single-ended amplifier according to the reference voltage value, Wherein the differential to single-ended amplifier is also used to adjust the voltage value of the differential to single-ended amplifier internal signal according to the control signal, so that the duty cycle of the second output signal is adjusted, wherein the voltage detector is also used to output the control signal according to the voltage difference between the reference voltage value and a standard reference voltage value.

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