Preparation method of bottom electrode excited surface acoustic wave device

Abstract

The present invention relates to a method for preparing a bottom-electrode excitation surface acoustic wave device, comprising the following steps: S1. performing photolithography on a piezoelectric wafer to prepare an electrode structure and an interdigital transducer structure; S2. depositing an insulating layer on the piezoelectric wafer, overetching the upper side of the insulating layer to define the location of an insulating layer via hole; S3. etching the insulating layer to expose the electrode structure; S4. sputtering a seed layer on the sidewalls of the insulating layer via hole to form a via hole insulating isolation layer, and electroplating the insulating layer via hole; S5. performing photolithography on a substrate wafer to define the location of the substrate wafer via hole; S6. etching the substrate wafer via hole on the substrate wafer, and sputtering the substrate wafer insulating layer and the sidewalls of the substrate wafer seed layer within the substrate wafer via hole; S7. electroplating the substrate wafer via hole. The present invention is used to prepare a surface acoustic wave device, reduce the impact of the external environment on the surface acoustic wave device, and improve the high integration requirements of the surface acoustic wave device.

Description

Technical Field

[0001] The present invention relates to the technical field of surface acoustic wave filters, in particular to a method for preparing a bottom electrode excitation type surface acoustic wave device. Background Art

[0002] A surface acoustic wave (SAW) filter is an acoustic device used in communications, radio, radar and other related RF front-end fields.

[0003] Currently, SAW devices primarily include traditional SAW, TC-SAW, and IHP-SAW, with various structures. TC-SAW is an acoustic device that suppresses temperature drift by coating the base SAW structure with a SiO2 temperature-compensating film and is widely used in communication terminals. IHP-SAW, also known as TF-SAW, is a new acoustic device that achieves higher performance by optimizing and modifying the piezoelectric substrate through a multilayer film structure. Regardless of the structure, the operating principle of SAW devices is essentially the same: a comb-shaped interdigital transducer structure is fabricated on the surface of a piezoelectric material or a substrate with a piezoelectric material layer through semiconductor processing. The piezoelectric and inverse piezoelectric effects of the piezoelectric layer enable electrical-acoustic-electrical signal propagation, thereby filtering communication signals. Commonly used piezoelectric materials include lithium tantalate (LiTaO3, LT), lithium niobate (LiNbO3, LN), aluminum nitride (AlN), and zinc oxide (ZnO), with LT and LN being the most common. LT and LN are mostly synthetic materials with high plasticity and strong corrosion resistance. Therefore, these materials are difficult to process in a refined manner. For example, when using a through-hole process to drill holes in LT and LN, the conventional processing depth can only be maintained between hundreds of nanometers and 1 micron, making it difficult to achieve micron-level processing. In addition, key material parameters such as the thermal expansion coefficient of these materials are also incompatible with silicon-based materials. Therefore, piezoelectric materials are difficult to integrate with mainstream silicon-based semiconductor processes, which leads to a natural disadvantage in the integration and miniaturization of related devices. In addition, for most SAW devices, the comb-tooth structure of their active functional area is located on the very surface of the chip. Not only is the propagation of sound waves easily affected by changes in the external environment, but the unprotected comb-tooth structure is also extremely susceptible to damage from external debris, which in turn affects the overall performance of the device. Therefore, there are almost no bare chip solutions for these devices available for use in the communications field. This further limits the application of these devices in miniaturization and integration.

[0004] Therefore, those skilled in the art are committed to developing a method for preparing a bottom electrode excited surface acoustic wave device, which is used to prepare the surface acoustic wave device, reduce the influence of the surface acoustic wave device on the external environment, and improve the high integration demand of the surface acoustic wave device. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for preparing a bottom electrode excited surface acoustic wave device, which is used to prepare the surface acoustic wave device, reduce the influence of the surface acoustic wave device on the external environment, and improve the high integration requirement of the surface acoustic wave device.

[0006] The present invention solves the above-mentioned technical problem with the following technical solution: A method for preparing a bottom electrode excited surface acoustic wave device comprises the following steps:

[0007] S1. Perform photolithography on the piezoelectric wafer to fabricate the electrode structure and IDT structure.

[0008] S2. Depositing an insulating layer on the piezoelectric wafer, overlaying the upper side of the insulating layer to define the position of the via hole in the insulating layer;

[0009] S3. Etching the insulating layer to expose the electrode structure;

[0010] S4. Sputtering a via seed layer on the sidewalls of the via holes in the insulating layer to form an insulating isolation layer for the via holes, and filling the via holes in the insulating layer with electroplating;

[0011] S5. Performing photolithography on the substrate wafer and defining the positions of the substrate wafer vias;

[0012] S6. Etching the substrate wafer via hole on the substrate wafer, and performing sputtering of the substrate wafer insulation layer and the substrate wafer seed layer sidewall in the substrate wafer via hole;

[0013] S7. Electroplating filling is performed in the substrate wafer via hole;

[0014] S8. Pre-processing and aligning the substrate wafer with the filled substrate wafer vias and the piezoelectric wafer with the electrode structure, and performing direct wafer bonding at room temperature;

[0015] S9. Prepare a UBM pad on the surface of the substrate wafer, and the UBM pad is in contact with the electroplating material in the through hole of the substrate wafer.

[0016] The beneficial effects of the present invention are: through the relevant process technologies and process steps such as wafer thin film deposition, direct wafer bonding at room temperature, etching and opening, electroplating filling, wafer thinning and CMP, a bottom comb-shaped transducer structure is realized by wrapping the piezoelectric material above the device and the insulating layer below, which solves the disadvantage that the surface acoustic wave device is easily affected by the external environment. At the same time, it can also achieve a temperature compensation effect to control the temperature drift of the device within an acceptable range. The device also meets the needs of subsequent integration in a bare chip manner. The relevant structure also has improvements in Q value and electromechanical coupling coefficient, and is suitable for the research and development of high-end advanced acoustic devices.

[0017] On the basis of the above technical solution, the present invention can also be improved as follows.

[0018] Furthermore, step S9 further includes preparing solder joints on the UBM pads, and the solder joint preparation methods include BGA ball planting, flip chip ball planting and microbump electroplating.

[0019] The beneficial effect of adopting the above further solution is that the solder joint is used to connect with external devices.

[0020] Furthermore, in step S1, before the piezoelectric wafer is photolithographically processed, a photoresist is coated on the surface of the piezoelectric wafer.

[0021] The beneficial effect of adopting the above further solution is that the surface of the piezoelectric wafer is coated with photoresist, which is conducive to rapid etching to prepare the electrode structure and the interdigital transducer structure.

[0022] Furthermore, in step S4, after the insulating layer is prepared, a functional layer is deposited on the surface of the insulating layer.

[0023] The beneficial effect of adopting the above further solution is that the functional layer is provided with corresponding functional layers according to different applications of the product, thereby improving the specificity of the surface acoustic wave device.

[0024] Furthermore, after the functional layer is deposited on the surface of the insulating layer, the surface of the functional layer is planarized, and the position of the functional layer via hole is defined on the functional layer and etched, and the insulating layer side wall sputtering and the seed layer side wall sputtering are performed in the functional layer via hole, and then the functional layer via hole is electroplated and filled.

[0025] The beneficial effect of adopting the above further solution is that functional layer vias and electroplating materials are provided on the functional layer for connecting the electrode structure and the interdigital transducer structure with external devices.

[0026] Furthermore, after the electroplating filling of the functional layer via holes is completed, the functional layer is subjected to a secondary planarization treatment. The thickness of the functional layer after planarization has an error of within ±5nm from the designed thickness, and the uniformity within the chip is within ±2nm.

[0027] The beneficial effect of adopting the above further solution is that the thickness of the functional layer after planarization is within a set range, which facilitates subsequent polishing and surface flattening.

[0028] Furthermore, in step S2, after the insulating layer is deposited on the piezoelectric wafer, the surface of the insulating layer is chemically mechanically polished, and then the surface of the insulating layer is flattened and planarized. The thickness of the insulating layer after planarization needs to be greater than the designed thickness.

[0029] The beneficial effect of adopting the above further solution is that the planarized insulating layer is conducive to subsequent etching on the surface.

[0030] Furthermore, in step S4, after the insulating layer via holes are electroplated and filled, chemical mechanical polishing is also included, and the surface of the insulating layer is subsequently flattened for a second time, so that the error between the insulating layer thickness and the designed thickness is within ±5nm, and the uniformity within the chip is within ±2nm.

[0031] The beneficial effect of adopting the above further solution is that after the surface of the insulating layer is flattened, it is convenient for subsequent bonding with the substrate wafer.

[0032] Furthermore, step S8 also includes thinning the substrate wafer side of the bonded wafer, and after thinning, the substrate wafer conductive holes need to be exposed.

[0033] The beneficial effect of adopting the above further solution is that the substrate wafer via hole and the electroplating material in the substrate wafer via hole are exposed for subsequent bonding.

[0034] Furthermore, step S8 also includes wafer thinning on one side of the piezoelectric wafer of the bonded wafer, and chemical mechanical polishing, followed by secondary flattening of the surface of the piezoelectric layer of the piezoelectric wafer, so that the error between the thickness of the piezoelectric wafer and the designed thickness is within ±5nm, and the uniformity within the chip is within ±2nm.

[0035] The beneficial effect of adopting the above further solution is that the flattened wafer is conducive to the subsequent preparation of the bonding pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is a flow chart of a specific embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of the device assembly structure of a specific embodiment of the present invention;

[0038] Figure 3 This is a schematic diagram of the photolithography structure of the piezoelectric layer according to a specific embodiment of the present invention;

[0039] Figure 4 This is a schematic structural diagram of an interdigital transducer structure and an electrode structure according to a specific embodiment of the present invention;

[0040] Figure 5 This is a schematic structural diagram of depositing an insulating layer according to a specific embodiment of the present invention;

[0041] Figure 6 This is a schematic diagram of the structure of a specific embodiment of the present invention after the insulating layer is planarized;

[0042] Figure 7This is a schematic diagram of the structure after the insulating layer is overetched according to a specific embodiment of the present invention;

[0043] Figure 8 This is a schematic structural diagram of an insulating layer after electroplating filling according to a specific embodiment of the present invention;

[0044] Figure 9 This is a structural diagram of a specific embodiment of the present invention after a functional layer is deposited on an insulating layer and then a secondary overlay is performed;

[0045] Figure 10 This is a schematic structural diagram of a functional layer after the seed layer sidewall sputtering in a specific embodiment of the present invention;

[0046] Figure 11 A schematic structural diagram of electroplating filling and planarization of the functional layer via holes according to a specific embodiment of the present invention;

[0047] Figure 12 This is a schematic structural diagram of a substrate wafer after photolithography according to a specific embodiment of the present invention;

[0048] Figure 13 This is a schematic diagram of a structure of a substrate wafer with via holes after etching according to a specific embodiment of the present invention;

[0049] Figure 14 This is a schematic diagram of the structure of a substrate wafer after the seed layer sidewall sputtering is completed in a specific embodiment of the present invention.

[0050] Figure 15 This is a schematic diagram of the structure of a substrate wafer after electroplating filling and planarization of a through hole in a specific embodiment of the present invention;

[0051] Figure 16 This is a schematic structural diagram of a specific embodiment of the present invention after wafer direct bonding between a laminated substrate wafer and a piezoelectric structure with an insulating layer and a functional layer;

[0052] Figure 17 This is a structural schematic diagram of a specific embodiment of the present invention after substrate wafer thinning is performed on a bonded wafer;

[0053] Figure 18 This is a schematic diagram of the structure of a piezoelectric layer wafer after thinning and surface flattening in a specific embodiment of the present invention;

[0054] Figure 19 The figure is a schematic diagram of the structure of the UBM pad prepared according to a specific embodiment of the present invention.

[0055] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0056] 10. Substrate wafer; 20. Functional layer; 30. Insulation layer; 40. Piezoelectric wafer; 50. IDT structure; 51. Electrode structure; 60. Via filling material layer; 61. Via insulation isolation layer; 62. Insulation layer via; 63. Via seed layer; 70. UBM pad; 80. Solder joint; 90. Photoresist. DETAILED DESCRIPTION

[0057] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0058] In the description of the present invention, it should be understood that the terms "center", "length", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "inside", "outside", "peripheral", "circumferential" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred system or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0059] In the description of the present invention, “a plurality of” means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0060] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0061] like Figures 1 to 19 As shown, a method for preparing a bottom electrode excited surface acoustic wave device includes the following steps:

[0062] S1. Perform photolithography on the piezoelectric wafer 40 to form the electrode structure 51 and the IDT structure 50. Specifically, before the photolithography of the piezoelectric wafer 40, a photoresist 90 is coated on the surface of the piezoelectric wafer 10. Then, the electrode structure 51 and the IDT structure 50 are photolithographically formed on the surface of the piezoelectric wafer 40. The piezoelectric wafer 40 is made of one or more materials selected from LN and LT with different cuts.

[0063] S2. Deposit an insulating layer 30 on the piezoelectric wafer 40. The insulating layer 30 can be made of SiO2. The thickness of the insulating layer 30 is increased by 50 nm based on design specifications to control film thickness and uniformity. Overlay is then performed on the upper side of the insulating layer 30 to define the location of the insulating layer vias 62. After depositing the insulating layer on the piezoelectric wafer, the surface of the insulating layer 30 is chemically mechanically polished (CMP). The surface of the insulating layer 30 is then flattened and planarized. The thickness of the planarized insulating layer 30 must be greater than the designed thickness.

[0064] S3. Etching the insulating layer 30 to expose the electrode structure 51;

[0065] S4. A via seed layer 63 is sputtered on the side wall of the insulating layer via hole 62 to form a via insulating isolation layer 61, and the insulating layer via hole 62 is electroplated to form a via filling material layer 60. The via filling material layer 60 is connected to the electrode structure 51 as a whole. The via filling material layer 60 realizes device insulation isolation through the via insulating isolation layer 61.

[0066] Next, after the insulating layer via holes 62 are electroplated and filled, mechanical polishing and chemical polishing (CMP) are also included, and the surface of the insulating layer 30 is subsequently flattened for a second time, so that the thickness error of the insulating layer 30 and the designed thickness is within ±5nm, and the uniformity within the chip is within ±2nm.

[0067] After the insulating layer 30 is prepared, a functional layer 20 can be deposited on the surface of the insulating layer to make the surface acoustic wave device suitable for a variety of components. In the specific steps, after the functional layer 20 is deposited on the surface of the insulating layer 30, the surface of the functional layer 20 is planarized, and the position of the functional layer via hole is defined on the functional layer 20 and etched. The functional layer via hole and the insulating layer via hole 62 are located in the same vertical plane. The insulating layer sidewall sputtering and the seed layer sidewall sputtering are then performed in the functional layer via hole. Then, the functional layer via hole is electroplated to fill the functional layer via hole, so that the electroplating material in the functional layer via hole and the via hole filling material layer 60 in the insulating layer via hole 62 are integrated.

[0068] After the electroplating filling of the functional layer via holes is completed, the functional layer 20 is subjected to a secondary planarization process. The thickness of the functional layer 20 after planarization is within ±5nm of the designed thickness, and the uniformity within the chip is within ±2nm.

[0069] S5. Perform photolithography on the substrate wafer 10 and define the positions of the substrate wafer via holes. The substrate wafer via holes and the functional layer via holes are arranged vertically opposite to each other.

[0070] S6. Etching a substrate wafer via hole on the substrate wafer 10, and performing sputtering of the substrate wafer insulating layer and the substrate wafer seed layer sidewall in the substrate wafer via hole;

[0071] S7. Perform electroplating filling in the substrate wafer via hole so that the electroplating material in the substrate wafer via hole and the electroplating material in the functional layer via hole are integrated.

[0072] S8. Pre-process and align the substrate wafer 10 with the filled substrate wafer vias and the piezoelectric wafer 40 with the electrode structure 51, and then perform direct wafer bonding at room temperature. After bonding is completed, the substrate wafer 10 side of the bonded wafer is thinned to expose the substrate wafer vias and the electroplated material within the substrate wafer vias.

[0073] Next, it also includes wafer thinning on one side of the piezoelectric wafer 10 of the bonded wafer, and ensuring the consistency and uniformity of the polished surface through chemical mechanical polishing (CMP), and then flattening the surface of the piezoelectric layer of the piezoelectric wafer 10 for a second time, so that the thickness error of the piezoelectric wafer 10 and the designed thickness is within ±5nm, and the uniformity within the chip is within ±2nm.

[0074] S9. Prepare UBM pads 70 (under bump metallization layer) on the surface of the substrate wafer, and the UBM pads 70 (under bump metallization layer) are in contact with the electroplating material in the substrate wafer through-hole for transmitting signals. It also includes preparing solder joints 80 on the UBM pads 70 (under bump metallization layer). The preparation methods of the solder joints 80 include BGA ball planting, flip chip ball planting and microbump electroplating.

[0075] In the present invention, by implementing relevant process technologies and steps such as wafer thin film deposition, direct wafer bonding at room temperature, etching and opening, electroplating and filling, wafer thinning and CMP, a bottom comb-shaped transducer structure is achieved, which is wrapped by the piezoelectric material above the device and the insulating layer below. This solves the disadvantage that the surface acoustic wave device is easily affected by the external environment. At the same time, it can also achieve a temperature compensation effect to control the temperature drift of the device within an acceptable range. The device also meets the requirements of subsequent integration in a bare chip manner. The relevant structure also has improved Q value and electromechanical coupling coefficient, making it suitable for the research and development of high-end advanced acoustic devices.

[0076] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0077] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a bottom electrode excited surface acoustic wave device, characterized in that: The following steps are involved: S1. Perform photolithography on the piezoelectric wafer to fabricate the electrode structure and IDT structure. S2. Depositing an insulating layer on the piezoelectric wafer, overlaying the upper side of the insulating layer to define the position of the via hole in the insulating layer; S3. Etching the insulating layer to expose the electrode structure; S4. Sputtering a via seed layer on the sidewalls of the via holes in the insulating layer to form an insulating isolation layer for the via holes, and filling the via holes in the insulating layer with electroplating; S5. Performing photolithography on the substrate wafer and defining the positions of the substrate wafer vias; S6. Etching the substrate wafer via hole on the substrate wafer, and performing sputtering of the substrate wafer insulation layer and the substrate wafer seed layer sidewall in the substrate wafer via hole; S7. Electroplating filling is performed in the substrate wafer via hole; S8. Pre-processing and aligning the substrate wafer with the filled substrate wafer vias and the piezoelectric wafer with the electrode structure, and performing direct wafer bonding at room temperature; S9. Prepare a UBM pad on the surface of the substrate wafer, and the UBM pad is in contact with the electroplating material in the through hole of the substrate wafer.

2. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 1, wherein: Step S9 further includes preparing solder joints on the UBM pads, and the solder joint preparation methods include BGA ball planting, flip chip ball planting and microbump electroplating.

3. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 1, wherein: In step S1, before the piezoelectric wafer is photolithographically processed, a photoresist is coated on the surface of the piezoelectric wafer.

4. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 1, wherein: In step S4, after the insulating layer is prepared, a functional layer is deposited on the surface of the insulating layer.

5. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 4, wherein: After the functional layer is deposited on the surface of the insulating layer, the surface of the functional layer is planarized, and the position of the functional layer via hole is defined on the functional layer and etched, and the insulating layer side wall sputtering and the seed layer side wall sputtering are performed in the functional layer via hole, and then the functional layer via hole is electroplated and filled.

6. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 5, wherein: After the electroplating filling of the functional layer via holes is completed, the functional layer is subjected to a secondary planarization treatment. The thickness of the functional layer after planarization has an error of within ±5nm from the designed thickness, and the uniformity within the chip is within ±2nm.

7. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 1, wherein: In step S2, after the insulating layer is deposited on the piezoelectric wafer, the surface of the insulating layer is chemically mechanically polished, and then the surface of the insulating layer is flattened and planarized. The thickness of the insulating layer after planarization needs to be greater than the designed thickness.

8. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 1, wherein: In step S4, after the insulating layer via holes are electroplated and filled, the insulating layer surface is subsequently flattened and smoothed for a second time by chemical mechanical polishing, so that the thickness of the insulating layer is within ±5nm of the designed thickness and the uniformity within the chip is within ±2nm.

9. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 1, wherein: Step S8 also includes thinning the substrate wafer side of the bonded wafer, and after thinning, the substrate wafer conductive holes need to be exposed.

10. The method for preparing a bottom electrode excited surface acoustic wave device according to claim 9, wherein: Step S8 also includes wafer thinning on one side of the piezoelectric wafer of the bonded wafer, and chemical mechanical polishing, followed by secondary flattening of the surface of the piezoelectric layer of the piezoelectric wafer, so that the thickness error of the piezoelectric wafer and the designed thickness is within ±5nm, and the uniformity within the chip is within ±2nm.

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