Adjustable delay circuit and electronic device
Through the combination of three-stage adjustment modules, the large delay range and fine adjustment steps of the delay circuit under a limited area are realized, and the contradiction between the difficulty of the existing technology is solved.
Patent Information
- Application Number
- CN202211003512.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-08-19
- Publication Date
- 2025-08-19
- Estimated Expiration
- 2042-08-19
AI Technical Summary
It is difficult for existing delay circuits to achieve large delay range and fine adjustment steps at the same time under limited areas.
The first adjustment module, the second adjustment module and the third adjustment module are used for three-stage adjustment, and the multi-stage adjustment of the delay is achieved through the combination of decoding, differential processing and delay module.
It realizes the advantages in delay range and adjustment accuracy, and can meet the needs of large delay range and fine adjustment steps at the same time.
Smart Images
Figure CN115378406B_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of electronic circuits, and in particular relates to an adjustable delay circuit and electronic equipment. Background Art
[0002] In circuit design or application, it's sometimes necessary to delay one signal for a period of time before interacting with another. This is typically accomplished using a delay circuit. Delay circuits, as a circuit structure that allows for the free movement of signal edges, are widely used in various clock, data, and calibration circuits.
[0003] The most common implementation of delay circuits is phase interpolators or delay lines. Due to structural limitations, these delay circuits find it difficult to simultaneously achieve two diametrically opposed functions: a large delay range and fine adjustment steps within a limited area. Summary of the Invention
[0004] The purpose of the embodiments of the present application is to provide an adjustable delay circuit and electronic device that can simultaneously achieve a large delay range and fine adjustment steps.
[0005] An embodiment of the present application provides an adjustable delay circuit, comprising a first adjustment module, including a first input terminal and a control output terminal, wherein the first adjustment module is configured to decode a first adjustment signal input from the first input terminal and output a control selection signal from the control output terminal according to the decoding result; a second adjustment module, including a second input terminal and a first output terminal, wherein the second adjustment module is configured to perform differential processing on a second adjustment signal input from the second input terminal and output a first pair of differential signals obtained by the differential processing through the first output terminal; and a third adjustment module, including a third input terminal and a second output terminal, wherein the third adjustment module is configured to perform differential processing on a third adjustment signal input from the third input terminal and output a second pair of differential signals obtained by the differential processing through the second output terminal.
[0006] The delay module includes: a signal input end for receiving a target differential signal pair; a selection signal input end connected to the control output end and used to receive the control selection signal; a first control end for receiving the first pair of differential signals; a second control end for receiving the second pair of differential signals; the delay module is used to delay the target differential signal pair according to the input control selection signal, the first pair of differential signals and the second pair of differential signals; and a signal output end is used to output the target differential signal pair after being delayed by the delay module.
[0007] An embodiment of the present application further provides an electronic device, which includes the above-mentioned adjustable delay circuit.
[0008] At least one of the above-mentioned technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects: the adjustable delay circuit in the present application adopts a first adjustment module, a second adjustment module and a third adjustment module for three-level adjustment, thereby realizing multi-level adjustment of the delay to meet the requirements of the delay range and adjustment accuracy. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0010] Figure 1 This is a schematic diagram of the structure of an adjustable delay circuit in an embodiment of the present application;
[0011] Figure 2 This is a structural diagram of a delay module in one embodiment of the present application;
[0012] Figure 3 This is a structural diagram of the first delay submodule in one embodiment of the present application;
[0013] Figure 4 This is a structural diagram of the second delay submodule in one embodiment of the present application. DETAILED DESCRIPTION
[0014] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with the specific embodiments of this application and the corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0015] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.
[0016] The technical solutions provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.
[0017] The embodiment of the present application provides an adjustable delay circuit, such as Figure 1 shown. Figure 1 This is a schematic diagram of the structure of an adjustable delay circuit in an embodiment of the present application, which mainly includes:
[0018] The first regulating module includes a first input terminal and a control output terminal. The first regulating module is used to decode the first regulating signal input from the first input terminal and output a control selection signal from the control output terminal according to the decoding result. In the embodiment of the present application, according to the actual requirements of the delay circuit, the first regulating module can output multiple control selection signals. Schematically, in the embodiment of the present application, the first regulating module can use a decoder to generate a control selection signal through the decoder. For example, in Figure 1 In the embodiment, the first input terminal A of the first regulating module can be used to receive a 3-bit first regulating signal input by IN3. The first regulating module decodes the first regulating signal and can output an 8-bit control selection signal from the N terminal accordingly.
[0019] The second regulating module includes a second input terminal and a first output terminal, wherein the second regulating module is used to perform differential processing on the second regulating signal input from the second input terminal, and output a first pair of differential signals obtained by the differential processing through the first output terminal, for example, Figure 1 In the embodiment of the present application, the first output terminal of the second adjustment module includes VOP and VON, wherein one differential signal in the first pair of differential signals is output through VOP, and the other differential signal is output through VON. In an embodiment of the present application, the second adjustment module can achieve a delay adjustment step size with a certain accuracy based on the actual requirements of the delay circuit. For example, an embodiment of the present application can use a 4-bit digital-to-analog converter DAC as the second adjustment module, and the second adjustment signal inputted into the second input terminal of the second adjustment module can be a 4-bit signal.
[0020] The third adjustment module includes a third input terminal and a second output terminal, wherein the third adjustment module is used to perform differential processing on the third adjustment signal input from the third input terminal, and output the second pair of differential signals obtained by the differential processing through the second output terminal, for example, Figure 1 In the embodiment of the present application, the second output terminal of the second adjustment module includes VOP and VON, wherein one differential signal of the second pair of differential signals is output through VOP, and the other differential signal is output through VON. In an embodiment of the present application, the third adjustment module can achieve a delay adjustment step length of a certain accuracy based on the actual requirements of the delay circuit. For example, an embodiment of the present application can use a 10-bit digital-to-analog converter DAC as the third adjustment module, and the third adjustment signal input to the third input terminal of the third adjustment module can be a 10-bit signal.
[0021] Delay module, which can include:
[0022] Signal input terminal, used to receive the target differential signal pair, for example, Figure 1 In the embodiment, the signal input terminals of the delay module include VIP and VIN, each of which is used to receive a differential signal in the target differential signal pair;
[0023] The selection signal input terminal is connected to the control output terminal and is used to receive the control selection signal. Figure 1 In the embodiment, the strobe signal input terminal is a NOE, which is used to receive the 8-bit control strobe signal output by the first regulation module;
[0024] The first control terminal is used to receive the first pair of differential signals, for example, Figure 1 In the embodiment, the first control terminal may include 4bitDAC_VIP and 4bitDAC_VIN;
[0025] The second control terminal is used to receive the second pair of differential signals, for example, Figure 1 In the embodiment, the first control terminal may include 10bitDAC_VIP and 10bitDAC_VIN;
[0026] The delay module is used to delay the target differential signal pair according to the input control selection signal, the first pair of differential signals and the second pair of differential signals;
[0027] The signal output terminal is used to output the target differential signal pair after the delay module delays the target differential signal pair. Figure 1 In the embodiment, the signal output terminals of the delay module include VOP and VON, which are respectively used to output one differential signal of the delayed target differential signal pair.
[0028] In an embodiment of the present application, the first adjustment module inputs a control selection signal to the delay module according to the input first adjustment signal, the second adjustment module inputs a first pair of differential signals to the delay module according to the input second adjustment signal, and the third adjustment module inputs a second pair of differential signals to the delay module according to the input third adjustment signal. The delay module delays the target differential signal pair according to the input control selection signal, the first pair of differential signals and the second pair of differential signals, so that different levels of adjustment signals can be input through the first adjustment module, the second adjustment module and the third adjustment module. For example, a coarse adjustment signal is input through the first adjustment module, a secondary adjustment signal is input through the second adjustment module, and a fine adjustment signal is input through the third adjustment module, thereby expanding the delay range of the delay module and improving the delay accuracy of the delay module.
[0029] Figure 2An optional structural diagram of the delay module in the embodiment of the present application is shown. Figure 2 As shown, in this optional implementation, the delay module mainly includes: a first delay submodule, N second delay submodules, a first load module and a second load module, wherein N is an integer greater than or equal to 1, for example, Figure 2 In the example, N is 7.
[0030] In this possible implementation, the first control end includes: at least one first control sub-end and at least one second control sub-end, the first control sub-end is used to receive one differential signal in the first pair of differential signals, and the second control sub-end is used to receive the other differential signal in the first pair of differential signals.
[0031] In this possible implementation, the first delay submodule includes the signal input terminal, the second control terminal, the first differential output terminal, and the first differential output positive terminal. The second control terminal may include two ports, for example, Figure 2 The 10bitDAC_VIP port and 10bitDAC_VIN port, the first differential output terminal (VOP and VON) is used to output a pair of differential signals to the first second delay sub-module, and (IOP and ION) is connected to the second differential output positive terminal of each second delay sub-module and then connected to the first load module.
[0032] In an embodiment of the present application, each of the N second delay submodules includes: a second differential input terminal, a second differential output terminal, and a second differential output positive terminal. The second differential output terminal of the previous second delay submodule in each of the N second delay submodules is connected to the second differential input terminal of the next second delay submodule, the second differential input terminal of the first second delay submodule in the N second delay submodules is connected to the first differential output terminal, and the second differential output terminal of the last second delay submodule in the N second delay submodules is connected to the second load module; the first differential output positive terminal is connected to the second differential output positive terminals of each second delay submodule and then connected to the first load module.
[0033] In the embodiment of the present application, the first load module includes the signal output end, that is, the target differential signal after delay processing is output through the first load module.
[0034] In the embodiment of the present application, one of the two adjacent delay submodules among the first delay submodule and the N second delay submodules is further provided with the first control sub-terminal, and the other delay submodule is further provided with the second control sub-terminal. That is, in the embodiment of the present application, one differential signal in the first pair of differential signals output by the second adjustment module can be input to one of the two adjacent delay submodules among the first delay submodule and the N second delay submodules, and the other differential signal can be output to the other of the two adjacent delay submodules, so that the delays of the two adjacent delay submodules can be interpolated. For example, in Figure 2 In the embodiment, the first delay sub-module includes a first control sub-terminal 4bitDAC_VI, which is used to receive a differential signal 4bitDAC_VIN in the first pair of differential signals, and the first second delay sub-module includes a second control sub-terminal 4bitDAC_VI, which is used to receive the other differential signal 4bitDAC_VIP in the first pair of differential signals, and the second second delay sub-module includes a first control sub-terminal 4bitDAC_VI, which is used to receive a differential signal 4bitDAC_VIN in the first pair of differential signals.
[0035] In the embodiments of this application, Figure 2 As shown, each of the first delay submodule and the N second delay submodules is provided with a selection signal input terminal NOE for receiving a control selection signal for controlling whether the corresponding delay submodule is connected to the first control subterminal or the second control subterminal. Figure 2 In the embodiment, the control output terminal N of the first regulating module outputs an 8-bit control selection signal, of which 1 bit is input to the selection signal input terminal of a delay sub-module to control whether the delay sub-module is connected to the first control sub-terminal or the second control sub-terminal, that is, whether it is connected to one of the first pair of differential signals.
[0036] In a possible implementation of the embodiment of the present application, as Figure 3 and 4 As shown, the first delay submodule may include a first buffer unit, a phase interpolation unit and a first gating unit; the second delay submodule may include a second buffer unit and a second gating unit.
[0037] In the above possible implementation, the input end of the first buffer unit includes the signal input end, and the output end is connected to an input end of the phase interpolation unit; one input end of the phase interpolation unit is connected to the output end of the first buffer unit, and the other input end is used to input the target differential signal pair, the control end of the phase interpolation unit includes the second control end, and the output end of the phase interpolation unit is connected to the first differential output end; the input end of the first gating unit is connected to the output end of the phase interpolation unit, the control end of the first gating unit includes one of the gating signal input ends, the output end of the first gating unit includes the first differential output positive end, and the first gating unit also includes the first control sub-end or the second control sub-end.
[0038] In the above possible implementation, the input end of the second buffer unit may include the second differential input end, and the output end of the second buffer unit is connected to the second differential output end; the input end of the second gating unit is connected to the output end of the second buffer unit, the control end includes a gating signal input end, the output end of the second gating unit includes the second differential output positive end, and the second gating unit also includes the first control sub-end or the second control sub-end.
[0039] Figure 3 FIG. 1 shows a schematic diagram of the structure of the first delay submodule in an embodiment of the present application. Figure 3 As shown, the first buffer unit may include:
[0040] A first transistor Q1, having a base connected to the input end of the first buffer unit, a collector connected to one end of the first resistor R1, and an emitter connected to ground via a current source I1;
[0041] A second transistor Q2 has a base connected to the input terminal, a collector connected to one end of the second resistor R2, and an emitter connected to the ground via a current source I1;
[0042] A first resistor R1, one end of which is connected to the power supply terminal VCC, and the other end of which is connected to the collector of the first transistor Q1;
[0043] A second resistor R2, one end of which is connected to the power supply terminal VCC, and the other end of which is connected to the collector of the second transistor Q2;
[0044] A third transistor Q3, whose base is connected to the collector of the first transistor Q1, the collector is connected to the power supply terminal VCC, and the emitter serves as an output terminal of the first buffer unit and is grounded through the current source I2;
[0045] The fourth transistor Q4 has a base connected to the collector of the second transistor Q2 , a collector connected to the power supply terminal VCC, and an emitter serving as an output terminal of the first buffer unit and grounded through the current source I3 .
[0046] In a possible implementation of the embodiment of the present application, as Figure 3 As shown, the phase interpolation unit may include:
[0047] a fifth transistor Q5 , having a base connected to the output end of the first buffer unit, a collector connected to one end of the third resistor R3 , and an emitter connected to the collector of the ninth transistor Q9 ;
[0048] a sixth transistor Q6 , having a base connected to the output end of the first buffer unit, a collector connected to one end of the fourth resistor R4 , and an emitter connected to the collector of the ninth transistor Q9 ;
[0049] a seventh transistor Q7, having a base connected to the signal input terminal, a collector connected to one end of the third resistor R3, and an emitter connected to the collector of the tenth transistor Q10;
[0050] an eighth transistor Q8 , having a base connected to the signal input terminal, a collector connected to one end of the fourth resistor R4 , and an emitter connected to the collector of the tenth transistor Q10 ;
[0051] a ninth transistor Q9, having a base connected to the third control sub-terminal, a collector connected to the emitters of the fifth transistor Q5 and the sixth transistor Q6, respectively, and an emitter grounded via a current source I4, wherein the second control terminal includes the third control sub-terminal and the fourth control sub-terminal;
[0052] a thirteenth transistor Q10, whose base is connected to the fourth control sub-terminal, whose collector is respectively connected to the emitter of the seventh transistor Q7 and the emitter of the eighth transistor Q8, and whose emitter is grounded through the current source I4;
[0053] A third resistor R3, one end of which is connected to the collector of the seventh transistor Q7, and the other end of which is connected to the power supply terminal VCC;
[0054] The fourth resistor R4 has one end connected to the collector of the eighth transistor Q8 and the other end connected to the power supply terminal VCC.
[0055] In a possible implementation of the embodiment of the present application, the phase interpolation unit may further include an emitter follower unit, such as Figure 3 As shown, the emitter follower unit may include:
[0056] an eleventh transistor Q11, whose base is connected to the collector of the seventh transistor Q7, the collector is connected to the power supply terminal VCC, and the emitter serves as the output terminal of the phase interpolation unit and is grounded through the current source I5;
[0057] The twelfth transistor Q12 has a base connected to the collector of the eighth transistor Q8 , a collector connected to the power supply terminal VCC, and an emitter serving as an output terminal of the phase interpolation unit and grounded through the current source I6 .
[0058] In a possible implementation of the embodiment of the present application, as Figure 3 As shown, the first gating module includes:
[0059] A thirteenth transistor Q13, whose base serves as an input terminal of the first selection module and whose emitter is connected to the collector of the fifteenth transistor Q15;
[0060] A fourteenth transistor Q14, whose base serves as an input terminal of the first selection module and whose emitter is connected to the collector of the fifteenth transistor Q15;
[0061] The collector of the thirteenth transistor Q13 and the collector of the fourteenth transistor Q14 serve as output terminals;
[0062] A fifteenth transistor Q15 has a base connected to the source of the MOS transistor NM1, a collector connected to the emitter of the thirteenth transistor Q13 and the emitter of the fourteenth transistor Q14, and an emitter grounded;
[0063] The MOS transistor NM1 has a gate connected to the selection signal input terminal, a source grounded to the base of the fifteenth transistor Q15, and a drain connected to the first control sub-terminal or the second control sub-terminal.
[0064] Figure 4 The following is a schematic diagram showing the structure of the second delay submodule in one embodiment of the present application. The second buffer unit may include:
[0065] A first transistor Q1, having a base connected to the input end of the second buffer unit, a collector connected to one end of the first resistor R1, and an emitter connected to ground via a current source I1;
[0066] A second transistor Q2, having a base connected to the input end of the second buffer unit, a collector connected to one end of the second resistor R2, and an emitter connected to ground via a current source I1;
[0067] A first resistor R1, one end of which is connected to the power supply terminal VCC, and the other end of which is connected to the collector of the first transistor Q1;
[0068] A second resistor R2, one end of which is connected to the power supply terminal VCC, and the other end of which is connected to the collector of the second transistor Q2;
[0069] A third transistor Q3, whose base is connected to the collector of the first transistor Q1, the collector is connected to the power supply terminal VCC, and the emitter serves as an output terminal of the second buffer unit and is grounded through the current source I2;
[0070] The fourth transistor Q4 has a base connected to the collector of the second transistor Q2 , a collector connected to the power supply terminal VCC, and an emitter serving as an output terminal of the second buffer unit and grounded through the current source I3 .
[0071] In a possible implementation of the embodiment of the present application, as Figure 4 As shown, the second gating unit may include:
[0072] A thirteenth transistor Q13, whose base serves as an input terminal of the second selection unit and whose emitter is connected to the collector of the fifteenth transistor Q15;
[0073] A fourteenth transistor Q14, whose base serves as an input terminal of the second selection unit and whose emitter is connected to the collector of the fifteenth transistor Q15;
[0074] The collector of the thirteenth transistor Q13 and the collector of the fourteenth transistor Q14 serve as output terminals;
[0075] A fifteenth transistor Q15 has a base connected to the source of the MOS transistor NM1, a collector connected to the emitter of the thirteenth transistor Q13 and the emitter of the fourteenth transistor Q14, and an emitter grounded;
[0076] The MOS transistor NM1 has a gate connected to the selection signal input terminal, a source grounded to the base of the fifteenth transistor Q15, and a drain connected to the first control sub-terminal or the second control sub-terminal.
[0077] In an embodiment of the present application, the target differential signal pair is delayed by the delay module according to the input control selection signal, the first pair of differential signals and the second pair of differential signals, and the first adjustment module, the second adjustment module and the third adjustment module are used to perform three-level adjustment, which can simultaneously achieve two completely opposite functions of a large delay range and a fine adjustment step, and has great advantages in both delay range and adjustment accuracy.
[0078] The present application embodiment provides another adjustable delay circuit, which can be referred to Figures 1 to 4 The embodiment of the present application is composed of a 10bit_DAC (10-bit digital-to-analog converter), a 4bit_DAC (4-bit digital-to-analog converter), a decoder and a delay module.
[0079] In the embodiment of the present application, the input terminal DI<9:0> of the 10-bit_DAC serves as the input terminal of IN1<9:0> of the three-level adjustment; the input terminal DI<3:0> of the 4-bit_DAC serves as the input terminal of IN2<3:0> of the two-level adjustment; the input terminal A<2:0> of the decoder serves as the input terminal of IN3<2:0> of the first-level adjustment; the differential input terminal VIP / VIN of the delay module is connected to the differential input signal VIP / VIN, and the differential output terminal VOP / VON is connected to the differential output signal VOP / VON.
[0080] In the embodiment of the present application, the differential output terminals VOP / VON of the 10-bit_DAC are connected to the 10-bitDAC_VIP / 10-bitDAC_VIN ports of the delay module; the differential output terminals VOP / VON of the 4-bit_DAC are connected to the 4-bitDAC_VIP / 4-bitDAC_VIN ports of the delay module; and the output terminals N<7:0> of the decoder are connected to the NOE<7:0> ports of the delay module.
[0081] In the embodiment of the present application, the delay module is composed of a first delay submodule, seven second delay submodules, a first load module and a second load module.
[0082] The differential input terminal VIP / VIN of the first delay submodule is connected to the external differential input signal VIP / VIN; the 10bitDAC_VIP / 10bitDAC_VIN terminal of the first delay submodule is connected to the external third-stage adjustment signal 10bitDAC_VIP / 10bitDAC_VIN; the 4bitDAC_VI terminal of the first delay submodule is connected to the external 4bitDAC_VIN signal as a control terminal of the second-stage adjustment; the NOE of the first delay submodule is connected to the control selection signal NOE <0> ; The differential output terminal VOP / VON of the first delay submodule serves as a differential output terminal to output a differential signal; the IOP terminal of the first delay submodule is connected together with the IOP terminals of the other six second delay submodules and connected to the emitter of transistor Q1; the ION terminal of the first delay submodule is connected together with the ION terminals of the other six second delay submodules and connected to the emitter of transistor Q2; the IF terminal of the first delay submodule is connected together with the IF terminals of the other six second delay submodules and connected to the current source I5 to ground.
[0083] The differential input terminal VIP / VIN of the first second delay submodule (numbered as B_1) is connected to the differential output terminal VIP / VIN of the first delay submodule; the 4-bitDAC_VI terminal of the second delay submodule (B_1) is connected to the external 4-bitDAC_VIP signal as a control terminal of the second stage regulation; the NOE of the second delay submodule (B-_1) is connected to the control selection signal NOE <1> The differential output terminal VOP / VON of the second delay submodule (B_1) serves as a differential output terminal to output a differential signal.
[0084] The differential input terminal VIP / VIN of the second delay submodule (numbered as B_2) is connected to the differential output terminal VIP / VIN of the second delay submodule (B_1); the 4-bitDAC_VI terminal of the second delay submodule (B_2) is connected to the external 4-bitDAC_VIN signal as a control terminal of the second stage regulation; the NOE of the second delay submodule (B_2) is connected to the control selection signal NOE <2> The differential output terminal VOP / VON of the second delay submodule (B_2) serves as a differential output terminal to output a differential signal.
[0085] The differential input terminal VIP / VIN of the third second delay submodule (numbered as B_3) is connected to the differential output terminal VIP / VIN of the second delay submodule (B_2); the 4-bitDAC_VI terminal of the second delay submodule (B_3) is connected to the external 4-bitDAC_VIP signal as a control terminal of the second stage regulation; the NOE of the second delay submodule (B_3) is connected to the control selection signal NOE <3> ; The differential output terminal VOP / VON of the second delay submodule (B_3) serves as a differential output terminal to output a differential signal.
[0086] The differential input terminal VIP / VIN of the fourth second delay submodule (numbered as B_4) is connected to the differential output terminal VIP / VIN of the second delay submodule (B_3); the 4-bitDAC_VI terminal of the second delay submodule (B_4) is connected to the external 4-bitDAC_VIN signal as a control terminal of the second stage regulation; the NOE of the second delay submodule (B_4) is connected to the control selection signal NOE <4> The differential output terminal VOP / VON of the second delay submodule (B_4) serves as a differential output terminal to output a differential signal.
[0087] The differential input terminal VIP / VIN of the fifth second delay submodule (numbered as B_5) is connected to the differential output terminal VIP / VIN of the second delay submodule (B_4); the 4-bitDAC_VI terminal of the second delay submodule (B_5) is connected to the external 4-bitDAC_VIP signal as a control terminal of the second stage regulation; the NOE of the second delay submodule (B_5) is connected to the control selection signal NOE <5> The differential output terminal VOP / VON of the second delay submodule (B_5) serves as a differential output terminal to output a differential signal.
[0088] The differential input terminal VIP / VIN of the sixth second delay submodule (may be numbered as B_6) is connected to the differential output terminal VIP / VIN of the second delay submodule (B_5); the 4-bitDAC_VI terminal of the second delay submodule (B_6) is connected to the external 4-bitDAC_VIN signal as a control terminal of the second stage regulation; the NOE of the second delay submodule (B_6) is connected to the control selection signal NOE <6> The differential output terminal VOP / VON of the second delay submodule (B_6) serves as a differential output terminal to output a differential signal.
[0089] The differential input terminal VIP / VIN of the seventh second delay submodule (may be numbered as B_7) is connected to the differential output terminal VIP / VIN of the second delay submodule (B_6); the 4-bitDAC_VI terminal of the second delay submodule (B_7) is connected to the external 4-bitDAC_VIP signal as a control terminal of the second stage regulation; the NOE of the second delay submodule (B_7) is connected to the control selection signal NOE <7> The differential output terminal VOP / VON of the second delay submodule (B_5) serves as a differential output terminal to output a differential signal.
[0090] As the load of the second delay submodule (B_7), the base of transistor Q5 is connected to the output terminal VOP of the second delay submodule (B_7); the base of transistor Q6 is secondarily connected to the output terminal VON of the delay submodule (B_7); the emitters of Q5 and Q6 are connected together to a current source I04 and then to ground; the collector of Q5 is connected to the lower end of resistor R4; the collector of Q6 is connected to the lower end of resistor R5; and the upper ends of R4 and R5 are simultaneously connected to VCC.
[0091] The bases of transistors Q1 and Q2 are connected together to the lower end of resistor R3, and the current source I01 is connected to ground. The upper end of R3 is connected to VCC; the collector of Q1 is connected to the lower end of resistor R1; the collector of Q2 is connected to the lower end of resistor R2; the upper ends of R1 and R2 are connected to VCC; the base of transistor Q3 is connected to the lower end of R1; the collectors of transistors Q3 and Q4 are both connected to VCC, the emitter of Q4 is connected to the current source I03 and ground, and the emitters of Q3 and Q4 serve as the differential output terminal VOP / VON of the circuit.
[0092] In this embodiment of the present application, the first delay submodule includes:
[0093] The bases of transistors Q1 and Q2 are connected to the differential input terminal VIP / VIN and the external differential input signal. The emitters of Q1 and Q2 are connected together to the current source I1 and ground. The collector of Q1 is connected to the lower end of resistor R1, the collector of Q2 is connected to the lower end of resistor R2, and the upper ends of R1 and R2 are both connected to VCC. At the same time, the lower end of R1 is connected to the base of transistor Q3, the lower end of R2 is connected to the base of transistor Q4, and the bases of Q3 and Q4 are connected to VCC at the same time. The emitter of Q3 is connected to the current source I2 and ground, and the emitter of Q4 is connected to the current source I3 and ground.
[0094] The base of transistor Q5 is connected to the emitter of Q3, the base of transistor Q6 is connected to the emitter of Q4, and the emitters of Q5 and Q6 are connected together to the collector of transistor Q9; the collector of Q5 and the collector of transistor Q7 are connected together and connected to the lower end of resistor R3; the collector of Q6 and the collector of transistor Q7 are connected together and connected to the lower end of resistor R4; the upper ends of R3 and R4 are both connected to VCC; the bases of Q8 and Q7 are connected to the differential input terminal VIP / VIN to receive the external differential input signal, and the emitters of Q7 and Q8 are connected together to the collector of transistor Q10; Q The bases of Q10 and Q9 are connected to the external first-stage regulation signal 10bitDAC_VIP / 10bitDAC_VIN; the emitters of Q9 and Q10 are connected together and connected to the current source I4 to ground; the base of the transistor Q11 is connected to the lower end of R3, the base of the transistor Q12 is connected to the lower end of R4, the collectors of Q11 and Q12 are both connected to VCC, the emitter of Q11 is connected to the current source I5 to ground, the emitter of Q12 is connected to the current source I6 to ground, and at the same time, the emitters of Q11 and Q12 serve as the voltage differential output terminal VOP / VON of the circuit to output the voltage differential signal.
[0095] The base of transistor Q13 is connected to the emitter of Q11, the base of transistor Q14 is connected to the emitter of Q12, and the emitters of Q13 and Q14 are connected together to the collector of transistor Q15. The collectors of Q14 and Q13 serve as the current differential output terminal IOP / ION of the circuit to output the current differential signal; the base of Q15 is connected to the source of NMOS tube NM1, and the emitter of Q15 serves as the current output terminal IF; the gate of NM1 serves as the selection control NOE to connect to the external selection signal, and the drain of NM1 serves as one end of the second-stage adjustment signal 4bitDAC_VI to connect to the external signal.
[0096] In this embodiment of the present application, the second delay submodule includes:
[0097] The bases of transistors Q1 and Q2 are connected to the differential input terminal VIP / VIN, which receives an external differential input signal. The emitters of Q1 and Q2 are connected together, connected to current source I1 and ground. The collector of Q1 is connected to the lower end of resistor R1, and the collector of Q2 is connected to the lower end of resistor R2. The upper ends of R1 and R2 are both connected to VCC. Simultaneously, the lower end of R1 is connected to the base of transistor Q3, and the lower end of R2 is connected to the base of transistor Q4. The bases of Q3 and Q4 are both connected to VCC. The emitter of Q3 is connected to current source I2 and ground, and the emitter of Q4 is connected to current source I3 and ground. Simultaneously, the emitters of Q3 and Q4 serve as the circuit's voltage differential output terminal VOP / VON, outputting a voltage differential signal.
[0098] The base of transistor Q13 is connected to the emitter of Q3, the base of transistor Q14 is connected to the emitter of Q4, and the emitters of Q13 and Q14 are connected together to the collector of transistor Q15. The collectors of Q14 and Q13 serve as the current differential output terminal IOP / ION of the circuit to output the current differential signal; the base of Q15 is connected to the source of NMOS tube NM1, and the emitter of Q15 serves as the current output terminal IF; the gate of NM1 serves as the selection control NOE to connect to the external selection signal, and the drain of NM1 serves as one end of the second-stage adjustment signal 4bitDAC_VI to connect to the external signal.
[0099] In the embodiment of the present application, first, a first delay submodule can provide a fixed delay X (the value of X is different for different processes), and each second delay submodule can provide a fixed delay Y (the value of Y is different for different processes), so the maximum delay range of the circuit structure of this embodiment is approximately X+7Y; in addition, the number of second delay submodules can be appropriately increased or decreased according to needs to achieve a wide delay range; secondly, two adjacent second delay submodules are selected from the 7 second delay submodules according to the delay needs, so the accuracy of the first-level adjustment is Y; thirdly, phase interpolation is performed on the two adjacent second delay submodules that are selected, and the adjustment accuracy is Y / 16 (the accuracy is determined by the 4-bit DAC, and the bits can be added or subtracted according to actual needs), thereby achieving the second-level adjustment; finally, the first delay submodule is a phase interpolator module, and its adjustment accuracy is X / 1024 (the accuracy is determined by the 10-bit The DAC determines the bit addition and subtraction, and the bit can be added or subtracted according to actual needs. The value of X is generally about twice that of Y. Based on this rough estimate, X / 1024 is 32 times smaller than Y / 16. In other words, the accuracy of the third-stage adjustment is 32 times higher than that of the second stage, thereby achieving high-precision adjustment. Therefore, the circuit structure of this embodiment can achieve an adjustment range of X+7Y, three-stage adjustment with an accuracy of X / 1024, two-stage adjustment with an accuracy of Y / 16, and one-stage adjustment with an accuracy of Y.
[0100] In an embodiment of the present application, the delay circuit has a three-level adjustment function. When in use, the first-level adjustment is first used to perform a coarse adjustment. The control selection signal output by the first adjustment module is used to select the two adjacent second delay sub-modules. The second-level adjustment is used to perform a secondary adjustment. According to the second adjustment signal input by the second adjustment module, the two selected second delay sub-modules are controlled to be connected to the first control sub-end or the second control sub-end, so as to interpolate the delays of the two adjacent second delay sub-modules, thereby achieving secondary adjustment. Finally, the third-level adjustment is used to perform a fine adjustment. The second pair of differential signals output by the third scheduling module is used to control whether the first delay sub-module is connected to the first control sub-end or the second control sub-end, so as to interpolate the delay of the first delay sub-module, thereby achieving fine adjustment. Therefore, the two conflicting indicators of large delay range and fine adjustment can be achieved at the same time. Specifically, the decoder selects only two adjacent delay submodules, such as the second delay submodule B_1 and the second delay submodule B_2, or the second delay submodule B_6 and the second delay submodule B_7, to perform coarse delay adjustment, with an adjustment accuracy equivalent to the delay of one CML buffer. After the first level of adjustment is set, the two selected modules are used to perform a 4-bit phase interpolation, with an adjustment accuracy equivalent to the delay of one CML buffer / 16, thus performing the second level of adjustment. Finally, a third level of fine adjustment is performed, with an adjustment accuracy equivalent to the delay of one CML buffer / 1024. The maximum delay range of the embodiment of the present application is approximately: the delay of one CML buffer * 10; the minimum adjustment accuracy is approximately: the delay of one CML buffer / 1024.
[0101] It should be noted that, although the adjustable delay circuit provided in the embodiment of the present application can perform the above three-level delay adjustment, in specific applications, the adjustable delay circuit can also be used to achieve one-level or two-level delay adjustment. For example, the above-mentioned adjustable delay circuit can be used to achieve a delay adjustment with a narrow range but high precision. For example, a fixed high level can be input at the input end of the first adjustment module and the second adjustment module, and a corresponding adjustment signal can be input at the input end of the third scheduling module, so that only the first delay submodule in the delay module needs to be delayed to achieve fine adjustment of the delay. Alternatively, the above-mentioned adjustable delay circuit can be used to achieve a delay adjustment with a wide range but slightly lower precision. For example, a fixed high level can be input at the input end of the third adjustment module, and the first adjustment signal and the second adjustment signal can be input at the input end of the first adjustment module and the second adjustment module, so that the delay module can delay according to the first adjustment signal and the second adjustment signal to achieve secondary adjustment of the delay.
[0102] An embodiment of the present application further provides an electronic device, which includes the adjustable delay circuit mentioned in any of the aforementioned embodiments. The corresponding implementation method can refer to the detailed description of the aforementioned adjustable delay circuit, which will not be repeated here.
[0103] It should be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.
[0104] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.
Claims
1. An adjustable delay circuit, characterized in that: include: a first regulating module comprising a first input terminal and a control output terminal, wherein the first regulating module is configured to decode a first regulating signal input from the first input terminal and output a control selection signal from the control output terminal according to a decoding result; a second regulating module comprising a second input terminal and a first output terminal, wherein the second regulating module is configured to perform differential processing on a second regulating signal input from the second input terminal, and output a first pair of differential signals obtained by the differential processing through the first output terminal; a third regulating module, comprising a third input terminal and a second output terminal, wherein the third regulating module is configured to perform differential processing on a third regulating signal input from the third input terminal, and output a second pair of differential signals obtained by the differential processing through the second output terminal; Delay module, including: A signal input terminal, used for receiving a target differential signal pair; a strobe signal input terminal connected to the control output terminal and configured to receive the control strobe signal; a first control terminal, configured to receive the first pair of differential signals; a second control terminal, configured to receive the second pair of differential signals; The delay module is used to delay the target differential signal pair according to the input control selection signal, the first pair of differential signals and the second pair of differential signals; The signal output terminal is used to output the target differential signal pair after being delayed by the delay module.
2. The circuit according to claim 1, wherein: The delay module includes a first delay submodule, N second delay submodules, a first load module and a second load module, wherein: The first control terminal includes: at least one first control sub-terminal and at least one second control sub-terminal, the first control sub-terminal being used to receive one differential signal in the first pair of differential signals, and the second control sub-terminal being used to receive the other differential signal in the first pair of differential signals; The first delay submodule includes the signal input terminal, the second control terminal, the first differential output terminal, and the first differential output positive terminal; Each of the N second delay submodules includes: a second differential input terminal, a second differential output terminal, and a second differential output positive terminal; The second differential output end of the previous second delay submodule in each of the N second delay submodules is connected to the second differential input end of the next second delay submodule, the second differential input end of the first second delay submodule in the N second delay submodules is connected to the first differential output end, and the second differential output end of the last second delay submodule in the N second delay submodules is connected to the second load module; The first differential output positive terminal is connected to the second differential output positive terminals of each of the second delay submodules and then connected to the first load module; The first load module includes the signal output end; One of the first delay submodule and two adjacent delay submodules in the N second delay submodules is further provided with the first control subterminal, and the other delay submodule is further provided with the second control subterminal; Each of the first delay submodule and the N second delay submodules is provided with a strobe signal input terminal for receiving a control strobe signal for controlling whether the corresponding delay submodule is connected to the first control subterminal or the second control subterminal; N is an integer greater than or equal to 1.
3. The circuit according to claim 2, characterized in that The first delay submodule includes a first buffer unit, a phase interpolation unit and a first gating unit; The input end of the first buffer unit includes the signal input end, and the output end is connected to an input end of the phase interpolation unit; One input end of the phase interpolation unit is connected to the output end of the first buffer unit, and the other input end is used to input the target differential signal pair. The control end of the phase interpolation unit includes the second control end, and the output end of the phase interpolation unit is connected to the first differential output end. The input end of the first gating unit is connected to the output end of the phase interpolation unit, the control end of the first gating unit includes a gating signal input end, the output end of the first gating unit includes the first differential output positive end, and the first gating unit also includes the first control sub-end or the second control sub-end; The second delay submodule includes: a second buffer unit and a second gating unit; The input end of the second buffer unit includes the second differential input end, and the output end of the second buffer unit is connected to the second differential output end; The input end of the second gating unit is connected to the output end of the second buffer unit, the control end includes a gating signal input end, the output end of the second gating unit includes the second differential output positive end, and the second gating unit also includes the first control sub-end or the second control sub-end.
4. The circuit according to claim 3, characterized in that The first buffer unit and the second buffer unit respectively include: A first transistor Q1, having a base connected to the input terminal, a collector connected to one end of the first resistor R1, and an emitter connected to the ground via a current source I1; A second transistor Q2 has a base connected to the input terminal, a collector connected to one end of the second resistor R2, and an emitter connected to the ground via a current source I1; A first resistor R1, one end of which is connected to the power supply terminal VCC, and the other end of which is connected to the collector of the first transistor Q1; A second resistor R2, one end of which is connected to the power supply terminal VCC, and the other end of which is connected to the collector of the second transistor Q2; A third transistor Q3, whose base is connected to the collector of the first transistor Q1, the collector is connected to the power supply terminal VCC, and the emitter serves as an output terminal and is grounded through the current source I2; The fourth transistor Q4 has a base connected to the collector of the second transistor Q2, a collector connected to the power supply terminal VCC, and an emitter serving as an output terminal and grounded through the current source I3.
5. The circuit according to claim 3, characterized in that The phase interpolation unit includes: a fifth transistor Q5 , having a base connected to the output end of the first buffer unit, a collector connected to one end of the third resistor R3 , and an emitter connected to the collector of the ninth transistor Q9 ; a sixth transistor Q6 , having a base connected to the output end of the first buffer unit, a collector connected to one end of the fourth resistor R4 , and an emitter connected to the collector of the ninth transistor Q9 ; a seventh transistor Q7, having a base connected to the signal input terminal, a collector connected to one end of the third resistor R3, and an emitter connected to the collector of the tenth transistor Q10; an eighth transistor Q8 , having a base connected to the signal input terminal, a collector connected to one end of the fourth resistor R4 , and an emitter connected to the collector of the tenth transistor Q10 ; a ninth transistor Q9, having a base connected to the third control sub-terminal, a collector connected to the emitters of the fifth transistor Q5 and the sixth transistor Q6, respectively, and an emitter grounded via a current source I4, wherein the second control terminal includes the third control sub-terminal and the fourth control sub-terminal; a thirteenth transistor Q10, whose base is connected to the fourth control sub-terminal, whose collector is respectively connected to the emitter of the seventh transistor Q7 and the emitter of the eighth transistor Q8, and whose emitter is grounded through the current source I4; A third resistor R3, one end of which is connected to the collector of the seventh transistor Q7, and the other end of which is connected to the power supply terminal VCC; The fourth resistor R4 has one end connected to the collector of the eighth transistor Q8 and the other end connected to the power supply terminal VCC.
6. The circuit according to claim 5, characterized in that The phase interpolation unit further includes an emitter follower unit, and the emitter follower unit includes: an eleventh transistor Q11, whose base is connected to the collector of the seventh transistor Q7, the collector is connected to the power supply terminal VCC, and the emitter serves as an output terminal and is grounded through the current source I5; The twelfth transistor Q12 has a base connected to the collector of the eighth transistor Q8 , a collector connected to the power supply terminal VCC, and an emitter serving as an output terminal and grounded through the current source I6 .
7. The circuit according to claim 3, characterized in that The first gating unit and the second gating unit respectively include: A thirteenth transistor Q13 has a base serving as an input terminal and an emitter connected to the collector of a fifteenth transistor Q15; A fourteenth transistor Q14 has a base serving as an input terminal and an emitter connected to the collector of a fifteenth transistor Q15; The collector of the thirteenth transistor Q13 and the collector of the fourteenth transistor Q14 serve as output terminals; A fifteenth transistor Q15 has a base connected to the source of the MOS transistor NM1, a collector connected to the emitter of the thirteenth transistor Q13 and the emitter of the fourteenth transistor Q14, and an emitter grounded; The MOS transistor NM1 has a gate connected to the selection signal input terminal, a source grounded to the base of the fifteenth transistor Q15, and a drain connected to the first control sub-terminal or the second control sub-terminal.
8. The circuit according to any one of claims 1 to 7, characterized in that The first regulating module includes a decoder, the second regulating module includes a 4-bit digital-to-analog converter DAC, and the third regulating module includes a 10-bit digital-to-analog converter DAC.
9. The circuit according to any one of claims 2 to 7, characterized in that N＝7。 10. An electronic device, characterized in that: The invention comprises the adjustable delay circuit according to any one of claims 1 to 9.
Citation Information
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