A method for planarizing a microsystem thin film

Abstract

The present invention discloses a method for planarizing a micro-system thin film. The method for planarizing the micro-system thin film includes: depositing a borophosphosilicate glass layer on a patterned thin film; then, performing rapid thermal annealing and annealing treatment on the borophosphosilicate glass layer; finally, polishing the annealed borophosphosilicate glass layer until the borophosphosilicate glass layer reaches a preset thickness. Through the annealing treatment, the borophosphosilicate glass can effectively flow back, reducing the step difference; at the same time, the doped boron (B) and phosphorus (P) can be repaired at different interfaces to form a uniform concentration; when performing the polishing treatment, due to the higher stability and smaller step difference of the sacrificial layer, the polishing speed can be increased and the polishing amount can be reduced, effectively controlling the thickness, flatness and stability of the sacrificial layer thin film; at the same time, a large amount of CMP consumables such as polishing pads, polishing liquids, trimmers, etc. can be saved, and the output is higher, and the economic benefits are very obvious.

Description

Technical Field

[0001] The present invention relates to the technical field of microsystems, and in particular to a method for planarizing a microsystem thin film. Background Art

[0002] In a capacitive microphone, generally, sound waves act on the thin film of a capacitor. Due to the vibration of the thin film, the distance between the upper and lower electrodes changes, thereby changing the capacitance, and then a corresponding detected electrical signal is obtained. Among them, the distance between the upper and lower substrates formed between the capacitors (the thickness of the sacrificial layer) and the surface flatness (the surface flatness of the sacrificial layer) are particularly important for the sensitivity of the detection signal. The method for manufacturing such a capacitive microphone in the prior art is as follows: thermally oxidize a standard silicon wafer to form a silicon dioxide thin film; then deposit silicon nitride, polysilicon, and silicon nitride on the silicon dioxide thin film in sequence to form a patterned thin film; then, deposit two planarization layers and perform chemical-mechanical planarization (CMP) on the planarization layers to obtain a sacrificial layer; then form the upper and lower electrodes; finally, after releasing the sacrificial layer, a capacitive structure can be formed. During the polishing process of the two deposited planarization layers, since the thickness to be removed is as high as 2 - 3 μm, far exceeding the thickness of silicon dioxide in the IC (Integrated Circuit) thin film process, and it is necessary to ensure that the remaining thickness of silicon dioxide is within the required thickness range. Moreover, during the manufacturing process, it is also required that after CMP, the step difference in the central region of the sacrificial layer is small. However, CMP is a very refined planarization method that achieves high-precision surface planarization through the balance of chemistry and mechanics, and achieves global planarization by removing high points faster than low points. The removal rate is calculated in angstroms, and the typical removal rate of oxides is 2000 Å - 5000 Å. While the thick film process of micro-electro-mechanical systems (MEMS) requires at least removing more than 2 μm, which will result in a polishing time of more than 4 minutes. As a result, a large amount of heat accumulates inside the wafer, which causes the chemical reaction to intensify. It will be difficult to maintain the dynamic balance between the chemical reaction and mechanical removal stable for such a long time. In some low areas, due to the active chemical reaction, large-area chemical erosion will occur, resulting in poor within-wafer non-uniformity (WIWNU), and the thickness is also difficult to control within the specified range. In addition, MEMS generally has a large pattern pitch, and long-term polishing will cause the continuous increase of dishing defects, and it is difficult to effectively ensure the flatness of the central region.

[0003] In summary, it can be seen that the planarization method used in the current manufacturing process of microsystem thin films will make it difficult to control the thickness, flatness, and stability of the sacrificial layer thin film. Summary of the Invention

[0004] An embodiment of the present application provides a method for planarizing a microsystem thin film, which can ensure higher stability of the sacrificial layer, smaller step difference, improve the polishing speed and reduce the polishing amount, so that the thickness, flatness and stability of the sacrificial layer thin film are effectively controlled.

[0005] The present application provides the following technical solutions through an embodiment of the present application:

[0006] A method for planarizing a microsystem thin film, comprising:

[0007] Providing a semiconductor substrate formed with a patterned thin film; depositing a borophosphosilicate glass layer on the patterned thin film; performing rapid thermal annealing and annealing treatment on the borophosphosilicate glass layer; polishing the annealed borophosphosilicate glass layer until the borophosphosilicate glass layer reaches a preset thickness.

[0008] Optionally, depositing the borophosphosilicate glass layer on the patterned thin film includes:

[0009] Depositing a first borophosphosilicate glass layer with a thickness of 2 μm - 3.5 μm on the patterned thin film; depositing a second borophosphosilicate glass layer with a thickness of 2 μm - 3.5 μm on the first borophosphosilicate glass layer.

[0010] Optionally, performing rapid thermal annealing and annealing treatment on the borophosphosilicate glass layer includes:

[0011] Performing rapid thermal annealing treatment at a heating temperature of 800 °C - 850 °C for 5 s - 10 s; performing annealing treatment in a nitrogen environment after the rapid thermal annealing treatment.

[0012] Optionally, the duration of the annealing treatment is not less than 20 seconds.

[0013] Optionally, polishing the annealed borophosphosilicate glass layer until the borophosphosilicate glass layer reaches a preset thickness includes:

[0014] Polishing the annealed borophosphosilicate glass layer with a non-selective ratio polishing liquid until the borophosphosilicate glass layer reaches a preset thickness.

[0015] Optionally, polishing the annealed borophosphosilicate glass layer until the borophosphosilicate glass layer reaches a preset thickness includes:

[0016] Polishing the annealed borophosphosilicate glass layer with silicon dioxide abrasive particles until the borophosphosilicate glass layer reaches a preset thickness.

[0017] Optionally, the polishing time is not more than 3 min.

[0018] Optionally, providing the semiconductor substrate formed with the patterned thin film includes:

[0019] Provide a semiconductor substrate; form an insulating layer on the semiconductor substrate; sequentially deposit a first silicon nitride layer, a polysilicon layer, and a second silicon nitride layer on the insulating layer; etch the first silicon nitride layer, the polysilicon layer, and the second silicon nitride layer to form the patterned thin film.

[0020] Optionally, the polishing abrasive particles used are smoked abrasive particles.

[0021] Optionally, depositing a borophosphosilicate glass layer on the patterned thin film includes:

[0022] Deposit a borophosphosilicate glass layer on the patterned thin film by plasma enhanced chemical vapor deposition.

[0023] One or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0024] An embodiment of the present invention provides a microsystem thin film planarization method. A borophosphosilicate glass layer is deposited on the patterned thin film; then, rapid thermal annealing and annealing treatment are performed on the borophosphosilicate glass layer; finally, the annealed borophosphosilicate glass layer is polished until it reaches a preset thickness. Through the annealing treatment, the borophosphosilicate glass can effectively flow back, reducing the step difference; at the same time, the doped boron (B) and phosphorus (P) can be repaired at different interfaces to form a uniform concentration; when performing the polishing treatment, due to the higher stability and smaller step difference of the sacrificial layer, the polishing speed can be increased and the polishing amount can be reduced, effectively controlling the thickness, flatness, and stability of the sacrificial layer thin film; at the same time, a large amount of CMP consumables can be saved, such as polishing pads, polishing liquids, trimmers, etc., and the output is higher, and the economic benefits are very obvious. Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1 It is a flowchart of the microsystem thin film planarization method provided by the embodiment of the present invention;

[0027] Figures 2 - 8 It is a schematic structural diagram of different manufacturing process stages of a capacitive microphone provided by the embodiment of the present invention. Detailed Embodiments

[0028] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

[0029] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art can additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0030] In the context of the present disclosure, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component.

[0031] Please refer to Figure 1 , a micro-system thin-film planarization method provided in the present invention can be used for fabricating similar thin films in various micro-systems and for planarizing the thin films; for example, it can be applied to the manufacturing processes of micro-systems such as pressure sensors and capacitive microphones. The micro-system thin-film planarization method in the present invention will be described below with an embodiment of manufacturing a capacitive microphone. During the process of manufacturing a capacitive microphone, it is necessary to deposit PSG (phosphosilicate glass) twice by PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma-enhanced chemical vapor deposition). After the deposition is completed, the step difference of the phosphosilicate glass reaches 1.2 um, and the total film thickness is more than 6 um; however, the final required thickness is 4 um - 4.5 um, and the remaining thickness range needs to be controlled within ±0.2 um, and the step difference in the graphic area is less than ±0.1 um. Since the thickness of the removed film layer is relatively thick, if grinding is carried out for a long time, a large amount of heat will accumulate, resulting in defects in the wafer.

[0032] Please refer to Figures 2 - 8 , which shows structural schematic diagrams formed at different stages of a capacitive microphone manufacturing method in this embodiment. Among them, the structure formed by the process flow of the micro-system thin-film planarization method can be used to process the planarization layer 400 (sacrificial layer) in the process flow of manufacturing a capacitive microphone. To avoid the above problems and suppress the generation of new defects. The specific step flow is as follows:

[0033] Provide a semiconductor substrate 10, which can be a silicon substrate, sapphire, silicon carbide, gallium nitride, etc., without limitation. Then, form an insulating layer 20 on the semiconductor substrate 10; for example, taking a silicon substrate as an example, the silicon substrate can be oxidized to form a silicon dioxide thin film layer on the silicon substrate, as Figure 2 shown. The thickness of the insulating layer 20 is approximately 0.5 μm. Then, deposit a first silicon nitride layer 31 on the insulating layer 20, and then deposit a doped polysilicon layer 32 on the first silicon nitride layer 31 by using Low Pressure Chemical Vapor Deposition (LPCVD), and then deposit a second silicon nitride layer 33 on the polysilicon layer 32. After the deposition is completed, perform patterning etching on the first silicon nitride layer 31, the polysilicon layer 32, and the second silicon nitride layer 33 to form a patterned thin film 30, as Figure 3 shown. The groove shape and size on the patterned thin film 30 are not limited.

[0034] The above process can also be replaced by other solutions in the prior art, without limitation.

[0035] Immediately afterwards, deposit a planarization layer 400 (sacrificial layer) on the patterned thin film. In this embodiment, borophosphosilicate glass (BPSG) is used as the material of the planarization layer 400, that is, deposit a borophosphosilicate glass layer 40 on the patterned thin film; during the deposition process, Plasma Enhanced Chemical Vapor Deposition (PECVD) process can be used to fabricate a first borophosphosilicate glass layer 41 with a thickness of 2 μm - 3.5 μm, as Figure 4 shown; then, use the PECVD process to fabricate a second borophosphosilicate glass layer with a thickness of 2 μm - 3.5 μm, so that the total thickness of the borophosphosilicate glass layer 40 reaches 4 μm - 7 μm, as Figure 5 shown. The thickness control is achieved by depositing the same thickness twice; of course, during the two deposition processes, the thickness of the two depositions can also be adjusted according to the process level or production requirements; in addition, the number of depositions is not limited to two, and 1 deposition can also be performed under feasible process conditions, without limitation.

[0036] After that, the borophosphosilicate glass layer 40 is subjected to rapid thermal processing (RTP) and annealing treatment. During the rapid thermal annealing treatment, the heating temperature can be controlled at 800°C to 850°C, and the duration is 5 - 10 s to ensure good reflow of the borophosphosilicate glass. After the rapid thermal annealing treatment, the annealing treatment is carried out in a nitrogen environment, and the duration of the annealing treatment can be greater than or equal to 20 s. Since in this embodiment, when fabricating the planarization layer 400, the BPSG material is used to replace the PSG material in the prior art solution, the water absorption characteristics generated by the PSG material after manufacturing can be avoided, which may cause the film quality to become poor and unstable; while the BPSG material can overcome the water absorption characteristics of PSG. At the same time, since the PSG material can only achieve reflow at a temperature not less than 1100°C, while the BPSG material can achieve reflow at 850°C, the thermal budget is less. Therefore, by using the BPSG material, better reflow and more stable film quality can be achieved, the surface of the borosilicate glass layer can be made flatter after rapid annealing treatment, with a smaller step difference, reducing the thickness and time of grinding and polishing.

[0037] Moreover, in the traditional process, since the planarization layer 400 formed by multiple depositions using the PSG material is not subjected to rapid thermal annealing treatment, during wet etching, even if there is a slight difference in the deposited phosphorus (P) concentration at the place of two depositions, obvious steps are easily formed here during wet etching, resulting in a significant decrease in the yield. After using the BPSG material and performing rapid thermal annealing treatment, not only can the surface be preliminarily planarized, but also the doped B and P can be repaired at different interfaces to form a uniform concentration. The inclined surface obtained by wet etching can be more stable and reliable.

[0038] After completing the rapid thermal annealing and annealing treatment, the annealed borophosphosilicate glass layer 40 is polished until the borophosphosilicate glass layer 40 reaches a preset thickness; the preset thickness can be controlled at 4 μm to 5 μm and can be adjusted as needed. During polishing, chemical mechanical polishing (CMP) is used; specifically, non-selective ratio silica latex can be used for polishing, and the particle size of the silica grinding particles can be controlled at 30 nm - 80 nm, such as 40 nm, 45 nm, 50 nm, etc. At the same time, a filtering device with a filtering diameter of 1 μm is configured to prevent surface scratches under high pressure and high rotation speed. The polishing head adopts multi-region pressure control (the number of independent control regions ≥ 3) and controllable maintaining ring pressure technology. At the same time, silica grinding particles with a small particle size and a round surface are used. Compared with fumed grinding particles, it not only has a faster removal rate but also fewer defects, ensuring a removal rate ≥ 0.9 μm / min, and the intra-wafer non-uniformity ≤ 5%. The total removal amount is about 2 - 3 μm, and the total time can be controlled within 3 minutes.

[0039] During the polishing process, through the above operation process, a large amount of heat accumulation inside the wafer can be avoided, which may otherwise cause the chemical reaction to intensify. This ensures the stability of the dynamic balance between the chemical reaction and mechanical removal, prevents large-area chemical erosion in the low areas during the polishing process, improves the within-wafer non-uniformity (WIWNU), and makes the thickness easier to control. In addition, in this embodiment, since the polishing time can be controlled within 3 minutes, the dishing defect will not continuously increase due to the large spacing between patterns in the microsystem, and the flatness of the central area can be effectively guaranteed, as Figure 6 shown.

[0040] In the existing traditional solutions, the key components of the chemical mechanical planarization equipment, namely the polishing head and the polishing table, both use rotation to remove the corresponding materials. During the actual operation, the rotational speed, that is, the angular velocity, is controlled, but the removal amount is related to the linear velocity (Preston equation: MRR = KPV, where P is the sum of the pressures borne by the wafer, and V is the vector sum of the linear velocities of the wafer at this point). Therefore, the removal amount of the edge part of the wafer is significantly faster than that of other regions; even if multi-region pressure control of the polishing head is adopted, due to long-term polishing, the accuracy and stability of compensation also face great challenges; excessive removal amount of the edge part leads to chip failure in the effective regions of the surrounding areas. In this embodiment, by replacing the PSG material with the BPSG material, performing rapid thermal annealing treatment after depositing the planarization layer 400, and adopting multi-region ring pressure control during polishing, the polishing time can be effectively shortened, and the product stability can be guaranteed.

[0041] In this embodiment, the Nova on-line thickness control technology can also be adopted during the polishing process. If the total removal amount is insufficient, an appropriate polishing time is increased; in this way, the between-wafer non-uniformity can be guaranteed. However, the optical endpoint detection (infrared or visible light) technology used in the existing technology is difficult to be effective for ultra-thick film layers, and reaching the specified thickness can only be achieved by time, resulting in poor between-wafer non-uniformity (WTWNU).

[0042] Finally, a diaphragm layer 50 is formed, and the planarization layer 400 is released to form cavity structures, upper electrodes, lower electrodes and other structures. The process of forming cavity structures, upper electrodes, lower electrodes and other structures can adopt existing mature processes, which are not limited in this embodiment. For example, a doped polysilicon diaphragm layer 50 is formed on the planarization layer 400 by LPCVD, and then wet etching is performed to form a smooth and stable side surface, as Figure 7 shown; finally, upper and lower electrodes are formed (the polysilicon diaphragm layer 50 forms the upper electrode, and the polysilicon layer 32 forms the lower electrode), and the planarization layer 400 is released to form a cavity structure to complete the manufacture of the capacitive microphone, as Figure 8 shown.

[0043] It should be noted that the flat layer 400 to be processed in this embodiment may correspond to other thin film layers in other products, such as other sacrificial layers, diaphragm layers, insulating layers, etc., without limitation.

[0044] In summary, a method for planarizing a micro-system thin film provided in an embodiment of the present invention includes depositing a borophosphosilicate glass layer on a patterned thin film; then, performing rapid thermal annealing and annealing treatment on the borophosphosilicate glass layer; and finally, polishing the annealed borophosphosilicate glass layer until the borophosphosilicate glass layer reaches a preset thickness. Through the annealing treatment, the borophosphosilicate glass can be effectively refluxed to reduce the step difference; at the same time, the doped boron (B) and phosphorus (P) can be repaired at different interfaces to form a uniform concentration. When performing the polishing treatment, since the flat layer has higher stability and smaller step difference, the polishing speed can be increased and the polishing amount can be reduced, so that the thickness, flatness and stability of the flat layer (sacrificial layer) thin film can be effectively controlled; at the same time, a large amount of CMP consumables, such as polishing pads, polishing liquids, trimmers, etc., can be saved, and the output is higher, and the economic benefits are very obvious.

[0045] In the above description, technical details such as the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the required shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. In addition, although the above embodiments are described separately, this does not mean that the measures in each embodiment cannot be used in combination advantageously.

[0046] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0047] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A method for planarizing a microsystem thin film, characterized in that, Including: Providing a semiconductor substrate formed with a patterned thin film; Depositing a borophosphosilicate glass layer on the patterned thin film; Performing rapid thermal annealing and annealing treatment on the borophosphosilicate glass layer; Polishing the annealed borophosphosilicate glass layer until the borophosphosilicate glass layer reaches a preset thickness; The depositing a borophosphosilicate glass layer on the patterned thin film includes: Depositing a first borophosphosilicate glass layer with a thickness of 2 um - 3.5 um on the patterned thin film; Depositing a second borophosphosilicate glass layer with a thickness of 2 um - 3.5 um on the first borophosphosilicate glass layer; The performing rapid thermal annealing and annealing treatment on the borophosphosilicate glass layer includes: Performing rapid thermal annealing treatment at a heating temperature of 800 °C - 850 °C for 5 s - 10 s; Performing annealing treatment in a nitrogen environment after the rapid thermal annealing treatment, and the duration of the annealing treatment is not less than 20 seconds.

2. The method according to claim 1, wherein The polishing the annealed borophosphosilicate glass layer until the borophosphosilicate glass layer reaches a preset thickness includes: Polishing the annealed borophosphosilicate glass layer with a non-selective polishing liquid until the borophosphosilicate glass layer reaches a preset thickness.

3. The method according to claim 1, wherein The polishing the annealed borophosphosilicate glass layer until the borophosphosilicate glass layer reaches a preset thickness includes: Polishing the annealed borophosphosilicate glass layer with silicon dioxide abrasive particles until the borophosphosilicate glass layer reaches a preset thickness.

4. The method according to claim 1, wherein The polishing time is not more than 3 min.

5. The method according to claim 1, wherein The providing a semiconductor substrate formed with a patterned thin film includes: Providing a semiconductor substrate; Forming an insulating layer on the semiconductor substrate; Sequentially depositing a first silicon nitride layer, a polysilicon layer, and a second silicon nitride layer on the insulating layer; Etching the first silicon nitride layer, the polysilicon layer, and the second silicon nitride layer to form the patterned thin film.

6. The method according to claim 1, characterized in that The abrasive particles used for polishing are smoked abrasive particles.

7. The method according to claim 1, characterized in that, The depositing a borophosphosilicate glass layer on the patterned thin film includes: Depositing a borophosphosilicate glass layer on the patterned thin film by plasma-enhanced chemical vapor deposition.

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