A SiC chip testing method based on UIS

Abstract

A method for testing SiC chips based on UIS. This method relates to a semiconductor device testing method. The method comprises the following steps: S100, performing electrical testing on the silicon carbide power device to be tested, then selecting a number of silicon carbide power devices that have passed the electrical testing and performing UIS limit capability tests at room temperature, respectively, to obtain the corresponding UIS limit capability values, and calculating the average UIS limit capability test value, which is recorded as E max ; S200, first test: set the energy of UIS limit capacity test to E max 25%-30%; S300, second test: set the energy of UIS test to E max 20%-25% of, S400, N-1 test: Set the energy of the UIS test to E max This step can reduce the defect density to less than 0.1 cm ‑2 , even lower dies are screened out; S500, Nth test: set the energy of UIS test to E max The final retest ensures that all potential risk dies are stimulated in advance; it more effectively solves the PPM-level failure problem of SiC power devices at the reliability end.

Description

Technical Field

[0001] The present invention relates to a semiconductor device testing method, and in particular to a SiC chip testing method based on UIS. Background Art

[0002] Compared with traditional power devices and semiconductor materials, SiC materials have advantages such as high bandgap, high critical breakdown field strength, high electron saturation rate and high thermal conductivity. The high bandgap makes SiC power devices have excellent ability to withstand high temperatures and radiation; the high breakdown field strength makes the breakdown field strength of SiC power devices about 2-4 MV / cm, which is about 10 times that of traditional Si devices; the carrier drift in SiC materials is very high, about 2.0x10 7 cm / s, which makes the SiC power device able to withstand a very high limit frequency; the high thermal conductivity allows the generated heat to quickly diffuse from the surface of the device active area to the package interface, giving the device excellent heat dissipation performance. Due to the advantages of high breakdown field strength and high thermal conductivity, SiC materials and power devices are more adaptable to high temperature and reverse bias high voltage environments than Si devices.

[0003] As a key component of power electronics, SiC power devices have reached a critical mass in terms of market size and research capabilities. Furthermore, in today's globalized world, with advancements in theoretical design and process technology, the market continues to expand. SiC power devices are being widely used in applications such as DC voltage converters, aerospace, and electric vehicles, placing increasingly stringent demands on their reliability. In recent years, the reliability of SiC power devices under reverse avalanche conditions, forward surge conditions, high temperatures, and reverse bias stress has garnered widespread attention. In actual applications, silicon carbide power devices have been found to exhibit reliability failures. Long-term exposure to high-temperature reverse bias can lead to severe performance degradation, threatening the stability of the entire power system. Therefore, improving the reliability of SiC power devices in applications is crucial. Addressing the PPM-level failures of SiC power devices, in particular, has become a major challenge for the entire industry.

[0004] During the manufacturing and packaging process of silicon carbide chips, some products may exhibit poor performance due to inherent material defects and process variations. This is particularly true of screwing dislocations (TSDs), which penetrate the epitaxial layer from the substrate. These defects increase the reverse leakage current of the device, impacting both product performance and reliability. Furthermore, die containing TSDs are difficult to detect through conventional electrical testing, posing a significant risk of failure during reliability testing. When the device is subjected to a reverse bias voltage for an extended period, TSDs introduced in the substrate can extend to the epitaxial surface, forming a leakage path. When the leakage current reaches a certain level, reverse breakdown failure occurs. Summary of the Invention

[0005] In response to the above problems, the present invention provides a UIS-based SiC chip testing method that can stimulate potential risks of products in advance through gradient UIS testing, thereby solving the PPM-level failure problem of SiC power devices at the reliability end.

[0006] The technical solution of the present invention is: a SiC chip testing method based on UIS, comprising the following steps:

[0007] S100, conduct electrical testing on the silicon carbide power device to be tested, and then select several silicon carbide power devices from the products that pass the electrical testing to conduct UIS limit capability tests at room temperature, test the corresponding UIS limit capability values, and calculate the average UIS limit capability test value, which is recorded as E max ;

[0008] S200, first test:

[0009] Set the energy of UIS extreme capability test to E max 25%-30% of the total defect density; through the 25%-30% Emax UIS test, the TSD defects with a size of less than 10 microns in the epitaxial layer of the silicon carbide power device are stimulated in advance, and the TSD defect density in the epitaxial layer is greater than 0.5cm -2 The die are screened out; however, the defect density is between 0.1-0.5cm -2 The dies within the range will be damaged after this test, which will reduce the energy they can withstand in the UIS test;

[0010] S300, second test:

[0011] Set the energy of the UIS test to E max 20%-25% of the defect density in step S200 is 0.1-0.5cm -2 The tube cores within the range are screened out;

[0012] S400, N-1th test:

[0013] Set the energy of the UIS test to E max This step can reduce the defect density to less than 0.1 cm -2 , even lower die are screened out;

[0014] S500, Nth test:

[0015] Set the energy of the UIS test to E max 5% of the total, the final retest to ensure that all potential risk dies are stimulated in advance;

[0016] Furthermore, the number of silicon carbide power devices to be tested is no less than 10.

[0017] Furthermore, the electrical property test in step S100 includes whether the values ​​of the rated voltage and the current meet the set values.

[0018] The present invention has the advantages that before the SiC power device undergoes reliability verification, it first undergoes a UIS test with the test energy set at 25%-30%E max , can reduce UIS capacity to less than 25%-30%E max Products are screened in advance to increase the pass rate of reliability test. However, after a UIS test, not all potential defective products can be completely stimulated. There are still some products with poor performance that may have the risk of failure in reliability verification. Because these weaker performance dies have passed the 30% E max During the UIS test, a few chips will also be damaged to a certain extent, making their ability to withstand UIS less than 5%E max UIS capability is less than 5%E max The risk of die failure during reliability testing is high. Therefore, the present invention proposes a method of using multiple gradient UIS tests, with the energy distribution of the test being 30% -5% E max , the energy of the first test is 25%-30%E max , the energy of the intermediate test is 10%-25%E max , the energy of the last two tests was 5%E max , because 5%E max The test energy is low and will not cause any damage to the chip. The penultimate test can reduce the energy level to less than 5% of the previous test level. max Filtered out, and the last 5%E max UIS testing will not cause material degradation. After 4-6 gradient UIS tests, almost all products with potential risks can be stimulated in advance, which more effectively solves the PPM-level failure problem of SiC power devices on the reliability side. DETAILED DESCRIPTION

[0019] In view of the above problems, the present invention proposes a method to improve the reliability of SiC. On the basis of not damaging the performance of the product itself, a 25%-30% UIS limit test (E max Most of the TSD defects hidden in SiC epitaxy originate from the interface between the substrate and the epitaxial layer, and grow along the [11-20] crystal direction. The defect length L can be expressed as L=d / Sin(θ), where d is the thickness of the SiC epitaxial layer and θ is the deflection angle of the SiC substrate along the [11-20] direction. When the thickness of SiC epitaxy in the industry is 5-15 microns, the size of the TSD defect is generally less than 10 microns. 25%-30%E max UIS testing can stimulate TSD defects with a size of less than 10 microns in the epitaxy in advance. Excessive energy may cause greater damage to normal chips, and low energy cannot stimulate defects. This can screen out products with weaker performance in advance, thereby improving the pass rate of samples in the reliability test process to a certain extent.

[0020] However, a small number of die still fail during reliability assessments, and the PPM-level failure problem cannot be completely resolved. To address this issue, the present invention proposes a solution using multiple gradient UIS tests, which can preemptively identify all weaker products, thereby improving product reliability at the application end.

[0021] The multiple gradient UIS test refers to 4-6 UIS tests in advance, with the energy of the first test being 25%-30% E max , the energy of the last two tests was 5% E max , the energy of the intermediate test is 5%-20% E max .

[0022] A UIS-based SiC chip testing method comprises the following steps:

[0023] S100, conduct electrical testing on the silicon carbide power device to be tested, and then select several silicon carbide power devices from the products that pass the electrical testing to conduct UIS limit capability tests at room temperature, test the corresponding UIS limit capability values, and calculate the average UIS limit capability test value, which is recorded as E max ;

[0024] S200, first test:

[0025] Set the energy of UIS extreme capability test to E max Through the 25%-30% Emax UIS test, the TSD defects with a size of less than 10 microns in the epitaxial layer of the silicon carbide power device are stimulated in advance, thereby reducing the TSD defect density in the epitaxial layer to more than 0.5cm-2 The die are screened out; however, the defect density is between 0.1-0.5cm -2 The dies within the range will be damaged after this test, which will reduce the energy they can withstand in the UIS test;

[0026] Most TSD defects in SiC epitaxy originate from the interface between the substrate and the epitaxial layer, and grow regularly along the [11-20] crystal direction. The defect length L can be expressed as L=d / Sin(θ), where d is the thickness of the SiC epitaxial layer and θ is the deflection angle of the SiC substrate along the [11-20] direction. When the thickness of SiC epitaxy in the industry is 5-15 microns, the size of TSD defects is generally less than 10 microns. The 25%-30%Emax UIS test can stimulate TSD defects with a size of less than 10 microns in the epitaxy in advance. Excessive energy will cause greater damage to the entire chip, and low energy cannot stimulate defects. According to the UIS energy calculation formula E = ½I 2 L determines the inductance L and the test current I for the first UIS test; since the Emax values ​​of products of different specifications may be different, in the present invention, the test inductance L of the tube core with a current less than 10A is set to 5mH, and the test inductance L of the tube core with a current greater than 10A is set to 10mH. The test current I can be calculated according to the above formula. The above step can reduce the TSD defect density in the epitaxial layer to more than 0.5cm -2 The dies are screened out, but the defect density of a few is in the range of 0.1-0.5cm -2 After this test, the chip will also be damaged to a certain extent, which will reduce the energy it can withstand in the UIS test. The energy borne by a few chips will be less than 5% E max ,These dies need the next step of screening test;

[0027] S300, second test:

[0028] Set the energy of the UIS test to E max 20%-25% of the defect density in step S200 is 0.1-0.5cm -2 The tube cores within the range are screened out;

[0029] According to the UIS energy calculation formula E = ½I 2 L determines the inductance L and the test current I to perform the second UIS test; in the present invention, the damaged die in step S200 is screened out, and the energy of the test is lower than the energy of the test in the previous step, because the normal die continuously passes through 25%-30% E max The impact of energy will also cause damage, so the energy is reduced in sequence until the energy of the last two steps is 5% E max ;

[0030] S400, N-1th test:

[0031] Set the energy of the UIS test to E max This step can reduce the defect density to less than 0.1 cm -2 , even lower die are screened out;

[0032] S500, Nth test:

[0033] Set the energy of the UIS test to E max 5% of the total, the final retest to ensure that all potential risk dies are stimulated in advance;

[0034] Furthermore, in step S100, the number of silicon carbide power devices to be tested is no less than 10.

[0035] Furthermore, the electrical property test in step S100 includes whether the values ​​of the rated voltage and the current meet the set values.

[0036] Case 1:

[0037] The high-temperature reverse bias (HTRB) test is an accelerated lifetime aging test that applies a high reverse voltage to devices in a high-temperature environment for 168 hours, 500 hours, and 1000 hours. After HTRB testing, some damaged die can experience increased leakage, degraded reverse blocking performance, and even reverse breakdown in severe cases. Therefore, HTRB is often used to verify the reliability of power devices. This solution primarily targets a range of power devices, including silicon carbide (SiC) JBS, SBDs, MPSs, and MOSFETs. A domestically produced 650V, 6A SiC JBS diode is used as an example. Prior to HTRB reliability testing, these devices undergo five gradient UIS tests. This preemptive screening of defective products ensures a high pass rate for HTRB verification. To enhance comparability, four sets of experiments were conducted for comparative verification.

[0038] The UIS test conditions of experimental group 1 are: 30% E max , 20% E max 、10% E max , 5% E max , 5% E max UIS test;

[0039]

[0040] The test condition of experimental group 2 was 30% E max , 20% E max 、10% E maxUIS test;

[0041]

[0042] The test condition of experimental group 3 was 30%E max UIS test;

[0043]

[0044] Experimental group 4 was not tested with UIS.

[0045] Each experimental group consisted of 231 samples. After UIS testing, the samples in each group were placed in a 650V, 175°C environment for 1000 hours of HTRB reliability verification. The number of HTRB failures in each group was counted and analyzed in detail.

[0046] The overall implementation steps are as follows: First, a small number of samples are selected for static electrical testing at room temperature. Ten products with good static electrical properties are selected for UIS limit testing (testing inductance of 2mH) to obtain the UIS limit values ​​of the samples. The specific data is shown in Table 2 below:

[0047]

[0048] Since the test data is relatively discrete, the average value is selected as the E max Before HTRB reliability verification, each group of experimental samples underwent several UIS screening tests, of which 30% E max , 20% E max 、10% E max , 5%E max The inductors are 1mH, 0.5mH, 0.5mH and 0.5mH respectively. After each UIS test, each group of experimental samples will have a certain reduction ratio. A small number of products with poor performance can be screened out in advance to reduce the risk of failure in reliability testing.

[0049] The samples in experimental group 3 were treated once with 30% E max The test can only screen out 5 products with poor performance;

[0050] Experimental Group 2 produced 14 defective products after three UIS tests. Compared with Experimental Group 3, it can stimulate more potential defective products in advance.

[0051] Experimental group 1 was tested 5 times by UIS. max During the test, no material degradation occurred, indicating that after three UIS tests, a very small number of products in Experimental Group 2 still had the risk of failure in the HTRB assessment.

[0052] Each group of products that passed the UIS screening test was numbered and placed in a 650V, 175°C environment for HTRB reliability assessment. The experimental results are shown in Table 6 below:

[0053]

[0054] It can be seen that after four UIS tests, the products of experimental group 1 did not show any degradation after the 1000-h HTRB assessment, and all products passed the HTRB test. After the 1000-h HTRB test, the products of experimental groups 2 and 3 had one and two failed samples respectively, and after inspection, they were all in the reverse breakdown state. After the HTRB test, all products of experimental group 4 produced five failed products. This shows that after multiple gradient UIS tests, products with poor performance can be screened out in advance, thereby reducing the risk of failure during the HTRB assessment process and improving product reliability.

[0055] Case 2:

[0056] This case selected a 1200V, 20A silicon carbide MPS diode as the test object. Before conducting the HTRB assessment on this product, it was also subjected to five gradient UIS tests. Three sets of experiments were set up for comparative verification:

[0057] The UIS test conditions of experimental group 1 are as follows: 30% E max , 20% E max 、10% E max , 5% E max , 5% E max ;

[0058]

[0059] The test condition of experimental group 2 was 30% E max , 20% E max 、10% E max ;

[0060]

[0061] The test condition of experimental group 3 was 30% E max .

[0062]

[0063] Each experimental group consisted of 231 samples. After UIS testing, the samples in each group were placed in a 1200 V bias and 175°C environment for 1000 hours of HTRB reliability verification. The number of HTRB failures in each group was counted and analyzed in detail.

[0064] The overall implementation steps are as follows: First, a small number of samples were selected for static electrical testing at room temperature. Ten products with good static electrical properties were selected for UIS limit testing (test inductance was 30mH) to obtain the UIS limit values ​​of the samples. The specific data is shown in Table 7 below:

[0065]

[0066] Because the test data is relatively discrete, the average value is selected as the Emax of the product. Before the HTRB reliability verification, each group of experimental samples underwent several UIS screening tests. The inductances of the 30% Emax, 20% Emax, 10% Emax, and 5% Emax were 11mH, 7.3mH, 5.2mH, and 3.7mH, respectively. After each UIS test, each group of experimental samples produced a certain proportion of defective products, all of which were performance-defective products. Experimental Group 3 only screened out 4 defective products after one 30% UIS test. Experimental Group 2 produced 8 defective products after three UIS tests, which may have stimulated more defective products. However, Experimental Group 1, after five UIS tests, also produced 1 defective product in the fourth test. This indicates that the three UIS tests in Experimental Group 2 were not able to completely screen out all defective products, and a small number of products may still be at risk of failure.

[0067] Each group of products was numbered and placed in a 1200V, 175°C environment for HTRB reliability testing. The experimental results are shown in Table 11 below:

[0068]

[0069] It can be seen that after the 1000-h HTRB assessment, the products of Experimental Group 1, which had undergone 5 UIS tests, showed no degradation. All products passed the HTRB test. After the 1000-h HTRB test, the products of Experimental Groups 2 and 3 had 1 and 3 failed samples respectively. After inspection, all were in the reverse breakdown state. This shows that after multiple UIS tests, almost all products with poor performance can be screened out in advance, thereby reducing the risk of failure during the HTRB assessment process and improving product reliability.

[0070] The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A SiC chip testing method based on UIS, characterized in that: The following steps are involved: S100, conduct electrical testing on the silicon carbide power device to be tested, and then select several silicon carbide power devices from the products that pass the electrical testing to conduct UIS limit capability tests at room temperature, test the corresponding UIS limit capability values, and calculate the average UIS limit capability test value, which is recorded as E max ; S200, first test: Set the energy of UIS extreme capability test to E max 25%-30% of the total defect density; through the 25%-30% Emax UIS test, the TSD defects with a size of less than 10 microns in the epitaxial layer of the silicon carbide power device are stimulated in advance, and the TSD defect density in the epitaxial layer is greater than 0.5cm -2 The die are screened out; however, the defect density is between 0.1-0.5cm -2 The dies within the range will be damaged after this test, which will reduce the energy they can withstand in the UIS test; The inductor L for the tube core test with a current less than 10A is set to 5mH, and the inductor L for the tube core test with a current greater than 10A is set to 10mH; S300, second test: Set the energy of the UIS test to E max 20%-25% of the defect density in step S200 is 0.1-0.5cm -2 The tube cores within the range are screened out; S400, N-1th test: Set the energy of the UIS test to E max This step can reduce the defect density to less than 0.1 cm -2 , even lower die are screened out; S500, Nth test: Set the energy of the UIS test to E max 5% of the total, the final retest ensures that all potential risk dies are stimulated in advance.

2. A SiC chip testing method based on UIS according to claim 1, characterized in that: In step S100 , the number of silicon carbide power devices to be tested selected is no less than 10.

3. The UIS-based SiC chip testing method according to claim 1, characterized in that: The electrical property test in step S100 includes checking whether the values ​​of the rated voltage and the current meet the set values.

Images