Reflective mask and method of manufacturing the same

Abstract

A reflective mask and a method of manufacturing the same, the reflective mask including a substrate, a lower reflective multilayer disposed above the substrate, an intermediate layer disposed above the lower reflective multilayer, an upper reflective multilayer disposed above the intermediate layer, a capping layer disposed above the upper reflective multilayer, and an absorber layer disposed in a trench formed in the upper reflective layer and above the intermediate layer. The intermediate layer includes a metal other than chromium, ruthenium, silicon, a silicon compound, and carbon.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a reflective mask and a method of manufacturing the same. BACKGROUND

[0002] Optical lithography is one of the key operations in semiconductor manufacturing processes. Optical lithography technologies include ultraviolet lithography, deep ultraviolet lithography, and extreme ultraviolet lithography (EUVL). A mask is an important component in optical lithography operations. It is crucial to manufacture an EUV mask with high contrast of high-reflectivity portions and high-absorption portions. SUMMARY

[0003] According to some embodiments of the present disclosure, a reflective mask includes a substrate; a lower reflective multilayer disposed above the substrate; an intermediate layer disposed above the lower reflective multilayer; an upper reflective multilayer disposed above the intermediate layer; a capping layer disposed above the upper reflective multilayer; and an absorption layer disposed in a trench formed in the upper reflective layer and above the intermediate layer, wherein the intermediate layer comprises a metal other than chromium, ruthenium, silicon, silicon compound, and carbon.

[0004] According to some embodiments of the present disclosure, a method of manufacturing a reflective mask includes the following steps. A photoresist layer is formed above a blank mask, the blank mask comprising a substrate, a lower reflective multilayer disposed above the substrate, an intermediate layer disposed above the lower reflective multilayer, an upper reflective multilayer disposed above the intermediate layer, a capping layer disposed above the upper reflective multilayer, and a hard mask layer disposed above the capping layer; the photoresist layer is patterned; the hard mask layer is patterned by using the patterned photoresist layer; the capping layer and the upper reflective multilayer are patterned by using the patterned hard mask layer to form a trench pattern; an absorption layer is formed in the trench pattern; and after forming the absorption layer, the hard mask layer is removed so that the absorption layer protrudes from an upper surface of the capping layer.

[0005] According to some embodiments of the present disclosure, a method of manufacturing a reflective mask includes the following steps. Forming a photoresist layer over a blank mask, the blank mask including a substrate, a lower reflective multilayer disposed over the substrate, an intermediate layer disposed over the lower reflective multilayer, an upper reflective multilayer disposed over the intermediate layer, a cover layer disposed over the upper reflective multilayer, and a hard mask layer disposed over the cover layer; patterning the photoresist layer; patterning the hard mask layer using the patterned photoresist layer; patterning the cover layer and the upper reflective multilayer using the patterned hard mask layer to form a trench pattern; and forming a protective layer in the trench pattern, wherein the protective layer is transmissive to extreme ultraviolet light. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Figure One Best understood from the following detailed description when read with the accompanying drawings.

[0007] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , and Figure 6 shows a cross-sectional view of an EUV mask according to an embodiment of the present disclosure;

[0008] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E , and Figure 7F illustrates a sequential method of manufacturing an EUV mask according to an embodiment of the present disclosure;

[0009] Figure 8A , and Figure 8B illustrates a sequential method of manufacturing an EUV mask according to an embodiment of the present disclosure;

[0010] Figure 9A , and Figure 9B illustrates a sequential method of manufacturing an EUV mask according to an embodiment of the present disclosure;

[0011] Figure 10A , Figure 10B , and Figure 10C illustrates a sequential method of manufacturing an EUV mask according to an embodiment of the present disclosure;

[0012] Figure 11A , and Figure 11BFIG. 1 illustrates a method of manufacturing an EUV mask according to an embodiment of the present disclosure;

[0013] Figure 12 FIG. 2 illustrates a flowchart of a method of manufacturing a blank reflective mask according to an embodiment of the present disclosure;

[0014] Figure 13A and Figure 13B FIG. 3 illustrates a blank EUV mask according to an embodiment of the present disclosure and Figure 13C FIG. 4 illustrates an EUV mask according to an embodiment of the present disclosure;

[0015] Figure 14A FIG. 5 illustrates a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure, Figure 14B 、 Figure 14C 、 Figure 14D and Figure 14E FIG. 6 illustrates sequential manufacturing operations of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0016] [SYMBOL EXPLANATION]

[0017] 5: blank EUV reflective mask

[0018] 10: substrate

[0019] 15: reflective multilayer structure / multilayer stack

[0020] 15U: upper layer

[0021] 15L: lower layer

[0022] 20: capping layer

[0023] 22: trench

[0024] 25: absorbing layer

[0025] 27: protective layer

[0026] 30: hard mask layer

[0027] 35: first photoresist layer

[0028] 40: pattern

[0029] 42: trench pattern

[0030] 45: backside conductive layer

[0031] 50: intermediate layer

[0032] 57: black border pattern

[0033] D1: depth

[0034] D2: height

[0035] D3: depth

[0036] S101: step

[0037] S102: step

[0038] S103: step

[0039] S104: step

[0040] S105: step

[0041] S201: step

[0042] S202: step

[0043] S203: step

[0044] S204: step

[0045] X1, X2, Y1, Y2: size DETAILED DESCRIPTION

[0046] It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different characteristics of the disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the dimensions of the elements can not be to scale with one another but can be larger or smaller, as can be desired in a particular implementation depending on, among other things, the desired properties of the device. In addition, the formation of a first feature over or on a second feature in the following description can include embodiments where the first feature is formed in direct contact with the second feature, and can also include embodiments where additional features can be formed between the first and second features such that the first and second features can not be in direct contact. For simplicity and clarity, various features can be drawn to different scales in the various drawings.

[0047] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Moreover, the term "from" can mean "comprising" or "consisting of." In the present disclosure, the phrase "one of A, B, and C" means "A, B, and / or C" (A, B, C, A and B, A and C, B and C, or A, B, and C), and does not mean one element from A, one element from B, and one element from C, unless otherwise described. Materials, configurations, processes, and / or dimensions explained in relation to one embodiment can be employed in other embodiments, and detailed descriptions thereof can be omitted. In the present disclosure, the phrase "a layer is made of or includes a material M" (M is an atomic element) means that the layer is made of only the material M with a purity of more than 99%, and does not mean any alloy or compound unless otherwise stated.

[0048] Embodiments of the present disclosure provide a method of manufacturing an EUV mask. More specifically, the present disclosure provides techniques to prevent or inhibit damage on a conductive layer on the backside of an EUV mask.

[0049] EUV lithography (EUVL) employs a scanner that uses extreme ultraviolet (EUV) region light having a wavelength of about 1 nm to about 100 nm, for example, 13.5 nm. A mask is an important key component of an EUVL system. Since optical materials are not transparent to EUV radiation, an EUV mask is a reflective mask. As a property of a reflective optical system, EUV light cannot be irradiated on the mask in a normal direction, and is inclined, for example, by 6 degrees from the normal direction. When a circuit pattern is formed in an absorption layer provided above a reflective structure, a three-dimensional effect of the absorption layer height can cause a CD (critical dimension) variation or other problems. In the present disclosure, an absorption layer is embedded in a reflective multilayer structure to suppress the three-dimensional effect.

[0050] Figure 1 A cross-sectional view of an EUV reflective mask according to an embodiment of the present disclosure is shown.

[0051] In some embodiments, the EUV mask includes a substrate 10, a multilayer Mo / Si stack 15 of a plurality of alternating layers of silicon and molybdenum, a capping layer 20, and an absorption layer 25. Furthermore, as Figure 1As shown in FIG. 1, a backside conductive layer 45 is formed on the backside of the substrate 10. In some embodiments, an intermediate layer 50 is disposed intermediate the reflective multilayer structure 15 as an etch stop layer, separating the reflective multilayer structure 15 into a lower layer 15L and an upper layer 15U. In addition, in some embodiments, a black border pattern 57 is formed to surround the circuit pattern area. In some embodiments, the black border pattern 57 penetrates into the substrate 10.

[0052] In some embodiments, the substrate 10 is formed of a low thermal expansion material. In some embodiments, the substrate is a low thermal expansion glass or quartz, such as fused silica or fused quartz. In some embodiments, the low thermal expansion glass substrate transmits light at visible wavelengths, a portion of the near visible spectrum (near infrared), and a portion of the ultraviolet wavelengths. In some embodiments, the low thermal expansion glass substrate absorbs extreme ultraviolet wavelengths and deep ultraviolet wavelengths in the near extreme ultraviolet. In some embodiments, the substrate 10 is square or rectangular in shape.

[0053] In some embodiments, the Mo / Si multilayer stack 15 includes about 30 to about 60 pairs of alternating silicon and molybdenum layers. In certain embodiments, about 40 to about 50 pairs of alternating silicon and molybdenum layers are formed. In some embodiments, the reflectivity is higher than about 70% for wavelengths of interest (e.g., 13.5 nm). In some embodiments, the silicon and molybdenum layers are formed by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD) (sputtering), or any other suitable film formation method. Each layer of silicon and molybdenum is about 2 nm to about 10 nm in thickness. In some embodiments, the thickness of the silicon and molybdenum layers is substantially the same. In other embodiments, the thickness of the silicon and molybdenum layers is different. In some embodiments, each silicon layer is about 4 nm in thickness and each molybdenum layer is about 3 nm in thickness. In some embodiments, the bottommost layer of the multilayer stack 15 is a Si layer or a Mo layer.

[0054] In other embodiments, the reflective multilayer structure 15 includes alternating molybdenum and beryllium layers. In some embodiments, the number of pairs in the multilayer stack 15 is in the range of about 20 to about 100, although any number of layers is allowed as long as sufficient reflectivity is maintained for the imaging target substrate. In some embodiments, the reflectivity is higher than about 70% for the wavelengths of interest (e.g., 13.5 nm). In some embodiments, the reflective multilayer structure 15 includes about 30 to about 60 alternating Mo and Be layers. In other embodiments of the present disclosure, the multilayer stack 15 includes about 40 to about 50 alternating layers of each of Mo and Be. Further, in some embodiments, the uppermost layer of the reflective multilayer structure 15 is a Si layer, which is not in contact with the capping layer 20.

[0055] In some embodiments, a capping layer 20 is disposed over the reflective multilayer structure 15 to prevent oxidation of the multilayer stack 15. In some embodiments, the capping layer 20 is made of elemental ruthenium (greater than 99% ruthenium, not a ruthenium compound), a ruthenium alloy (e.g., RuB, RuZr, RuZrN, RuRh, RUBN, RuRhN, RuV, RuVN, RuIr, RuTi, RuP, RuOs, RuPd, RuPt, or RuRe), or a ruthenium-based oxide (e.g., Ru02, RUBO, RiVO, or RuON) with a thickness of about 2 nm to about 10 nm. In some embodiments, the capping layer 20 is a ruthenium compound Ru x M 1-x where M is one or more of Nb, Ir, Rh, Zr, Ti, B, P, V, Os, Pd, Pt, or Re, and x is greater than zero and equal to or less than about 0.5.

[0056] In some embodiments, the capping layer 20 has a thickness of about 1 nm to about 30 nm, and in other embodiments, about 2 nm to about 15 nm. In certain embodiments, the capping layer 20 has a thickness of about 3 nm to about 10 nm. In some embodiments, the capping layer 20 has a thickness of 3.5 nm ± 10%. In some embodiments, the capping layer 20 is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition (e.g., sputtering), or any other suitable film formation method. In other embodiments, a Si layer is used as the capping layer 20. In some embodiments, as set forth below, one or more layers are disposed between the capping layer and the multilayer 15.

[0057] In some embodiments, the capping layer 20 comprises two or more layers of different materials. In some embodiments, the capping layer 20 comprises two or more layers of different Ru-based materials. In some embodiments, the capping layer 20 comprises two layers, a lower layer and an upper layer, wherein the upper layer has a higher carbon absorption resistance than the lower layer, and the lower layer has a higher etching resistance during absorber etching. In some embodiments, the capping layer 20 comprises a RuNb-based layer (RuNb or RuNbN) disposed on a RuRh-based layer (RuRh or RuRhN). In some embodiments, the capping layer 20 comprises one or more of Ru, Ti, Ni, Co, Ir, In, Ta, Te, Al, Cr, Zr, Cu, Zn, Y, Nb, Tc, Pt, Rh, Ga, or Tl, or alloys, oxides, or nitrides thereof.

[0058] The absorption layer 25 is disposed in a trench formed in the upper layer 15U of the reflective multilayer structure 15, such as Figure 1 As shown in the figure. The absorber layer 25 comprises a high EUV absorbing material having a k value greater than about 0.03 or greater than about 0.045. In some embodiments, the absorber layer 25 is a Ta-based material. In some embodiments, the absorber layer 25 is made of TaN, TaO, TaB, TaBO, or TaBN. In other embodiments, the absorber layer 25 comprises a Cr-based material, such as CrN, CrBN, CrO, and / or CrON. In some embodiments, the absorber layer 25 has a multilayer structure of Cr, CrO, or CrON. In some embodiments, the absorber layer is Ir or an Ir-based material, such as IrRu, IrPt, IrN, IrAl, IrSi, or IrTi. In some embodiments, the absorber layer is a Ru-based material, such as IrRu, RuPt, RuN, RuAl, RuSi, or RuTi, or a Pt-based material, such as PtI, RuPt, PtN, PtAl, PtSi, or PtTi. In other embodiments, the absorber layer comprises an Os-based material, a Pd-based material, or a Re-based material. In some embodiments disclosed herein, X-based materials mean that the amount of X is equal to or greater than 50 atoms.

[0059] In other embodiments, the absorbent layer material is made of A x B y This indicates that A and B are each one or more of Ir, Pt, Ru, Cr, Ta, Os, Pd, Al, or Re, and that x:y is from about 0.25:1 to about 4:1. In some embodiments, x is different from y (smaller or larger). In some embodiments, the absorber layer further comprises one or more of Si, B, or N, in an amount greater than 0 to about 10 atomic%.

[0060] In some embodiments, a coating layer or antireflective layer (not shown) is disposed over the absorber layer 25. In some embodiments, the coating layer comprises a Ta-based material such as TaO or TaBO. In some embodiments, the coating layer is made of tantalum oxide (Ta2O5 or non-isostoichiometric (e.g., oxygen-deficient) tantalum oxide) and has a thickness of about 2 nm to about 20 nm. In other embodiments, a TaBO layer having a thickness in the range of about 2 nm to about 20 nm is used as the coating layer. In some embodiments, the thickness of the coating layer is about 2 nm to about 5 nm. In some embodiments, the coating layer is formed by oxidation of the absorber layer 25.

[0061] In some embodiments, the upper surface of the absorber layer 25 is flush with the upper surface of the capping layer 20. In other embodiments, the upper surface of the absorber layer 25 is lower than the upper surface of the capping layer 20 and higher than the lower surface of the capping layer 20. In some embodiments, the upper surface of the absorber layer 25 is about 0.5 nm to about 1 nm lower than the upper surface of the capping layer 20.

[0062] Furthermore, in some embodiments, the intermediate layer 50 is disposed in the middle of the reflective multilayer 15. In some embodiments, the intermediate layer 50 includes one or more of Ru, Ti, V, Ni, Co, Ir, In, Ta, Te, Al, Cr, Zr, Cu, Zn, Y, Nb, Tc, OS, Pd, Pt, Rh, Re, Ga, or Tl, or alloys, oxides, or nitrides thereof. In some embodiments, the intermediate layer includes one or more of BC, BN, CN, or graphene. In some embodiments, the material of the intermediate layer 50 is selected from the materials for the capping layer 20 as described above. In some embodiments, the intermediate layer 50 is made of the same material as the capping layer 20, and in other embodiments, the intermediate layer 50 is made of a different material than the capping layer 20. In some embodiments, the intermediate layer 50 is a material other than Ru, Cr (metallic Ru and metallic Cr), Si, Si compounds, and carbon.

[0063] In some embodiments, the thickness of the intermediate layer 50 is from about 1 nm to about 30 nm, and in other embodiments it is from about 2 nm to about 15 nm. In some embodiments, the thickness of the intermediate layer 50 is from about 3 nm to about 10 nm. In some embodiments, the intermediate layer 50 is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition (e.g., sputtering), or any other suitable film formation method. When the thickness of the intermediate layer is greater than these ranges, it can reduce the reflectivity of the reflective multilayer structure 15, and when the thickness is less than these ranges, the intermediate layer may not be able to fully function as an etch stop layer.

[0064] In some embodiments, the number of Mo / Si pairs in the upper layer 15U is equal to or less than the number of Mo / Si pairs in the lower layer 15L. In other embodiments, the number of Mo / Si pairs in the upper layer 15U is greater than the number of Mo / Si pairs in the lower layer 15L. In some embodiments, each of the upper layer 15U and the lower layer 15L comprises about 20 to about 40 pairs of Mo / Si layers.

[0065] In some embodiments, a back-side conductive layer 45 is disposed on a second main surface of the substrate 10, the second main surface being opposite to a first main surface of the substrate 10 on which the Mo / Si multilayer 15 is formed. In some embodiments, the back-side conductive layer 45 is made of TaB (tantalum boride) or other Ta-based conductive materials. In some embodiments, tantalum boride is crystalline. Crystalline tantalum boride includes TaB, Ta5B6, Ta3B4, and TaB2. In other embodiments, tantalum boride is polycrystalline or amorphous. In other embodiments, the back-side conductive layer 45 is made of a Cr-based conductive material (CrN or CrON). In some embodiments, the sheet resistance of the back-side conductive layer 45 is equal to or less than 20 Ω / □. In some embodiments, the sheet resistance of the back-side conductive layer 45 is equal to or greater than 0.1 Ω / □. In some embodiments, the surface roughness Ra of the back-side conductive layer 45 is equal to or less than 0.25 nm. In some embodiments, the surface roughness Ra of the back-side conductive layer 45 is equal to or greater than 0.05 nm. Furthermore, in some embodiments, the flatness of the back-side conductive layer 45 is equal to or less than 50 nm. In some embodiments, the planarity of the back-side conductive layer 45 is greater than 1 nm. In some embodiments, the thickness of the back-side conductive layer 45 is in the range of about 50 nm to about 400 nm. In other embodiments, the back-side conductive layer 45 has a thickness of about 50 nm to about 100 nm. In some embodiments, the thickness is in the range of about 65 nm to about 75 nm. In some embodiments, the back-side conductive layer 45 is formed by atmospheric chemical vapor deposition (CVD), low-pressure CVD, plasma-enhanced CVD, laser-enhanced CVD, atomic layer deposition (ALD), molecular beam epitaxy (MBE), physical vapor deposition (including thermal deposition, pulsed laser deposition, electron beam evaporation, ion beam assisted evaporation, and sputtering), or any other suitable film formation method. In the case of CVD, in some embodiments, the source gas includes TaCl5 and BCl3.

[0066] Figure 2 A cross-sectional view of an EUV reflective photomask according to an embodiment of this disclosure is shown. The materials, configurations, processes, and / or dimensions explained with respect to the above embodiments can be applied to the following embodiments, and therefore detailed explanations are omitted for simplicity.

[0067] In some embodiments, the absorbent layer 25 is recessed from the upper surface of the cover layer 20, such as... Figure 2 As shown in the figure. In some embodiments, the upper surface of the absorber layer 25 is recessed from the self-reflective multilayer structure 15. In some embodiments, the depth D1 from the upper surface of the capping layer 20 to the absorber layer 25 is in the range of about 5 nm to about 100 nm, and in other embodiments, the depth D1 is in the range of about 10 nm to about 50 nm.

[0068] Figure 3 A cross-sectional view of an EUV reflective photomask according to an embodiment of this disclosure is shown. The materials, configurations, processes, and / or dimensions explained with respect to the above embodiments can be applied to the following embodiments, and therefore detailed explanations are omitted for simplicity.

[0069] In some embodiments, the absorbent layer 25 protrudes beyond the upper surface of the cover layer 20, such as... Figure 3 As shown in the diagram. In some embodiments, the height D2 from the upper surface of the capping layer 20 to the top of the absorption layer 25 is in the range of about 4 nm to about 50 nm, and in other embodiments, the height D2 is in the range of about 5 nm to about 30 nm. In some embodiments, the height (protrusion amount) D2 depends on the thickness of the hard mask layer (explained later). When the height D2 is too large, it can cause three-dimensional effects and near-field diffraction at the edges of the absorption layer 25.

[0070] Figure 4 A cross-sectional view of an EUV reflective photomask according to an embodiment of this disclosure is shown. The materials, configurations, processes, and / or dimensions explained with respect to the above embodiments can be applied to the following embodiments, and therefore detailed explanations are omitted for simplicity.

[0071] In some embodiments, no absorption layer is provided in the trench 22 formed in the reflective multilayer structure 15, and the intermediate layer 50 is exposed at the bottom of the trench 22. In some embodiments, Figure 4 The EUV photomask shown is a phase-transfer mask. In some embodiments, the depth D3 of the trench is set to have an appropriate phase difference between the reflected EUV light from the reflective multilayer structure 15 (15U+15L) and the reflected EUV light from the lower layer 15L.

[0072] Figure 5 A cross-sectional view of an EUV reflective photomask according to an embodiment of this disclosure is shown. The materials, configurations, processes, and / or dimensions explained with respect to the above embodiments can be applied to the following embodiments, and therefore detailed explanations are omitted for simplicity.

[0073] In some embodiments, instead of an absorption layer, trenches formed in the upper layer 15U are filled with a protective layer 27, which is substantially an EUV transmitting material (e.g., with a transmittance greater than 70%). Figure 5 As shown in the figure. In some embodiments, the protective layer 27 comprises silicon oxide, silicon nitride, polycrystalline silicon, silicon carbide, or any other suitable material. The protective layer 27 inhibits damage to the fine patterns formed in the upper layer 15U and prevents oxidation of the side surfaces of the upper layer 15U. In some embodiments, the protective layer 27 is also formed to fill the black boundary pattern 57.

[0074] Figure 6 A cross-sectional view of an EUV reflective photomask according to an embodiment of this disclosure is shown. The materials, configurations, processes, and / or dimensions explained with respect to the above embodiments can be applied to the following embodiments, and therefore detailed explanations are omitted for simplicity.

[0075] In some embodiments, the trenches formed in the upper layer 15U are filled with an absorption layer 25 and a protective layer 27, wherein the protective layer 27 is essentially an EUV transmission material, such as... Figure 6 As shown in the figure. In some embodiments, the configuration of the absorber layer 25 is similar to... Figure 2 The configuration shown is the same. In some embodiments, the protective layer 27 comprises silicon oxide, silicon nitride, polysilicon, silicon carbide, or any other suitable material. The protective layer 27 inhibits damage to the fine patterns formed in the upper layer 15U and prevents oxidation of the side surfaces of the upper layer 15U. In some embodiments, the protective layer 27 is also filled with a black boundary pattern 57.

[0076] Figure 7A to Figure 7E The diagram illustrates the sequential method for manufacturing an EUV mask used in extreme ultraviolet lithography (EUVL). Of course, it is possible to... Figure 7A to Figure 7E Additional operations are provided before, during, and after the processes shown, and for additional embodiments of the method, some operations described below may be replaced or eliminated. The order of operations / processes is interchangeable. The materials, configurations, processes, and / or dimensions explained with respect to the above embodiments can be applied to the following embodiments, and therefore detailed explanations are omitted for simplicity.

[0077] In the fabrication of the EUV photomask, a first photoresist layer 35 is formed above the blank mask. The blank mask includes a substrate 10, a reflective multilayer structure 15 (Mo / Si layer), a cover layer 20, and a rigid mask layer 30.

[0078] In some embodiments, a hard mask layer 30 is disposed above the cover layer 20. In some embodiments, the hard mask layer 30 is made of a Cr-based material, such as CrO, CrON, or CrCON. In other embodiments, the hard mask layer 30 is made of a Ta-based material, such as TaB, TaO, TaBO, or TaBN. In other embodiments, the hard mask layer 30 is made of silicon, a silicon-based compound (e.g., SiN or SiON), ruthenium, or a ruthenium-based compound (Ru or RuB). In some embodiments, the hard mask layer 30 has a thickness of about 5 nm to about 50 nm. In some embodiments, the hard mask layer 30 comprises two or more different material layers. In some embodiments, the hard mask layer 30 is formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, or any other suitable film formation method.

[0079] The first photoresist layer 35 is selectively exposed to photochemical radiation, such as an electron beam. In some embodiments, a blank EUV photomask is inspected prior to the formation of the first photoresist layer 35. The selectively exposed first photoresist layer 35 is developed to form a pattern 40 in the first photoresist layer 35. In some embodiments, the pattern 40 corresponds to a pattern of semiconductor device features to be formed using an EUV photomask in subsequent operations. The pattern 40 in the first photoresist layer 35 then extends into the hard mask layer 30, as... Figure 7B As shown in the figure. In some embodiments, the pattern 40 extending into the hard mask layer 30 is formed by etching with a suitable wet or dry etchant that is selective to the cover layer 20. After the pattern 40 in the hard mask layer 30 is formed, the first photoresist layer 35 is removed by a photoresist stripper to expose the upper surface of the hard mask layer 30.

[0080] Next, the pattern 40 in the rigid mask layer 30 extends into the cover layer 20 and the reflective multilayer structure 15, thereby forming a groove pattern 42, such as... Figure 7C As shown in some embodiments, such as Figure 7C As shown, the etching roughly stops at the intermediate layer 50.

[0081] In some embodiments, the trench pattern 42 extending into the capping layer 20 and the reflective multilayer structure 15 is formed by selectively etching the capping layer 20 and the multilayer structure 15 with a suitable wet or dry etchant. In some embodiments, plasma dry etching is used. In some embodiments, etching substantially stops at the intermediate layer 50 when the intermediate layer 50 is made of the same or similar material as the hard mask layer 30, or when the intermediate layer 50 and the hard mask layer 30 have similar etch resistivity to etching. In some embodiments, about 0.1 nm to about 0.3 nm of the surface of the intermediate layer 50 is etched. Then as... Figure 7D As shown, the rigid mask layer 30 has been removed.

[0082] In some embodiments, the overlay layer 20 is patterned by using a patterned hard mask layer 30, and then, with or without the hard mask layer 30 (i.e., the overlay layer is used as a hard mask), the reflective multilayer structure 15 is patterned by using the patterned overlay layer 20 as an etched mask.

[0083] Next, as Figure 7E As shown, one or more layers for the absorbent layer 25 are formed in the trench pattern 42 and over the capping layer 20. Next, a planarization operation, such as chemical mechanical polishing (CMP), is performed to remove excess material from the capping layer 20, thereby forming the absorbent layer (pattern) 25, as shown. Figure 7E As shown in the figure. In some embodiments, the hard mask layer 30 is not removed before forming one or more layers for the absorption layer 25, and the hard mask layer 30 is removed after or during the CMP operation.

[0084] Next, in some embodiments, an anti-reflective layer (not shown) is formed on the absorption layer 25. When the absorption layer 25 is made of a Ta-based material, the anti-reflective layer is formed by oxidation of the absorption layer 25. Subsequently, a black boundary pattern is formed as follows. Figure 7E A second photoresist layer is formed above the structure and is selectively exposed to photochemical radiation, such as electron beams, ion beams, or UV radiation. The selectively exposed second photoresist layer is developed to form a pattern within the second photoresist layer. The pattern corresponds to a black boundary surrounding the circuit pattern. The black boundary is a frame-shaped area created by removing all multilayers on the EUV mask in the area surrounding the circuit pattern region. Black boundaries are created when an EUV mask is printed on the wafer to prevent exposure of adjacent fields. In some embodiments, the width of the black boundary is in the range of about 1 mm to about 5 mm. Next, the pattern in the second photoresist layer extends into the capping layer 20, the reflective multilayer structure 15, and the intermediate layer 50 to form a black boundary pattern 57, as shown. Figure 7F As shown in the figure. In some embodiments, the black boundary pattern 57 is formed by etching with one or more suitable wet or dry etchants that selectively etch the respective layers. In some embodiments, plasma dry etching is used. The second photoresist layer is then removed using a suitable photoresist stripper, as shown in the figure. Figure 7F As shown in the diagram. In some embodiments of this disclosure, the black boundary pattern 57 defines the black boundary of the photomask.

[0085] Figure 8A and Figure 8B The diagram illustrates the sequential method for manufacturing EUV masks used in EUVL. Of course, this can be achieved by... Figure 8A and Figure 8BAdditional operations are provided before, during, and after the processes shown, and for additional embodiments of the method, some operations described below may be replaced or eliminated. The order of operations / processes is interchangeable. The materials, configurations, processes, and / or dimensions explained with respect to the above embodiments can be applied to the following embodiments, and therefore detailed explanations are omitted for simplicity.

[0086] In formation Figure 7E Following the structure shown, an etching operation is used to recess the absorber layer 25, such that the upper surface of the absorber layer 25 is located below the upper surface of the capping layer 20 or below the upper surface of the reflective multilayer structure 15, as shown. Figure 8A As shown in the diagram. The etching operation includes one or more plasma dry etching and wet etching processes. Then, as... Figure 8B As shown, a black boundary pattern 57 is formed.

[0087] Figure 9A and Figure 9B The diagram illustrates the sequential method for manufacturing EUV masks used in EUVL. Of course, this can be achieved by... Figure 9A and Figure 9B Additional operations are provided before, during, and after the processes shown, and for additional embodiments of the method, some operations described below may be replaced or eliminated. The order of operations / processes is interchangeable. The materials, configurations, processes, and / or dimensions explained with respect to the above embodiments can be applied to the following embodiments, and therefore detailed explanations are omitted for simplicity.

[0088] In formation Figure 8A Following the structure shown, a protective layer 27 is formed above the absorber layer 25, as... Figure 9A As shown in the diagram, one or more layers for the protective layer 27 are formed in a trench pattern above the absorbent layer 25 and above the capping layer 20. Next, a planarization operation, such as CMP, is performed to remove excess material from the capping layer 20, thereby forming the protective layer 27, as shown in the diagram. Figure 9A As shown in the image. Next, as... Figure 9B As shown, a black border pattern 57 is formed. In other embodiments, after the black border pattern 57 is formed, a protective layer 27 is formed, and in this case, a protective layer 27 is also formed in the black border pattern 57.

[0089] Figure 10A to Figure 10C The diagram illustrates the sequential method for manufacturing EUV masks used in EUVL. Of course, it is possible to... Figure 10A to Figure 10C Additional operations are provided before, during, and after the processes shown, and for additional embodiments of the method, some operations described below may be replaced or eliminated. The order of operations / processes is interchangeable. The materials, configurations, processes, and / or dimensions explained with respect to the above embodiments can be applied to the following embodiments, and therefore detailed explanations are omitted for simplicity.

[0090] In formation Figure 7C Following the structure shown, an absorption layer 25 is formed in the trench pattern, as... Figure 10A As shown in the diagram, one or more layers for the absorption layer 25 are formed in the trench pattern 42 and above the rigid mask layer 30. Next, a planarization operation, such as CMP, is performed to remove excess material on the rigid mask layer 30, thereby forming the absorption layer (pattern) 25, as shown. Figure 10A As shown in the image. Then, as... Figure 10B As shown, the hard mask layer 30 is removed using a suitable etching operation (such as wet etching). With the removal of the hard mask layer 30, the absorber layer 25 protrudes from the upper surface of the cover layer. Then, as... Figure 10C As shown, a black boundary pattern 57 is formed.

[0091] Figure 11A and Figure 11B The diagram illustrates the sequential method for manufacturing EUV masks used in EUVL. Of course, it is possible to... Figure 11A and Figure 11B Additional operations are provided before, during, and after the processes shown, and for additional embodiments of the method, some operations described below may be replaced or eliminated. The order of operations / processes is interchangeable. The materials, configurations, processes, and / or dimensions explained with respect to the above embodiments can be applied to the following embodiments, and therefore detailed explanations are omitted for simplicity.

[0092] In formation Figure 7B Following the structure shown, a protective layer 27 is formed in the groove pattern, as... Figure 11A As shown in the diagram, one or more layers for the protective layer 27 are formed in the trench pattern and over the cover layer 20, and then a planarization operation, such as CMP, is performed to remove excess material on the cover layer 20, thereby forming the protective layer 27, as shown in the diagram. Figure 11A As shown in the image. Next, as... Figure 11B As shown, a black border pattern 57 is formed. In other embodiments, after the black border pattern 57 is formed, a protective layer 27 is formed, and in this case, a protective layer 27 is also formed in the black border pattern 57.

[0093] Figure 12 A flowchart illustrating the manufacture of one or more of the blank screens described in the foregoing embodiments is shown. Of course, it is possible to... Figure 12 Additional operations are provided before, during, and after the process steps shown, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes is interchangeable.

[0094] At S101, a lower portion of a reflective multilayer structure is formed on a substrate. In some embodiments, one or more layers are formed on the substrate before forming the reflective multilayer structure. In some embodiments, the reflective multilayer structure is formed by an ion beam deposition method or a sputtering method.

[0095] At S102, an intermediate (etch stop) layer is formed on the lower portion of the reflective multilayer structure. In some embodiments, the intermediate layer is formed by an ion beam deposition method or a sputtering method. In some embodiments, in the same deposition apparatus as that used for the reflective multilayer structure, the intermediate layer is continuously formed on the lower portion of the multilayer stack by an ion beam deposition method.

[0096] Next, at S103, an upper portion of the reflective multilayer structure is formed on the intermediate layer. In some embodiments, the upper portion of the reflective multilayer structure is terminated with a Si layer, and in other embodiments, the multilayer stack is terminated with a Mo layer. In some embodiments, in the same deposition apparatus as that used for the intermediate layer, the upper portion is continuously formed on the intermediate layer by an ion beam deposition method.

[0097] At S104, a cover layer is formed on the upper portion of the reflective multilayer structure. In some embodiments, in the same deposition apparatus as that used for the reflective multilayer structure, the cover layer is continuously formed on the multilayer stack by an ion beam deposition method. At S105, a hard mask layer is formed on the cover layer.

[0098] Figure 13A And Figure 13B shows a blank EUV reflective mask 5 according to an embodiment of the present disclosure. Figure 13C shows a patterned EUV reflective mask for use in EUV lithography. Figure 13A is a plan view (viewed from the top), and Figure 13B is a cross-sectional view taken along the X direction.

[0099] In some embodiments, the functional layers (multilayer Mo / Si stack 15, intermediate layer 50, cover layer 20, and hard mask layer 30) above the substrate have the same size as the substrate (X1 = X2 and Y1 = Y2). In other embodiments, the functional layers have a size smaller than that of the substrate 10, as Figure 13A And Figure 13B shown in (X2 < X1 and Y2 < Y1). In some embodiments, the size of the functional layers is in the range of about 138 mm × 138 mm to 142 mm × 142 mm. In some embodiments, the shape of the functional layers is square or rectangular. When forming individual layers by, for example, sputtering, a smaller size of one or more of the functional layers can be formed by using a frame-shaped coating having an opening in the range of about 138 mm × 138 mm to about 142 mm × 142 mm. In other embodiments, all the layers above the substrate 10 have the same size as the substrate 10.

[0100] Figure 14A A flowchart of a method for manufacturing a semiconductor device according to an embodiment of this disclosure is shown, and Figure 14B , Figure 14C , Figure 14D and Figure 14E This disclosure illustrates the sequential manufacturing operations of a method for manufacturing a semiconductor device according to embodiments of the present disclosure. The disclosure provides a semiconductor substrate or other suitable substrate to be patterned for forming an integrated circuit thereon. In some embodiments, the semiconductor substrate comprises silicon. Alternatively, the semiconductor substrate may comprise germanium, silicon-germanium, or other suitable semiconductor materials, such as group III-V semiconductor materials. Figure 14A At step S201, a target layer to be patterned is formed over a semiconductor substrate. In some embodiments, the target layer is a semiconductor substrate. In some embodiments, the target layer includes a conductive layer, such as a metal layer or a polysilicon layer; a dielectric layer, such as silicon oxide, silicon nitride, SiON, SiOC, SiOCN, SiCN, hafnium oxide, or aluminum oxide; or a semiconductor layer, such as an epitaxially formed semiconductor layer. In some embodiments, the target layer is formed over an underlying structure, such as an isolation structure, a transistor, or wiring. Figure 14A At position S202, a photoresist layer is formed above the target layer, such as... Figure 14B As shown in the diagram. During subsequent optical lithography exposure processes, the photoresist layer is sensitive to radiation from the exposure source. In this embodiment, the photoresist layer is sensitive to EUV light used in the optical lithography exposure process. The photoresist layer can be formed over the target layer by spin-on or other suitable techniques. The coated photoresist layer can be further baked to remove solvent from the photoresist layer. Figure 14A At point S203, an EUV reflective mask, as described above, is used to pattern the photoresist layer, such as... Figure 14B As shown in the diagram, the patterning of the photoresist layer includes performing an optical lithography exposure process using an EUV exposure system employing an EUV mask. During the exposure process, an integrated circuit (IC) design pattern defined on the EUV mask is imaged onto the photoresist layer to form a potential pattern thereon. The patterning of the photoresist layer further includes developing the exposed photoresist layer to form a patterned photoresist layer with one or more openings. In one embodiment where the photoresist layer is a positive photoresist layer, the exposed portion of the photoresist layer is removed during the development process. The patterning of the photoresist layer may further include other process steps, such as various baking steps at different stages. For example, a post-exposure-baking (PEB) process may be performed after the optical lithography exposure process and before the development process.

[0101] exist Figure 14A At S204, a patterned photoresist layer is used as an etching mask to pattern the target layer, such as...Figure 14D As shown in the figure. In some embodiments, the patterned target layer includes applying an etching process to the target layer using a patterned photoresist layer as an etching mask. A portion of the target layer exposed within an opening in the patterned photoresist layer is etched, while the remaining portion is protected from etching. Furthermore, the patterned photoresist layer can be removed by wet stripping or plasma ashing, as shown in the figure. Figure 14E As shown in the image.

[0102] In this disclosure, the use of an intermediate layer as an etch stop layer in the middle of the reflective multilayer structure allows for precise control of the depth of the embedded absorber layer. The embedded absorber layer suppresses three-dimensional effects and near-field diffraction at the absorber edges.

[0103] It should be understood that not all advantages have been discussed in this document, no particular advantage is required for all embodiments or instances, and other embodiments or instances may offer different advantages.

[0104] According to one embodiment of this application, a reflective screen includes a substrate, a lower reflective multilayer disposed above the substrate, an intermediate layer disposed above the lower reflective multilayer, an upper reflective multilayer disposed above the intermediate layer, a capping layer disposed above the upper reflective multilayer, and an absorption layer disposed in a trench formed in the upper reflective layer and above the intermediate layer. The intermediate layer includes a metal other than chromium (Cr), ruthenium (Ru), silicon (Si), silicon (Si) compounds, and carbon. In one or more of the above and below embodiments, the intermediate layer includes one or more selected from the group consisting of titanium (Ti), nickel (Ni), cobalt (Co), iridium (Ir), indium (In), tantalum (Ta), tellurium (Te), aluminum (Al), zirconium (Zr), copper (Cu), zinc (Zn), yttrium (Y), niobium (Nb), technetium (Tc), platinum (Pt), rhodium (Rh), gallium (Ga), and thallium (Tl), their alloys, their oxides, and their nitrides. In one or more of the above and below embodiments, the intermediate layer comprises one or more selected from the group consisting of iridium (Ir), indium (In), tellurium (Te), yttrium (Y), niobium (Nb), technetium (Tc), platinum (Pt), rhodium (Rh), and thallium (Tl), their alloys, their oxides, and their nitrides. In one or more of the above and below embodiments, the thickness of the intermediate layer is in the range of 2 nm to 15 nm. In one or more of the above and below embodiments, the capping layer is made of the same material as the intermediate layer. In one or more of the above and below embodiments, the uppermost layer of the upper reflective multilayer in contact with the capping layer is a silicon (Si) layer.

[0105] According to another embodiment of this disclosure, a reflective mask includes a substrate, a lower reflective multilayer disposed above the substrate, an intermediate layer disposed above the lower reflective multilayer, an upper reflective multilayer disposed above the intermediate layer, a capping layer disposed above the upper reflective multilayer, and an absorption layer disposed in a trench formed in the upper reflective layer and above the intermediate layer. The absorption layer protrudes from the upper surface of the capping layer. In one or more of the above and following embodiments, the protrusion of the absorption layer is in the range of 5 nm to 30 nm. In one or more of the above and following embodiments, the capping layer is made of the same material as the intermediate layer. In one or more of the above and following embodiments, the capping layer includes Ru. x M 1-x M is one or more of niobium (Nb), iridium (Ir), rhodium (Rh), zirconium (Zr), titanium (Ti), boron (B), phosphorus (P), vanadium (V), osmium (Os), palladium (Pd), platinum (Pt), or rhenium (Re), and x is greater than zero and equal to or less than about 0.5. In one or more of the above and below embodiments, the absorber layer comprises one or more layers of an iridium (Ir)-based material, a platinum (Pt)-based material, or a ruthenium (Ru)-based material. In one or more of the above and below embodiments, the intermediate layer comprises a ruthenium (Ru) alloy. In one or more of the above and below embodiments, the intermediate layer comprises at least one selected from the group consisting of ruthenium niobate (RuNb), ruthenium boron nitride (RuBN), ruthenium rhodiumide (RuRh), and ruthenium rhodium nitride (RuRhN). In one or more of the above and below embodiments, the intermediate layer includes at least one selected from the group consisting of boron carbide (BC), boron nitride (BN), carbon nitride (CN), and graphene.

[0106] According to another embodiment of this disclosure, a reflective mask includes a substrate, a lower reflective multilayer disposed above the substrate, an intermediate layer disposed above the lower reflective multilayer, an upper reflective multilayer disposed above the intermediate layer, a capping layer disposed above the upper reflective multilayer, and a protective layer disposed in a trench formed in the upper reflective layer and above the intermediate layer. The protective layer is transmissive to extreme ultraviolet light. In one or more of the above and following embodiments, the protective layer includes at least one selected from the group consisting of silicon oxide, silicon nitride, polycrystalline silicon, and silicon carbide. In one or more of the above and following embodiments, the reflective mask further includes an absorption layer disposed in a trench between the protective layer and the intermediate layer. In one or more of the above and following embodiments, the capping layer is made of the same material as the intermediate layer. In one or more of the above and following embodiments, the capping layer and the intermediate layer are made of ruthenium (Ru) or a ruthenium (Ru) compound. In one or more of the above and following embodiments, the intermediate layer is made of a different material from the capping layer.

[0107] According to another embodiment of this disclosure, in a method for manufacturing a reflective mask, a photoresist layer is formed above a blank mask. The blank mask includes a substrate, a lower reflective multilayer disposed above the substrate, an intermediate layer disposed above the lower reflective multilayer, an upper reflective multilayer disposed above the intermediate layer, a capping layer disposed above the upper reflective multilayer, and a rigid mask layer disposed above the capping layer. The photoresist layer is patterned. The rigid mask layer is patterned using the patterned photoresist layer. The capping layer and the upper reflective multilayer are patterned using the patterned rigid mask layer to form a trench pattern. An absorption layer is formed in the trench pattern. The intermediate layer includes metals other than chromium (Cr), ruthenium (Ru), silicon (Si), silicon (Si) compounds, and carbon. In one or more of the above and below embodiments, the intermediate layer comprises one or more selected from the group consisting of titanium (Ti), nickel (Ni), cobalt (Co), iridium (Ir), indium (In), tantalum (Ta), tellurium (Te), aluminum (Al), zirconium (Zr), copper (Cu), zinc (Zn), yttrium (Y), niobium (Nb), technetium (Tc), platinum (Pt), rhodium (Rh), gallium (Ga), and thallium (Tl), their alloys, their oxides, and their nitrides. In one or more of the above and below embodiments, the hard mask layer is removed before the absorption layer is formed. In one or more of the above and below embodiments, the thickness of the intermediate layer is in the range of 2 nm to 15 nm. In one or more of the above and below embodiments, the capping layer is made of the same material as the intermediate layer. In one or more of the above and below embodiments, the uppermost layer of the upper reflective multilayer in contact with the capping layer is a silicon (Si) layer.

[0108] According to another embodiment of this disclosure, in a method for manufacturing a reflective mask, a photoresist layer is formed above a blank mask. The blank mask includes a substrate, a lower reflective multilayer disposed above the substrate, an intermediate layer disposed above the lower reflective multilayer, an upper reflective multilayer disposed above the intermediate layer, a capping layer disposed above the upper reflective multilayer, and a rigid mask layer disposed above the capping layer. The photoresist layer is patterned. The rigid mask layer is patterned using the patterned photoresist layer. The capping layer and the upper reflective multilayer are patterned using the patterned rigid mask layer to form a trench pattern. An absorption layer is formed in the trench pattern. After forming the absorption layer, the rigid mask layer is removed, causing the absorption layer to protrude beyond the upper surface of the capping layer. In one or more of the above and following embodiments, the protrusion of the absorption layer is in the range of 5 nm to 30 nm. In one or more of the above and following embodiments, the capping layer is made of the same material as the intermediate layer. In one or more of the above and following embodiments, the capping layer includes Ru... x M 1-xM is one or more of niobium (Nb), iridium (Ir), rhodium (Rh), zirconium (Zr), titanium (Ti), boron (B), phosphorus (P), vanadium (V), osmium (Os), palladium (Pd), platinum (Pt), or rhenium (Re), and x is greater than zero and equal to or less than about 0.5. In one or more of the above and below embodiments, the absorber layer comprises one or more layers of an iridium (Ir)-based material, a platinum (Pt)-based material, or a ruthenium (Ru)-based material. In one or more of the above and below embodiments, the intermediate layer comprises a Ru alloy. In one or more of the above and below embodiments, the intermediate layer comprises at least one selected from the group consisting of ruthenium niobide (RuNb), ruthenium boron nitride (RuBN), ruthenium rhodium nitride (RuRhN), and ruthenium rhodium nitride (RuRhN). In one or more of the above and below embodiments, the intermediate layer includes at least one selected from the group consisting of boron carbide (BC), boron nitride (BN), carbon nitride (CN), and graphene.

[0109] According to another embodiment of this disclosure, in a method for manufacturing a reflective mask, a photoresist layer is formed above a blank mask. The blank mask includes a substrate, a lower reflective multilayer disposed above the substrate, an intermediate layer disposed above the lower reflective multilayer, an upper reflective multilayer disposed above the intermediate layer, a capping layer disposed above the upper reflective multilayer, and a rigid mask layer disposed above the capping layer. The photoresist layer is patterned. The rigid mask layer is patterned using the patterned photoresist layer. The capping layer and the upper reflective multilayer are patterned using the patterned rigid mask layer to form a trench pattern. A protective layer is formed in the trench pattern. The protective layer is transmissive to extreme ultraviolet light. In one or more of the above and following embodiments, the protective layer includes at least one selected from the group consisting of silicon oxide, silicon nitride, polycrystalline silicon, and silicon carbide. In one or more of the above and following embodiments, an absorption layer is formed in the trench pattern and recessed before forming the protective layer. The protective layer is formed above the recessed absorption layer. In one or more of the above and below embodiments, the capping layer is made of the same material as the intermediate layer. In one or more of the above and below embodiments, both the capping layer and the intermediate layer are made of ruthenium (Ru) or a ruthenium (Ru) compound. In one or more of the above and below embodiments, the intermediate layer is made of a different material than the capping layer.

[0110] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A reflective dome, characterized in that, Include: One substrate; A multi-layer reflective structure is disposed above the substrate; An intermediate layer is disposed above the lower reflective multilayer; A multi-layered reflective structure is disposed above the intermediate layer; A covering layer is disposed above the upper reflective multilayer; and An absorption layer is disposed in a trench forming through the cover layer, in the upper reflective multilayer, and above the intermediate layer. The capping layer and the intermediate layer are made of the same material, which includes one or more of the group consisting of indium, tellurium, copper, zinc, technetium, gallium and thallium, their alloys, their oxides and their nitrides.

2. The reflective dome as described in claim 1, characterized in that, The same material includes one or more of the group consisting of tellurium, copper, zinc, technetium, gallium and thallium, their alloys, their oxides and their nitrides.

3. The reflective dome as described in claim 1, characterized in that, The same material includes one or more of the group consisting of indium, tellurium, technetium and thallium, their alloys, their oxides and their nitrides.

4. The reflective dome as described in claim 1, characterized in that, The thickness of the intermediate layer is in the range of 2nm to 15nm.

5. The reflective dome as described in claim 1, characterized in that, The outer surface of the reflective shroud includes an absorption layer protruding from the upper surface of the cover layer, wherein a portion of the absorption layer in the upper reflective multilayer, a portion of the absorption layer in the cover layer, and a portion of the absorption layer protruding from the upper surface of the cover layer have the same width.

6. The reflective dome as described in claim 1, characterized in that, The topmost layer of the upper reflective multilayer that is in contact with the capping layer is a silicon layer.

7. A method for manufacturing a reflective dome, characterized in that, The method includes the following steps: A photoresist layer is formed above a blank mask. The blank mask includes a substrate, a lower reflective multilayer disposed above the substrate, an intermediate layer disposed above the lower reflective multilayer, an upper reflective multilayer disposed above the intermediate layer, a cover layer disposed above the upper reflective multilayer, and a rigid mask layer disposed above the cover layer. Pattern the photoresist layer; The rigid mask layer is patterned by using a patterned photoresist layer; The overlay and the upper reflective multilayer are patterned by using a patterned hard mask layer to form a trench pattern, and the intermediate layer is used as an etch stop layer for the trench pattern. An absorption layer is formed in the groove pattern; and After the absorbent layer is formed, the hard masking layer is removed, causing the absorbent layer to protrude from one upper surface of the cover layer. The capping layer and the intermediate layer are made of the same material, which includes one or more of the group consisting of indium, tellurium, copper, zinc, technetium, gallium and thallium, their alloys, their oxides and their nitrides.

8. The method as described in claim 7, characterized in that, The protrusion of the absorption layer is in the range of 5 nm to 30 nm.

9. The method as described in claim 7, characterized in that, After the absorption layer is formed, a portion of the absorption layer in the upper reflective multilayer, a portion of the absorption layer in the cover layer, and a portion of the absorption layer protruding from the upper surface of the cover layer have the same width, and wherein the outer surface of the reflective shroud includes the absorption layer protruding from the upper surface of the cover layer.

10. The method as described in claim 7, characterized in that, The same material includes ruthenium-indium alloy.

11. The method as described in claim 7, characterized in that, The absorber layer comprises one or more layers of iridium-based, platinum-based, or ruthenium-based materials.

12. The method as described in claim 7, characterized in that, This same material includes ruthenium-tellurium alloy.

13. The method as described in claim 7, characterized in that, This same material includes ruthenium-thallium alloys.

14. The method as described in claim 7, characterized in that, The thickness of the intermediate layer is in the range of 2nm to 15nm.

15. A method for manufacturing a reflective dome, characterized in that, The method includes the following steps: A photoresist layer is formed above a blank mask. The blank mask includes a substrate, a lower reflective multilayer disposed above the substrate, an intermediate layer disposed above the lower reflective multilayer, an upper reflective multilayer disposed above the intermediate layer, a cover layer disposed above the upper reflective multilayer, and a rigid mask layer disposed above the cover layer. Pattern the photoresist layer; The rigid mask layer is patterned by using a patterned photoresist layer; The overlay and the upper reflective multilayer are patterned by using a patterned hard mask layer to form a trench pattern, and the intermediate layer is used as an etch stop layer for the trench pattern. and A protective layer is formed in the groove pattern. This protective layer is transmissive to extreme ultraviolet light. The capping layer and the intermediate layer are made of the same material, which includes one or more of the group consisting of indium, tellurium, copper, zinc, technetium, gallium and thallium, their alloys, their oxides and their nitrides.

16. The method as described in claim 15, characterized in that, The protective layer includes at least one selected from the group consisting of silicon oxide, silicon nitride, polycrystalline silicon, and silicon carbide.

17. The method as described in claim 15, characterized in that, Before forming this protective layer, the following steps are further included: An absorption layer is formed in the trench pattern; and This causes the absorbent layer to become concave. The protective layer is formed on top of the recessed absorbent layer.

18. The method as described in claim 15, characterized in that, The outer surface of the reflective shroud includes a pattern of the covering layer and the protective layer.

19. The method as described in claim 15, characterized in that, The same material includes ruthenium-indium alloy.

20. The method as described in claim 15, characterized in that, The thickness of the intermediate layer is in the range of 2nm to 15nm.

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