A RapidIO and 10 Gigabit Ethernet Protocol High-Speed Switching System and Method

Abstract

The present invention relates to a high-speed switching system and method for RapidIO and 10 Gigabit Ethernet protocols. The system of the present invention includes an APB interface and a register resource module accessible to registers, an AXI bus interface module, a DMA start control module, a descriptor generation / parsing module, a memory module, and a buffer application / release module. The APB interface and the register resource module accessible to registers are connected to the internal status register through the APB bus. The AXI bus interface module is respectively connected to the memory module and the external AXI bus. The buffer application / release module is respectively connected to the DMA start control module, the descriptor generation / parsing module, and the external buffer management module. The descriptor generation / parsing module is respectively connected to the external descriptor management module and the DMA start control module. The DMA start control module is connected to the external DMA controller. The present invention provides a hardware circuit for 10 Gigabit Ethernet and RapidIO data transmission without the participation of a processor, reduces the performance loss caused by the frequent processing of interrupts by the processor, and improves the performance of the processor.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology, and particularly relates to a high-speed switching system and method for RapidIO and 10 Gigabit Ethernet protocols. Background Art

[0002] A high-speed switching circuit for RapidIO and 10 Gigabit Ethernet protocols can receive or send 10 Gigabit Ethernet data through RapidIO, and realize the conversion and transmission of data between the 10 Gigabit Ethernet and the RapidIO network without the participation of a processor.

[0003] The traditional method is that after receiving data through RapidIO and 10 Gigabit Ethernet, the data is stored in the internal storage space of the system, and the processor is used to further process the data. This method will cause performance loss due to the processor frequently handling interrupts. Summary of the Invention

[0004] To solve the technical problems existing in the background art, the present invention provides a high-speed switching system and method for RapidIO and 10 Gigabit Ethernet protocols, providing a hardware circuit without the participation of a processor for the data transmission between the 10 Gigabit Ethernet and RapidIO, reducing the performance loss caused by the processor frequently handling interrupts, and improving the performance of the processor.

[0005] The technical solution of the present invention is: The present invention is a high-speed switching system for RapidIO and 10 Gigabit Ethernet protocols, which is characterized in that: the system includes an APB interface and a register resource module that can access registers, an AXI bus interface module, a DMA start control module, a descriptor generation / parsing module, a memory module, and a buffer application / release module. The APB interface and the register resource module that can access registers are connected to the internal status register through the APB bus. The AXI bus interface module is respectively connected to the memory module and the external AXI bus. The buffer application / release module is respectively connected to the DMA start control module, the descriptor generation / parsing module, and the external buffer management module. The descriptor generation / parsing module is respectively connected to the external descriptor management module and the DMA start control module. The DMA start control module is connected to the external DMA controller.

[0006] Further, the APB interface and the register resource module that can access registers can access or configure the internal status information.

[0007] Further, the AXI bus interface module inputs a storage signal from the memory module or an AXI bus transmission signal; by receiving the read / write request signal of the AXI bus data, according to control information such as the address, the AXI data is stored in / read out from the memory module to realize the storage or reading of the data.

[0008] Further, the DMA start control module inputs descriptor information from the descriptor generation / parsing module. The descriptor contains control information such as the address and data size required for DMA start to control the external DMA to start the data transfer process. At the same time, the input also comes from the address control information of the buffer application / release module.

[0009] Further, the descriptor generation / parsing module inputs the buffer address valid information from the buffer application / release module. The valid address generates corresponding frame descriptors through the buffer application / release module, submits the frame descriptors to the external descriptor management module to complete the data forwarding. At the same time, the external descriptor management module provides frame descriptors to the buffer application / release module, and through parsing, provides descriptor storage address information to the DMA start control module.

[0010] Further, the buffer application / release module inputs the data storage control information from the external buffer management module. After parsing, it submits information such as the address control and data size of the descriptor to the descriptor generation / parsing module, and at the same time submits address information to the DMA start control module.

[0011] Further, the memory module inputs the data storage control information from the AXI bus interface module to complete the process of storing and reading data.

[0012] A method for implementing the above RapidIO and 10 Gigabit Ethernet protocol high-speed switching system, characterized in that: the method includes the following steps:

[0013] 1) The APB interface and register resource module of the accessible register accesses or configures the internal state information of the internal state register through the external APB bus.

[0014] 2) The 10 Gigabit Ethernet module transmits a write request signal for data to the AXI bus interface module through the external AXI bus. According to control information such as the address, it converts the AXI control signal into an internal memory write control signal and stores the data information in the memory module. The 10 Gigabit Ethernet module transmits a read request signal for data to the AXI bus interface module through the external AXI bus. According to control information such as the address, it converts the AXI control signal into an internal memory read control signal and reads the data information from the memory module.

[0015] 3) The external buffer management module transmits the free address information of the external buffer to the buffer application / release module. After processing, it forms address information, and through the descriptor generation / parsing module, in accordance with the frame descriptor format, submits the control information of the address and data to the external descriptor management module in accordance with the frame descriptor format to complete the frame descriptor sending process.

[0016] 4) The descriptor generation / parsing module receives the descriptor information from the external descriptor management module. Through parsing, it generates control information such as data storage addresses and data packet sizes, and transmits it to the DMA start control module. After processing the information, the DMA start control module converts it into control information for a DMA that can complete self-starting. At the same time, it receives the valid buffer address information from the buffer application / release module and transfers the data to the destination.

[0017] The present invention provides a high-speed switching system and method for RapidIO and 10 Gigabit Ethernet protocols, which can encapsulate Ethernet packets into RapidIO data packets, providing a hardware circuit without the participation of a processor for data transmission between 10 Gigabit Ethernet and RapidIO, reducing the overhead of the processor core in aspects such as data distribution and content acceleration processing, and improving communication performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a block diagram of the present invention.

[0019] The reference numerals are as follows:

[0020] 1. APB interface and register resource module with accessible registers; 2. AXI bus interface module; 3. DMA start control module; 4. Descriptor generation / parsing module; 5. Memory module; 6. Buffer application / release module. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The technical solutions of the present invention will be further described in detail below with reference to the drawings and specific embodiments.

[0022] See Figure 1 , the structure of a specific embodiment of the high-speed switching system for RapidIO and 10 Gigabit Ethernet protocols of the present invention includes an APB interface and register resource module 1 with accessible registers, an AXI bus interface module 2, a DMA start control module 3, a descriptor generation / parsing module 4, a memory module 5, and a buffer application / release module 6. It is specifically applied to an existing high-speed switching circuit for RapidIO and 10 Gigabit Ethernet protocols, and the existing high-speed switching circuit for RapidIO and 10 Gigabit Ethernet protocols includes an external APB bus, internal status registers, an external AXI bus, an external DMA controller, an external descriptor management module, and an external buffer management module.

[0023] Among them:

[0024] The APB interface and register resource module 1 with accessible registers is connected to the internal status registers through the APB bus; the on-chip processor can access or configure the internal status registers through the APB bus;

[0025] The AXI bus interface module 2 is connected to the memory module 5 and the external AXI bus. The 10 Gigabit Ethernet module transmits a write request signal of data to the AXI bus interface module 2 through the AXI bus. According to control information such as the address, it converts the AXI control signal into an internal memory write control signal and stores the data information into the memory module 5. The 10 Gigabit Ethernet module transmits a read request signal of data to the AXI bus interface module 2 through the AXI bus. According to control information such as the address, it converts the AXI control signal into an internal memory read control signal and reads the data information from the memory module 5.

[0026] The buffer application / release module 6 is connected to the DMA start control module 3, the descriptor generation / parsing module 4, and the external buffer management module. The external buffer management module transmits the free address information of the external buffer to the buffer application / release module 6. After processing, it forms address information. Through the descriptor generation / parsing module 4, according to the frame descriptor format, it submits the control information of the address and data to the external descriptor management module in the frame descriptor format.

[0027] The descriptor generation / parsing module 4 is connected to the external descriptor management module, the buffer application / release module 6, and the DMA start control module 3. It receives the descriptor information from the external descriptor management module. Through parsing, it generates control information such as the data storage address and the data packet size, and transmits it to the DMA start control module 3. After processing the information, the DMA start control module 3 converts it into control information for a DMA that can complete self-starting. At the same time, it receives the valid buffer address information from the buffer application / release module 6 and transfers the data to the destination.

[0028] The present invention also provides a high-speed switching method for the RapidIO and 10 Gigabit Ethernet protocols. The method includes the following steps:

[0029] 1) The APB interface of the accessible register and the register resource module 1 can access or configure the internal state information of the internal state register through the external APB bus.

[0030] 2) The 10 Gigabit Ethernet module transmits a write request signal of data to the AXI bus interface module 2 through the external AXI bus. According to control information such as the address, it converts the AXI control signal into an internal memory write control signal and stores the data information into the memory module 5. The 10 Gigabit Ethernet module transmits a read request signal of data to the AXI bus interface module 2 through the external AXI bus. According to control information such as the address, it converts the AXI control signal into an internal memory read control signal and reads the data information from the memory module 5.

[0031] 3) The external buffer management module transmits the free address information of the external buffer to the buffer application / release module 6. After processing, address information is formed and submitted to the external descriptor management module as a frame descriptor in accordance with the frame descriptor format through the descriptor generation / parsing module 4, along with the control information of the address and data, thus completing the descriptor sending process;

[0032] 4) The descriptor generation / parsing module 4 receives the descriptor information from the external descriptor management module. Through parsing, control information such as the data storage address and packet size is generated and transmitted to the DMA start control module 3. After processing the information, the DMA start control module 3 converts it into control information for a self-starting DMA. At the same time, it receives the valid buffer address information from the buffer application / release module 6 and transfers the data to the destination.

[0033] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. However, such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A RapidIO and 10 Gigabit Ethernet protocol high-speed switching system, characterized in that: The system includes an APB interface that can access registers, a register resource module, an AXI bus interface module, a DMA start control module, a descriptor generation / parsing module, a memory module, and a buffer application / release module. The APB interface that can access registers and the register resource module are connected to internal status registers through the APB bus. The AXI bus interface module is respectively connected to the memory module and an external AXI bus. The buffer application / release module is respectively connected to the DMA start control module, the descriptor generation / parsing module, and an external buffer management module. The descriptor generation / parsing module is respectively connected to an external descriptor management module and the DMA start control module. The DMA start control module is connected to an external DMA controller. The APB interface that can access registers and the register resource module can access or configure internal status information. The AXI bus interface module inputs storage signals from the memory module and AXI bus transmission signals; by receiving read / write request signals for AXI bus data and according to control information: address, the AXI data is stored into / read out from the memory module to realize data storage and reading. The DMA start control module inputs descriptor information from the descriptor generation / parsing module, where the descriptor contains address and data size control information required for DMA start, and controls the external DMA to start the data transmission process; at the same time, the input also comes from the address control information of the buffer application / release module. The descriptor generation / parsing module inputs buffer address valid information from the buffer application / release module. This buffer address valid information generates corresponding frame descriptors through the buffer application / release module and submits the frame descriptors to the external descriptor management module to complete data forwarding; at the same time, the external descriptor management module provides frame descriptors to the buffer application / release module, and through parsing, provides enqueue address information to the DMA start control module. The buffer application / release module inputs data storage control information from the external buffer management module, and after parsing, submits descriptor address control and data size information to the descriptor generation / parsing module, and at the same time submits address information to the DMA start control module. The memory module inputs data storage control information from the AXI bus interface module to complete the data storage and reading process.

2. A method for implementing a high-speed switching system of the RapidIO and 10 Gigabit Ethernet protocols described in claim 1, characterized in that: The method includes the following steps: 1) The APB interface that can access registers and the register resource module can access or configure the internal status information of the internal status registers through an external APB bus; 2) The 10 Gigabit Ethernet module transmits a write request signal for data to the AXI bus interface module through an external AXI bus. According to control information: address, the AXI control signal is converted into an internal memory write control signal, and the data information is stored into the memory module; the 10 Gigabit Ethernet module transmits a read request signal for data to the AXI bus interface module through an external AXI bus. According to control information: address, the AXI control signal is converted into an internal memory read control signal, and the data information is read out from the memory module; 3) The external buffer management module transmits the free address information of the external buffer to the buffer application / release module. After processing, address information is formed. Through the descriptor generation / parsing module, according to the frame descriptor format, the control information of the address and data is submitted to the external descriptor management module in the frame descriptor format to complete the descriptor sending process; 4) The descriptor generation / parsing module receives the descriptor information from the external descriptor management module. Through parsing, the data storage address and the packet size control information are generated and transmitted to the DMA start control module. After processing the information, the DMA start control module converts it into the control information of the DMA that can complete self-starting. At the same time, it receives the valid buffer address information from the buffer application / release module and transfers the data to the destination.

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