System code-based encryption method, device and equipment

Abstract

This application provides a system code-based encryption method, apparatus, and device. The method includes: acquiring the total number of bits in the data to be encrypted and a preset transfer matrix; wherein the preset transfer matrix is ​​used to indicate the mapping relationship between the operation result of the system code division circuit in the first clock cycle, the operation result of the division circuit in the second clock cycle, and the characters in the data to be encrypted received by the division circuit in the first clock cycle; determining the remainder of the data to be encrypted based on the total number of bits, the data to be encrypted, and the preset transfer matrix; the remainder is used to indicate the remainder after performing a modulo operation between the data to be encrypted and the generator polynomial of the system code; and determining the system code encryption result of the data to be encrypted based on the remainder and the data to be encrypted. By acquiring the preset transfer matrix, the total number of bits in the data to be encrypted, and the data to be encrypted to determine the encryption result, the problem of the long time consumption in determining the remainder using a division circuit in related technologies can be avoided.

Description

Technical Field

[0001] This application relates to the field of data processing, and in particular to an encryption method, apparatus, and device based on system codes. Background Technology

[0002] Currently, in digital communication, data is transmitted in the form of digital signals. To ensure the security of signal transmission, the signals need to be encrypted before being sent. This encryption can be achieved using cyclic codes, which can be further divided into systematic and non-systematic encoding methods.

[0003] In related technologies, when using system code encoding for encryption, a division circuit is typically used to determine the remainder corresponding to the data to be encrypted. The data to be encrypted is the unencrypted digital signal to be transmitted. In this process, the division circuit receives one character from the data to be encrypted in each clock cycle until all characters in the data are input into the division circuit. The result obtained by the division circuit in the last clock cycle is then used as the remainder to be calculated.

[0004] However, in the above process, as the number of characters in the data to be encrypted increases, the number of clock cycles required by the corresponding division circuit also increases, which leads to an increase in the time consumed by the division circuit to determine the remainder, and thus a longer encryption processing time. Summary of the Invention

[0005] This application provides an encryption method, apparatus, and device based on system codes to solve the problem that determining the remainder corresponding to the data to be encrypted using a division circuit in related technologies is time-consuming.

[0006] Firstly, this application provides an encryption method based on system codes, comprising:

[0007] Obtain the total number of bits in the data to be encrypted and a preset transition matrix; wherein, the preset transition matrix is ​​used to indicate the mapping relationship between the operation result of the system code division circuit in the first clock cycle, the operation result of the division circuit in the second clock cycle, and the characters in the data to be encrypted received by the division circuit in the first clock cycle; the division circuit is used to determine the operation result of the first clock cycle based on the characters in the data to be encrypted received in the first clock cycle and the operation result obtained by the division circuit in the second clock cycle, and use the operation result of the last clock cycle as the remainder; the second clock cycle is the clock cycle preceding the first clock cycle;

[0008] Based on the total number of bits, the data to be encrypted, and the preset transition matrix, the remainder of the data to be encrypted is determined; the remainder is used to indicate the remainder after performing a modulo operation between the data to be encrypted and the generator polynomial of the system code.

[0009] Based on the remainder of the data to be encrypted and the data to be encrypted, the system code encryption result of the data to be encrypted is determined.

[0010] In some embodiments, determining the remainder of the data to be encrypted based on the total number of bits, the data to be encrypted, and the preset transition matrix includes:

[0011] For each character contained in the data to be encrypted, based on the number of times the character is in the data to be encrypted and the total number of times, the power of the power operation of the preset transition matrix corresponding to the character is determined; the power result of the power operation of the preset transition matrix is ​​determined, and the product of the power result and the character is taken as the processing result corresponding to the character;

[0012] After summing the processing results corresponding to each character in the data to be encrypted, the remainder of the data to be encrypted is obtained.

[0013] In some embodiments, the division circuit includes a plurality of sequentially arranged registers and a multiplier corresponding to each register; wherein, the result of the division circuit in the first clock cycle is composed of the stored values ​​of each register in the division circuit in the first clock cycle; one of the factors of the multiplier is determined by the generator polynomial of the system code;

[0014] Obtain the total number of bits in the data to be encrypted and the preset transition matrix, including:

[0015] Get the total number of bits in the data to be encrypted;

[0016] Based on the division circuit, a first expression of the register in the first clock cycle is determined, wherein the first expression is used to indicate the mapping relationship between the stored value of the register in the first clock cycle, the stored value of the previous register of the register in the second clock cycle, the stored value of the last register in the division circuit in the second clock cycle, and the character received by the division circuit in the first clock cycle.

[0017] Based on the first expression of each register, a first correspondence is determined under the first clock cycle; wherein, the first correspondence is used to indicate the mapping relationship between the operation result of the division circuit under the first clock cycle, the operation result under the second clock cycle, and the characters received by the division circuit under the clock cycle;

[0018] Based on the first correspondence, the preset transition matrix is ​​determined.

[0019] In some embodiments, the method further includes:

[0020] Based on the first correspondence of each first clock cycle, a second correspondence is determined. The second correspondence is used to indicate the relationship between the total number of bits, the data to be encrypted, the preset transfer matrix, and the remainder.

[0021] In some embodiments, the division circuit includes a plurality of calculation units connected in series, wherein a first input terminal of a non-first calculation unit is connected to the output terminal of the preceding calculation unit; a second input terminal of a non-last calculation unit is connected to the output terminal of the last calculation unit; a first input terminal of the first calculation unit is connected to the output terminal of the last calculation unit; and a second input terminal of the last calculation unit is the input terminal of the division circuit.

[0022] The result of the division circuit in the first clock cycle is composed of the stored values ​​of each calculation unit in the division circuit during the first clock cycle.

[0023] In some embodiments, the plurality of sequentially connected computational units, in the case of a non-last computational unit, includes an adder, a register, and a multiplier. The first and second input terminals of the adder are respectively connected to the output terminal of the register and the output terminal of the multiplier. The input terminal of the multiplier serves as the second input terminal of the non-last computational unit; the input terminal of the register serves as the first input terminal of the non-last computational unit; and the output terminal of the adder serves as the output terminal of the non-last computational unit.

[0024] The last calculation unit includes: a register, an adder, and a switching element; wherein, the input terminal of the register serves as the first input terminal of the last calculation unit; the first input terminal of the adder is connected to the output terminal of the register, the second input terminal of the adder serves as the input terminal of the division circuit, the output terminal of the adder is connected to the first terminal of the switching element, and the second terminal of the switching element serves as the output terminal of the last calculation unit;

[0025] The result of the division circuit in the first clock cycle includes the stored values ​​of each register in the division circuit during the first clock cycle; the value of the multiplier in the calculation unit is determined by the generator polynomial of the system code.

[0026] In some embodiments, the method further includes:

[0027] The encrypted result of the system code is sent to the receiving device.

[0028] Secondly, this application provides an encryption device based on system codes, comprising:

[0029] An acquisition unit is used to acquire the total number of bits in the data to be encrypted and a preset transition matrix; wherein, the preset transition matrix is ​​used to indicate the mapping relationship between the operation result of the system code division circuit in the first clock cycle, the operation result of the division circuit in the second clock cycle, and the characters in the data to be encrypted received by the division circuit in the first clock cycle; the division circuit is used to determine the operation result of the first clock cycle based on the characters in the data to be encrypted received in the first clock cycle and the operation result obtained by the division circuit in the second clock cycle, and use the operation result of the last clock cycle as the remainder; the second clock cycle is the clock cycle preceding the first clock cycle;

[0030] The first determining unit is used to determine the remainder of the data to be encrypted based on the total number of bits, the data to be encrypted, and the preset transition matrix; the remainder is used to indicate the remainder after performing a modulo operation between the data to be encrypted and the generator polynomial of the system code.

[0031] The second determining unit is used to determine the system code encryption result of the data to be encrypted based on the remainder of the data to be encrypted and the data to be encrypted.

[0032] In some embodiments, the first determining unit includes:

[0033] The first determining module is used to determine the power of the power operation of the preset transition matrix corresponding to each character in the data to be encrypted, based on the number of times the character is in the data to be encrypted and the total number of times the character is in the data to be encrypted;

[0034] The second determining module is used to determine the power result of the power operation of the preset transition matrix;

[0035] The third determining module is used to take the product of the exponentiation result and the character as the processing result corresponding to the character;

[0036] The processing module is used to sum the processing results corresponding to each character in the data to be encrypted, and then obtain the remainder of the data to be encrypted.

[0037] In some embodiments, the division circuit includes a plurality of sequentially arranged registers and a multiplier corresponding to each register; wherein, the result of the division circuit in the first clock cycle is composed of the stored values ​​of each register in the division circuit in the first clock cycle; one of the factors of the multiplier is determined by the generator polynomial of the system code;

[0038] The acquisition unit includes:

[0039] The first acquisition module is used to acquire the total number of bits in the data to be encrypted;

[0040] The fourth determining module is used to determine a first expression of the register in the first clock cycle based on the division circuit, wherein the first expression is used to indicate the mapping relationship between the stored value of the register in the first clock cycle, the stored value of the previous register of the register in the second clock cycle, the stored value of the last register in the division circuit in the second clock cycle, and the character received by the division circuit in the first clock cycle.

[0041] The fifth determining module is used to determine a first correspondence in the first clock cycle based on the first expression of each register; wherein the first correspondence is used to indicate the mapping relationship between the operation result of the division circuit in the first clock cycle, the operation result in the second clock cycle, and the characters received by the division circuit in the clock cycle;

[0042] The sixth determining module is used to determine the preset transition matrix based on the first correspondence.

[0043] In some embodiments, the apparatus further includes:

[0044] The third determining unit is used to determine a second correspondence based on the first correspondence of each first clock cycle. The second correspondence is used to indicate the relationship between the total number of bits, the data to be encrypted, the preset transfer matrix, and the remainder.

[0045] In some embodiments, the division circuit includes a plurality of calculation units connected in series, wherein a first input terminal of a non-first calculation unit is connected to the output terminal of the preceding calculation unit; a second input terminal of a non-last calculation unit is connected to the output terminal of the last calculation unit; a first input terminal of the first calculation unit is connected to the output terminal of the last calculation unit; and a second input terminal of the last calculation unit is the input terminal of the division circuit.

[0046] The result of the division circuit in the first clock cycle is composed of the stored values ​​of each calculation unit in the division circuit during the first clock cycle.

[0047] In some embodiments, the plurality of sequentially connected computational units, in the case of a non-last computational unit, includes an adder, a register, and a multiplier. The first and second input terminals of the adder are respectively connected to the output terminal of the register and the output terminal of the multiplier. The input terminal of the multiplier serves as the second input terminal of the non-last computational unit; the input terminal of the register serves as the first input terminal of the non-last computational unit; and the output terminal of the adder serves as the output terminal of the non-last computational unit.

[0048] The last calculation unit includes: a register, an adder, and a switching element; wherein, the input terminal of the register serves as the first input terminal of the last calculation unit; the first input terminal of the adder is connected to the output terminal of the register, the second input terminal of the adder serves as the input terminal of the division circuit, the output terminal of the adder is connected to the first terminal of the switching element, and the second terminal of the switching element serves as the output terminal of the last calculation unit;

[0049] The result of the division circuit in the first clock cycle includes the stored values ​​of each register in the division circuit during the first clock cycle; the value of the multiplier in the calculation unit is determined by the generator polynomial of the system code.

[0050] In some embodiments, the apparatus further includes:

[0051] The sending unit is used to send the encrypted result of the system code to the receiving device.

[0052] Thirdly, this application provides an electronic device, including: a memory and a processor;

[0053] Memory; memory for storing instructions executable by the processor;

[0054] The processor is configured to execute the method as described in any of the first aspects according to the executable instructions.

[0055] Fourthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any of the first aspects.

[0056] Fifthly, this application provides a computer program product comprising a computer program that, when executed by a processor, implements the method described in any one of the first aspects.

[0057] This application provides a system code-based encryption method, apparatus, and device. The method includes: acquiring the total number of bits in the data to be encrypted and a preset transition matrix; wherein the preset transition matrix is ​​used to indicate the mapping relationship between the operation result of the system code division circuit in a first clock cycle, the operation result of the division circuit in a second clock cycle, and the characters in the data to be encrypted received by the division circuit in the first clock cycle; the division circuit is used to determine the operation result of the first clock cycle based on the characters in the data to be encrypted received in the first clock cycle and the operation result obtained by the division circuit in the second clock cycle, and to use the operation result of the last clock cycle as the remainder; the second clock cycle is the clock cycle preceding the first clock cycle; determining the remainder of the data to be encrypted based on the total number of bits, the data to be encrypted, and the preset transition matrix; the remainder is used to indicate the remainder after performing a modulo operation between the data to be encrypted and the generator polynomial of the system code; and determining the system code encryption result of the data to be encrypted based on the remainder and the data to be encrypted. By obtaining the preset transition matrix, the total number of bits in the data to be encrypted, and the data to be encrypted, the encryption result can be determined, avoiding the problem of long time consumption in related technologies when using division circuits to determine the remainder. Attached Figure Description

[0058] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0059] Figure 1 A flowchart illustrating an encryption method based on system codes provided in this application embodiment;

[0060] Figure 2 A flowchart illustrating another encryption method based on system codes provided in this application embodiment;

[0061] Figure 3 This is a schematic diagram of a division circuit provided in an embodiment of this application;

[0062] Figure 4 This is a schematic diagram of another division circuit provided in an embodiment of this application;

[0063] Figure 5 A schematic diagram of the structure of an encryption device based on system codes provided in an embodiment of this application;

[0064] Figure 6 A schematic diagram of the structure of another encryption device based on system code provided in this application embodiment;

[0065] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0066] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0067] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application.

[0068] Currently, in digital communication, to improve the security of signal transmission, existing encoding methods can be used to encrypt the digital signals before transmission. Among commonly used encoding methods, cyclic code encoding is relatively simple to implement for signal encryption and decryption, and therefore, it is often chosen as the encoding method in digital communication.

[0069] Furthermore, cyclic codes can be further divided into two types: systematic codes and non-systematic codes. In the encoding result obtained by the encoding method corresponding to the systematic code, the signal to be encrypted appears in plaintext form in the encrypted result, so that the actual signal to be received (i.e., the previous signal to be encrypted) can be quickly decrypted later.

[0070] In related technologies, when encrypting data using system code encoding, the modulo operation is first performed between the data to be encrypted and the generator polynomial of the system code. The resulting modulo is then concatenated with the original data to obtain the encrypted result. Furthermore, the modulo operation can be performed using a division circuit disclosed in related technologies. However, existing division circuits input multiple characters from the data to be encrypted one by one, processing each character sequentially. When the data to be encrypted contains a large number of characters, the time consumed by the division circuit in performing the modulo operation increases, resulting in low encryption efficiency.

[0071] The encryption method, apparatus, and device based on system codes provided in this application are used to solve the above-mentioned technical problems.

[0072] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0073] Figure 1 A flowchart illustrating an encryption method based on system codes provided in this application is shown below. Figure 1 As shown, the method includes the following steps:

[0074] S101. Obtain the total number of bits in the data to be encrypted and the preset transfer matrix; wherein, the preset transfer matrix is ​​used to indicate the mapping relationship between the operation result of the division circuit of the system code in the first clock cycle, the operation result of the division circuit in the second clock cycle, and the characters in the data to be processed received by the division circuit in the first clock cycle; the division circuit is used to determine the operation result of the first clock cycle based on the characters in the data to be processed received in the first clock cycle and the operation result obtained by the division circuit in the second clock cycle, and take the operation result of the last clock cycle as the remainder; the second clock cycle is the clock cycle preceding the first clock cycle, and the first clock cycle can be understood as any one of the multiple clock cycles corresponding to the process of the division circuit determining the remainder.

[0075] For example, when encryption is required during digital signal transmission, the total number of bits in the data to be encrypted is first determined, that is, the number of characters contained in the data to be encrypted.

[0076] Furthermore, in related technologies, the division circuit receives one character from the data to be encrypted in each clock cycle. Within each clock cycle, the result of the current clock cycle is determined based on the received character and the result of the previous clock cycle. It should be noted that for the first clock cycle of multiple clock cycles, the result of the previous clock cycle can be understood as the initial state value of the division circuit, which can be a binary sequence with a value of 0. After processing through multiple clock cycles, the result obtained by the division circuit in the last clock cycle is the remainder result (i.e., the remainder expression) required when encoding using the system code encoding method. In this application, the remainder expression can be understood as the remainder obtained by dividing the data to be encrypted by the generator polynomial of the system code. Moreover, the generator polynomial of the system code is predetermined; the specific method for determining the generator polynomial can be found in the descriptions of related technologies, and will not be repeated here.

[0077] To avoid the need for processing over multiple clock cycles to obtain the remainder of the data to be encrypted using a division circuit, in this embodiment, based on the division circuit in related technologies, a preset transition matrix is ​​determined to indicate the mapping relationship between the operation result of the division circuit in the first clock cycle, the operation result of the division circuit in the second clock cycle, and the characters in the data to be encrypted received by the division circuit in the first clock cycle, wherein the second clock cycle is the clock cycle preceding the first clock cycle.

[0078] S102. Based on the total number of bits, the data to be encrypted, and the preset transition matrix, determine the remainder of the data to be encrypted; the remainder is used to indicate the remainder after performing a modulo operation between the data to be encrypted and the generator polynomial of the system code.

[0079] For example, after obtaining the total number of bits of the data to be encrypted and the preset transition matrix, the remainder corresponding to the data to be encrypted can be determined based on the total number of bits, the preset transition matrix, and the data to be encrypted.

[0080] In one example, when determining the remainder of the data to be encrypted based on the total number of bits, the data to be encrypted, and the preset transfer matrix, the preset transfer matrix indicates the mapping relationship between the results of two adjacent clock cycles of the division circuit and the input characters. Therefore, based on the data to be encrypted and the preset transfer matrix, the correspondence between the results of the last clock cycle of the division circuit and the data to be encrypted and the preset transfer matrix can be further determined. After that, the remainder corresponding to the data to be encrypted can be directly determined based on this correspondence.

[0081] In one example, the correspondence between the total number of bits of the data to be encrypted, the preset transition matrix, the data to be encrypted, and the remainder corresponding to the data to be encrypted is predetermined, and the remainder can be determined directly based on the above correspondence.

[0082] S103. Based on the remainder of the data to be encrypted and the data to be encrypted, determine the encryption result of the system code of the data to be encrypted.

[0083] For example, in this embodiment, after determining the remainder of the data to be encrypted, the system code encryption result of the data to be encrypted is generated using the remainder of the data to be encrypted and the data to be encrypted.

[0084] Specifically, when generating the system code encryption result, the determined remainder and the data to be encrypted can be concatenated, and the concatenated result can be used as the encryption result of the system code.

[0085] In this embodiment, when encrypting the data to be encrypted using the system code encoding method, the encryption result is determined by obtaining the preset transition matrix, the total number of bits of the data to be encrypted, and the data to be encrypted, thus avoiding the problem of long time consumption in related technologies when using a division circuit to determine the remainder.

[0086] Figure 2 A flowchart illustrating another encryption method based on system codes provided in this application embodiment; as shown in the figure, the method includes the following steps:

[0087] S201. Obtain the total number of bits in the data to be encrypted.

[0088] For example, in this embodiment, when it is necessary to encrypt the data to be encrypted, the total number of bits in the data to be encrypted is first obtained. It should be noted that the data to be encrypted in this application is a digital signal.

[0089] S202. Based on the division circuit, determine the first expression of the register in the first clock cycle, wherein the first expression is used to indicate the mapping relationship between the stored value of the register in the first clock cycle, the stored value of the previous register in the second clock cycle, the stored value of the last register in the division circuit in the second clock cycle, and the characters received by the division circuit in the first clock cycle; the division circuit is used to determine the running result of the first clock cycle based on the characters in the data to be encrypted received in the first clock cycle and the running result obtained by the division circuit in the second clock cycle, and use the running result of the last clock cycle as the remainder; the second clock cycle is the clock cycle preceding the first clock cycle; the division circuit includes multiple sequentially arranged registers and a multiplier corresponding to each register; wherein the running result of the division circuit in the first clock cycle consists of the stored values ​​of each register in the division circuit in the first clock cycle; one of the factors of the multiplier is determined by the generator polynomial of the system code.

[0090] For example, the division circuit described in this embodiment includes multiple sequentially arranged registers, and each register also corresponds to its own multiplier. In the process of determining the remainder using the above-described division circuit, the result of the division circuit's operation in each clock cycle includes the stored values ​​of the registers included in the division circuit in that clock cycle. Furthermore, one of the factors corresponding to the multiplication operation performed by the multiplier is determined by the generator polynomial of the system code. The structural principle of the above-described division circuit is similar to that in related technologies and will not be elaborated upon here.

[0091] When determining the preset transfer matrix, the first expression of each register in the division circuit in the first clock cycle can be determined according to the division circuit in the relevant technology. The first expression can be understood as the transformation rule of the value stored in the register in different clock cycles. Specifically, the first expression can indicate the relationship between the value stored in the register corresponding to the first expression in the first clock cycle, the value stored in the previous register in the second clock cycle, and the characters received by the division circuit in the first clock cycle.

[0092] It should be noted here that in the first expression of the first register among multiple registers, the stored value of the register preceding that register in different clock cycles can be regarded as 0.

[0093] S203. Based on the first expression of each register, determine the first correspondence under the first clock cycle; wherein, the first correspondence is used to indicate the mapping relationship between the operation result of the division circuit under the first clock cycle, the operation result under the second clock cycle, and the characters received by the division circuit under the first clock cycle.

[0094] For example, after determining the first expression of each register in the division circuit, since the result of the division circuit in a certain clock cycle can be represented by the stored values ​​of all registers in the division circuit in that clock cycle, and based on the mapping relationship represented by the first expression of each register, the mapping relationship between the result of the division circuit in the first clock cycle, the result of the division circuit in the second clock cycle, and the character received in the first clock cycle can be determined.

[0095] S204. Based on the first correspondence, determine the preset transition matrix; wherein, the preset transition matrix is ​​used to indicate the mapping relationship between the operation result of the division circuit of the system code in the first clock cycle, the operation result of the division circuit in the second clock cycle, and the characters in the data to be encrypted received by the division circuit in the first clock cycle.

[0096] For example, after determining the first correspondence, the mapping relationship indicated by the first correspondence can be directly used as the preset transition matrix.

[0097] For example, the first expression for each register in the division circuit during the (T+1)th clock cycle can be found in the following formula:

[0098] s r-1 (T+1)=s r-2 (T)+g r-1 (s r-1 (T)+m(T+1))

[0099] s r-2 (T+1)=s r-3 (T)+g r-2 (s r-1 (T)+m(T+1)) ...

[0101] s1(T+1)=s0(T)+g1(s r-1 (T)+m(T+1))

[0102] s0(T+1)=g0(s r-1 (T)+m(T+1))

[0103] Where T is a positive integer; assuming there are r registers in total, where r is a positive integer, s r-1 (T+1) represents the value stored in the r-th register during the (T+1)-th first clock cycle; s0(T+1) represents the value stored in the first register during the (T+1)-th first clock cycle. m(T+1) represents the character in the data to be encrypted received by the division circuit during the (T+1)-th first clock cycle. g r-1 The value of one of the factors used to characterize the multiplier corresponding to the r-th register is determined by the generator polynomial of the system code.

[0104] Based on the first expressions of each of the first registers mentioned above, the first expressions are represented in matrix form, and the results are as follows:

[0105]

[0106] Furthermore, the above matrix representation can be further simplified to obtain the first correspondence:

[0107] S(T+1)=F×(S(T)+M(T+1))

[0108] Here, S(T+1) is the matrix composed of the stored values ​​of each register in the (T+1)th first clock cycle. This matrix can be used to characterize the operating result of the division circuit in the (T+1)th first clock cycle. Similarly, S(T) can be used to characterize the operating result of the division circuit in the Tth first clock cycle; where matrix M(T+1) can be represented as follows:

[0109]

[0110] Matrix F can be represented in the following form:

[0111]

[0112] Therefore, matrix F in the first correspondence mentioned above can be used as the preset transition matrix. It can be seen from the matrix representation of the preset transition matrix that when the generator polynomial corresponding to the system code is determined, the value of the corresponding preset transition matrix is ​​also determined.

[0113] The generator polynomial of the systematic code can be represented by the following expression:

[0114] g(x) = g0 + g1x + ... + g r x r

[0115] In the above generator polynomial, if the characters in the data to be encrypted in this embodiment are binary characters, then g r The value of g0 is always 1.

[0116] It is understood that this embodiment provides a first expression based on each register in the division circuit to determine a second correspondence relationship for indicating the mapping relationship between the operation result of the division circuit in the first clock cycle, the operation result in the second clock cycle, and the characters received by the division circuit in the clock cycle. Based on the above first correspondence relationship, a preset transition matrix can be determined to improve the efficiency of subsequent encryption.

[0117] S205. Based on the first correspondence of each first clock cycle, determine the second correspondence. The second correspondence is used to indicate the relationship between the total number of bits, the data to be encrypted, the preset transfer matrix, and the remainder.

[0118] For example, in this embodiment, the first clock cycle can be understood as any one of the multiple clock cycles corresponding to the process of the division circuit determining the remainder, and each clock cycle corresponds to a first correspondence.

[0119] When determining the second correspondence mentioned above, it is possible to first replace the running result of the clock cycle preceding the last first clock cycle in the first correspondence corresponding to the last first clock cycle among multiple first clock cycles. The replaced correspondence can then indicate the relationship between the running result of the last first clock cycle, the running result during the time interval of one clock cycle from the last first clock cycle, and the characters input in the last two first cycles of the data to be encrypted.

[0120] Based on the first mapping relationship of the remaining first clock cycle, the above replacement process is repeated sequentially to determine the correspondence between the data to be encrypted, the total number of bits of the data to be encrypted, the preset transition matrix and the remainder, that is, the second correspondence.

[0121] For example, based on the expression of the first correspondence in the example illustration in step S204 above, the following substitution derivation can be further performed:

[0122] S(T+1)=F×(S(T)+M(T+1))=F×((F×(S(T-1)+M(T)))+M(T+1))

[0123] =F 2 ×S(T-1)+F 2 ×M(T)+F×M(T+1)

[0124] =F 3 ×S(T-2)+F 3 ×M(T-1)+F 2 ×M(T)+F×M(T+1) ...

[0126] Furthermore, through the above substitution derivation, it can be determined that the result of the division circuit in the last clock cycle (i.e., the remainder) can be characterized by the following expression:

[0127] S(N)=F N ×S(0)+F N ×M(1)+F N-1 ×M(2)+…+F×M(N)

[0128] Where N represents the total number of clock cycles, which is the total number of bits in the data to be encrypted; F is the preset transition matrix mentioned above; S(0) is the initialization result of the division circuit, that is, the initial value of each register in the division circuit, and the initial value of each register can be regarded as 0; the above expression can be regarded as the second correspondence that needs to be determined. Subsequently, when determining the remainder of the data to be encrypted, it can be processed based on the above second correspondence.

[0129] Understandably, by using the first correspondence corresponding to each first clock cycle, a second correspondence can be further determined that can be used to indicate the total number of bits, the data to be encrypted, the preset transfer matrix, and the remainder. This allows the remainder of the data to be encrypted to be determined directly based on the data to be encrypted, the total number of bits, and the preset transfer matrix, without needing to go through multiple clock cycles, thus improving the efficiency of remainder determination.

[0130] S206. For each character contained in the data to be encrypted, based on the number of bits of the character in the data to be encrypted and the total number of bits, determine the power of the power operation of the preset transition matrix corresponding to the character; determine the power of the power operation of the preset transition matrix corresponding to the character; determine the power result of the power operation of the preset transition matrix, and use the product of the power result and the character as the processing result corresponding to the character.

[0131] For example, when determining the remainder of the data to be encrypted, firstly, for each character in the data to be encrypted, based on the number of bits of the character, determine the power corresponding to the preset transition matrix; and determine the power result obtained when the preset transition matrix performs the power operation of that power.

[0132] It is understandable that when determining the power of the preset transition matrix based on the number of digits of the character, the second correspondence obtained above shows that the sum of the power of the preset transition matrix corresponding to the character and the number of digits of the character is the total number of digits of the data to be encrypted. Therefore, the power of the preset transition matrix corresponding to the character can be determined based on the total number of digits of the data to be encrypted and the number of digits of the character.

[0133] Furthermore, when determining the power result corresponding to the transition matrix, one possible implementation is to directly multiply the preset transition matrix once or multiple times to obtain the corresponding power result. Another possible implementation, to avoid slow encryption processing due to multiple multiplication operations, can pre-store multiple power results in the database, and directly search for the required power result in the database when encryption is needed. Yet another possible implementation is that the power results stored in the database can be power results with multiple intervals. For example, the stored power results can be power results corresponding to odd powers such as 1, 3, 5, 7; or power results corresponding to even powers such as 2, 4, 6; or power results with intervals such as 1, 4, 7, 10; or the power can be unequal intervals. Thus, by using the above storage methods, the storage space can be reduced.

[0134] S207. After summing the processing results corresponding to each character in the data to be encrypted, the remainder of the data to be encrypted is obtained.

[0135] For example, after determining the processing result corresponding to each character in the data to be encrypted, the remainder corresponding to the data to be encrypted can be obtained by summing the processing results corresponding to each character.

[0136] S208. Based on the remainder of the data to be encrypted and the data to be encrypted, determine the encryption result of the system code of the data to be encrypted.

[0137] For example, this step can be referred to in step S103, which will not be repeated here.

[0138] It should be noted that steps S202-S205 in this embodiment do not need to be repeated in each encryption process. It is only necessary to determine the preset transition matrix and the second correspondence relationship in advance through the above steps. Subsequently, in each encryption process, based on the preset transition matrix and the pre-determined second correspondence relationship, by executing steps S201 and steps S206-S208, the remainder corresponding to the data to be encrypted can be determined, thereby completing the encryption process and obtaining the encryption result corresponding to the data to be encrypted.

[0139] In this embodiment, when determining the remainder of the data to be encrypted, the power of the preset transition matrix and the corresponding power result are determined based on the number of bits of each character and the total number of bits in the data to be encrypted. Then, the remainder of the data to be encrypted is determined by adding the product of each character and the power result of each character. By using the above method, the problem of consuming a lot of clock cycles when using a division circuit for remainder processing in related technologies can be avoided, thereby improving the encryption efficiency.

[0140] In some embodiments, based on any of the above embodiments, after determining the system code encryption result, the system code encryption result can also be sent to the receiving device. That is, after determining the encryption result of the data to be encrypted, the encryption result can be sent to the data recipient of the data to be encrypted, so as to realize data transmission between different devices; or in some practical application scenarios, when data needs to be stored, the data will also be encrypted before storage, so after obtaining the system code encryption result, it can also be stored in a predetermined database.

[0141] Figure 3 This is a schematic diagram of a division circuit provided in an embodiment of this application, as shown below. Figure 3 As shown, the division circuit includes multiple calculation units connected in series. The first input terminal of a non-first calculation unit is connected to the output terminal of the preceding calculation unit. The second input terminal of a non-last calculation unit is connected to the output terminal of the last calculation unit. The first input terminal of the first calculation unit is connected to the output terminal of the last calculation unit. The second input terminal of the last calculation unit is the input terminal of the division circuit. The result of the division circuit in the first clock cycle consists of the stored values ​​of each calculation unit in the division circuit during the first clock cycle.

[0142] For example, in this embodiment, the division circuit includes multiple calculation units connected in series. Each calculation unit includes two input terminals and one output terminal.

[0143] In a series of sequentially connected computational units, the first input terminal of each unit (excluding the first unit) is connected to the output terminal of the unit preceding it to receive the output result. The second input terminals of each unit (excluding the last unit) are connected to the output terminal of the last unit. Furthermore, the first input terminal of the first unit is also connected to the output terminal of the last unit. The second input terminal of the last unit is used to receive the characters of the data to be encrypted input to the division circuit.

[0144] When a character is input at the second input terminal, the last calculation unit will obtain a processing result based on the result of the previous calculation unit's output received at its first input terminal and the currently received character. Then, it will input the obtained processing result to the second input terminal of the unit other than the last calculation unit and the first input terminal of the first calculation unit. The remaining calculation units will also process the data input at their first and second input terminals to obtain their corresponding calculation results.

[0145] Furthermore, the number of computational units is related to the total number of bits in the data to be encrypted and the total number of bits in the system code encryption result. Also, the division circuit, composed of the stored values ​​corresponding to each computational unit in the first clock cycle, represents the result of the division circuit's operation in the first clock cycle.

[0146] Figure 4 A schematic diagram of another division circuit provided in this application embodiment is shown below. Figure 4 As shown, among the multiple sequentially connected computation units, the non-last computation unit includes an adder, a register, and a multiplier. The first and second input terminals of the adder are connected to the output terminals of the register and the multiplier, respectively. The input terminal of the multiplier serves as the second input terminal of the non-last computation unit. The input terminal of the register serves as the first input terminal of the non-last computation unit. The output terminal of the adder serves as the output terminal of the non-last computation unit.

[0147] The last calculation unit includes: a register, an adder, and a switching element; wherein, the input terminal of the register serves as the first input terminal of the last calculation unit; the first input terminal of the adder is connected to the output terminal of the register, the second input terminal of the adder serves as the input terminal of the division circuit, the output terminal of the adder is connected to the first terminal of the switching element, and the second terminal of the switching element serves as the output terminal of the last calculation unit;

[0148] The result of the division circuit in the first clock cycle includes the stored values ​​of each register in the division circuit during the first clock cycle; the value of the multiplier in the calculation unit is determined by the generator polynomial of the system code.

[0149] For example, in this embodiment, each of the non-last calculation units includes a register, an adder, and a multiplier; wherein, the register can be used to store the stored value of the current clock cycle.

[0150] For calculation units other than the last one: the adder contained therein has two inputs and one output. The first input of the adder is connected to the output of the register in the calculation unit; the second input of the adder is connected to the output of the multiplier in the calculation unit, and the input of the multiplier serves as the second input of the calculation unit; the output of the adder serves as the output of the calculation unit; in addition, the input of the register in the calculation unit serves as the first input of the calculation unit.

[0151] For the last calculation unit: The last calculation unit is equipped with a register, an adder, and a switching element; wherein, the first input terminal of the adder is used to receive characters in the input data to be encrypted, and the second input terminal of the adder is connected to the output terminal of the register to receive the stored value output by the register; the output terminal of the adder is connected to the first terminal of the switching element, and the second terminal of the switching element serves as the output terminal of the calculation unit; the input terminal of the register serves as the first input terminal of the calculation unit.

[0152] In practical applications, when the data to be encrypted is encoded in binary, one of the factors in the multiplier is either 0 or 1, i.e., g in the generator polynomial. n The value of g is 0 or 1, where n is a positive integer in the range [0, r]. r g0 is always 1, and r is the number of registers.

[0153] When determining the remainder and the final encryption result using the division circuit described above, firstly, the switching element is closed, and characters from the data to be encrypted are input one character at a time, starting from the most significant bit; this character also becomes a character in the encryption result. After several clock cycles (where the number of clock cycles is the same as the total number of bits in the data to be encrypted), the stored values ​​in each register are the remainder of the data to be encrypted. Then, the switching element is opened, and after several clock cycles, the stored values ​​in each register at the last clock cycle when the switching element was closed are output sequentially, thus obtaining the encrypted result.

[0154] The data to be encrypted is represented by the following matrix: [m0 m1 … m k-1 ], where k is a positive integer greater than 1, the data to be encrypted contains k characters, m1 is used to represent the second character, the smaller the index of m, the lower the number of bits of the corresponding character.

[0155] Furthermore, during the last clock cycle, the stored values ​​in the registers included in the division circuit are represented by the following matrix [s0 s1 … s r-1 Based on the data to be encrypted and the result obtained in the last clock cycle, the final encryption result can be obtained, which can be represented as follows:

[0156] [s0 s1 … s n-k-1 m0 m1 … m k-1 ]

[0157] Figure 5 A schematic diagram of a system code-based encryption device provided in this application embodiment is shown below. Figure 5 As shown, the device includes:

[0158] The acquisition unit 51 is used to acquire the total number of bits in the data to be encrypted and a preset transfer matrix; wherein, the preset transfer matrix is ​​used to indicate the mapping relationship between the operation result of the division circuit of the system code in the first clock cycle, the operation result of the division circuit in the second clock cycle, and the characters in the data to be encrypted received by the division circuit in the first clock cycle; the division circuit is used to determine the operation result of the first clock cycle based on the characters in the data to be encrypted received in the first clock cycle and the operation result obtained by the division circuit in the second clock cycle, and use the operation result of the last clock cycle as the remainder; the second clock cycle is the clock cycle preceding the first clock cycle;

[0159] The first determining unit 52 is used to determine the remainder of the data to be encrypted based on the total number of bits, the data to be encrypted, and the preset transition matrix; the remainder is used to indicate the remainder after performing a modulo operation between the data to be encrypted and the generator polynomial of the system code.

[0160] The second determining unit 53 is used to determine the system code encryption result of the data to be encrypted based on the remainder of the data to be encrypted and the data to be encrypted.

[0161] The apparatus provided in this embodiment is used to implement the technical solution provided by the above method. Its implementation principle and technical effect are similar, and will not be described again.

[0162] Figure 6 This is a schematic diagram of another encryption device based on system codes provided in an embodiment of this application. Figure 5 Based on the device shown, the first determining unit 52 includes:

[0163] The first determining module 521 is used to determine the power of the power operation of the preset transition matrix corresponding to each character in the data to be encrypted, based on the number of bits of the character in the data to be encrypted and the total number of bits.

[0164] The second determining module 522 is used to determine the power result of the power operation of the preset transition matrix;

[0165] The third determining module 523 is used to take the product of the exponentiation result and the character as the processing result corresponding to the character;

[0166] The processing module 524 is used to sum the processing results corresponding to each character in the data to be encrypted to obtain the remainder of the data to be encrypted.

[0167] In some embodiments, the division circuit includes a plurality of sequentially arranged registers and a multiplier corresponding to each register; wherein, the result of the division circuit in the first clock cycle consists of the stored values ​​of each register in the division circuit in the first clock cycle; one of the factors of the multiplier is determined by the generator polynomial of the system code;

[0168] The acquisition unit 51 includes:

[0169] The first acquisition module 511 is used to acquire the total number of bits in the data to be encrypted;

[0170] The fourth determining module 512 is used to determine a first expression of the register in the first clock cycle based on the division circuit, wherein the first expression is used to indicate the mapping relationship between the stored value of the register in the first clock cycle, the stored value of the previous register in the second clock cycle, the stored value of the last register in the division circuit in the second clock cycle, and the character received by the division circuit in the first clock cycle.

[0171] The fifth determining module 513 is used to determine the first correspondence in the first clock cycle based on the first expression of each register; wherein the first correspondence is used to indicate the mapping relationship between the operation result of the division circuit in the first clock cycle, the operation result in the second clock cycle, and the characters received by the division circuit in the clock cycle;

[0172] The sixth determining module 514 is used to determine the preset transition matrix based on the first correspondence.

[0173] In some embodiments, the apparatus further includes:

[0174] The third determining unit 54 is used to determine a second correspondence based on the first correspondence of each first clock cycle. The second correspondence is used to indicate the relationship between the total number of bits, the data to be encrypted, the preset transfer matrix and the remainder.

[0175] In some embodiments, the division circuit includes a plurality of computing units connected in series, wherein a first input terminal of a non-first computing unit is connected to the output terminal of the preceding computing unit; a second input terminal of a non-last computing unit is connected to the output terminal of the last computing unit; a first input terminal of the first computing unit is connected to the output terminal of the last computing unit; and a second input terminal of the last computing unit is the input terminal of the division circuit.

[0176] The result of the division circuit in the first clock cycle consists of the stored values ​​of each calculation unit in the division circuit during the first clock cycle.

[0177] In some embodiments, a plurality of sequentially connected computational units, the non-last computational unit includes an adder, a register, and a multiplier, wherein the first input terminal and the second input terminal of the adder are respectively connected to the output terminal of the register and the output terminal of the multiplier, the input terminal of the multiplier serves as the second input terminal of the non-last computational unit; the input terminal of the register serves as the first input terminal of the non-last computational unit; and the output terminal of the adder serves as the output terminal of the non-last computational unit.

[0178] The last calculation unit includes: a register, an adder, and a switching element; wherein, the input terminal of the register serves as the first input terminal of the last calculation unit; the first input terminal of the adder is connected to the output terminal of the register, the second input terminal of the adder serves as the input terminal of the division circuit, the output terminal of the adder is connected to the first terminal of the switching element, and the second terminal of the switching element serves as the output terminal of the last calculation unit;

[0179] The result of the division circuit in the first clock cycle includes the stored values ​​of each register in the division circuit during the first clock cycle; the value of the multiplier in the calculation unit is determined by the generator polynomial of the system code.

[0180] In some embodiments, the apparatus further includes:

[0181] The sending unit 55 is used to send the system code encryption result to the receiving device.

[0182] The apparatus provided in this embodiment is used to implement the technical solution provided by the above method. Its implementation principle and technical effect are similar, and will not be described again.

[0183] This application provides an electronic device, including: a memory and a processor;

[0184] Memory; memory used to store processor-executable instructions;

[0185] The processor is used to execute methods according to executable instructions.

[0186] Figure 7This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 7 As shown, the electronic device includes:

[0187] The electronic device includes a processor 291 and a memory 292; it may also include a communication interface 293 and a bus 294. The processor 291, memory 292, and communication interface 293 can communicate with each other via the bus 294. The communication interface 293 can be used for information transmission. The processor 291 can call logical instructions stored in the memory 292 to execute the methods of the above embodiments.

[0188] Furthermore, the logic instructions in the aforementioned memory 292 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0189] The memory 292, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this application. The processor 291 executes functional applications and data processing by running the software programs, instructions, and modules stored in the memory 292, thereby implementing the methods in the above-described method embodiments.

[0190] The memory 292 may include a program storage area and a data storage area. The program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 292 may include high-speed random access memory and may also include non-volatile memory.

[0191] This application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement any of the methods.

[0192] This application provides a computer program product, which includes a computer program that, when executed by a processor, implements any one of the methods.

[0193] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the appended claims.

[0194] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. An encryption method based on system codes, characterized in that, include: Obtain the total number of bits in the data to be encrypted and a preset transition matrix; wherein, the preset transition matrix is ​​used to indicate the mapping relationship between the operation result of the system code division circuit in the first clock cycle, the operation result of the division circuit in the second clock cycle, and the characters in the data to be encrypted received by the division circuit in the first clock cycle; the division circuit is used to determine the operation result of the first clock cycle based on the characters in the data to be encrypted received in the first clock cycle and the operation result obtained by the division circuit in the second clock cycle, and use the operation result of the last clock cycle as the remainder; the second clock cycle is the clock cycle preceding the first clock cycle; Based on the total number of bits, the data to be encrypted, and the preset transition matrix, the remainder of the data to be encrypted is determined; the remainder is used to indicate the remainder after performing a modulo operation between the data to be encrypted and the generator polynomial of the system code. Based on the remainder of the data to be encrypted and the data to be encrypted, the system code encryption result of the data to be encrypted is determined; The determination of the remainder of the data to be encrypted, based on the total number of bits, the data to be encrypted, and the preset transition matrix, includes: For each character contained in the data to be encrypted, based on the number of times the character is in the data to be encrypted and the total number of times, the power of the power operation of the preset transition matrix corresponding to the character is determined; the power result of the power operation of the preset transition matrix is ​​determined, and the product of the power result and the character is taken as the processing result corresponding to the character; After summing the processing results corresponding to each character in the data to be encrypted, the remainder of the data to be encrypted is obtained.

2. The method according to claim 1, characterized in that, The division circuit includes multiple sequentially arranged registers and a multiplier corresponding to each register; wherein, the result of the division circuit in the first clock cycle is composed of the stored values ​​of each register in the division circuit in the first clock cycle; one of the factors of the multiplier is determined by the generator polynomial of the system code; Obtain the total number of bits in the data to be encrypted and the preset transition matrix, including: Get the total number of bits in the data to be encrypted; Based on the division circuit, a first expression of the register in the first clock cycle is determined, wherein the first expression is used to indicate the mapping relationship between the stored value of the register in the first clock cycle, the stored value of the previous register of the register in the second clock cycle, the stored value of the last register in the division circuit in the second clock cycle, and the character received by the division circuit in the first clock cycle. Based on the first expression of each register, a first correspondence is determined under the first clock cycle; wherein, the first correspondence is used to indicate the mapping relationship between the operation result of the division circuit under the first clock cycle, the operation result under the second clock cycle, and the characters received by the division circuit under the clock cycle; Based on the first correspondence, the preset transition matrix is ​​determined.

3. The method according to claim 2, characterized in that, The method further includes: Based on the first correspondence of each first clock cycle, a second correspondence is determined. The second correspondence is used to indicate the relationship between the total number of bits, the data to be encrypted, the preset transfer matrix, and the remainder.

4. The method according to claim 1, characterized in that, The division circuit includes multiple calculation units connected in series. The first input terminal of a non-first calculation unit is connected to the output terminal of the preceding calculation unit. The second input terminal of a non-last calculation unit is connected to the output terminal of the last calculation unit. The first input terminal of the first calculation unit is connected to the output terminal of the last calculation unit. The second input terminal of the last calculation unit is the input terminal of the division circuit. The result of the division circuit in the first clock cycle is composed of the stored values ​​of each calculation unit in the division circuit during the first clock cycle.

5. The method according to claim 4, characterized in that, The plurality of sequentially connected computational units, among which the non-last computational unit includes: an adder, a register, and a multiplier, wherein the first input terminal and the second input terminal of the adder are respectively connected to the output terminal of the register and the output terminal of the multiplier; the input terminal of the multiplier serves as the second input terminal of the non-last computational unit; the input terminal of the register serves as the first input terminal of the non-last computational unit; and the output terminal of the adder serves as the output terminal of the non-last computational unit. The last calculation unit includes: a register, an adder, and a switching element; wherein, the input terminal of the register serves as the first input terminal of the last calculation unit; the first input terminal of the adder is connected to the output terminal of the register, the second input terminal of the adder serves as the input terminal of the division circuit, the output terminal of the adder is connected to the first terminal of the switching element, and the second terminal of the switching element serves as the output terminal of the last calculation unit; The result of the division circuit in the first clock cycle includes the stored values ​​of each register in the division circuit during the first clock cycle; the value of the multiplier in the calculation unit is determined by the generator polynomial of the system code.

6. The method according to any one of claims 1-5, characterized in that, The method further includes: The encrypted result of the system code is sent to the receiving device.

7. An encryption device based on a system code, characterized in that, include: An acquisition unit is used to acquire the total number of bits in the data to be encrypted and a preset transition matrix; wherein, the preset transition matrix is ​​used to indicate the mapping relationship between the operation result of the system code division circuit in the first clock cycle, the operation result of the division circuit in the second clock cycle, and the characters in the data to be encrypted received by the division circuit in the first clock cycle; the division circuit is used to determine the operation result of the first clock cycle based on the characters in the data to be encrypted received in the first clock cycle and the operation result obtained by the division circuit in the second clock cycle, and use the operation result of the last clock cycle as the remainder; the second clock cycle is the clock cycle preceding the first clock cycle; The first determining unit is used to determine the remainder of the data to be encrypted based on the total number of bits, the data to be encrypted, and the preset transition matrix; the remainder is used to indicate the remainder after performing a modulo operation between the data to be encrypted and the generator polynomial of the system code. The first determining unit is specifically configured to, for each character contained in the data to be encrypted, determine the power of the power operation of the preset transition matrix corresponding to the character based on the number of times the character is in the data to be encrypted and the total number of times; determine the power result of the power operation of the preset transition matrix, and use the product of the power result and the character as the processing result corresponding to the character; and after summing the processing results corresponding to each character in the data to be encrypted, obtain the remainder of the data to be encrypted. The second determining unit is used to determine the system code encryption result of the data to be encrypted based on the remainder of the data to be encrypted and the data to be encrypted.

8. An electronic device, comprising: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1-6.

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