An image processing chip, a camera, and an image processing method

Abstract

The present application provides an image processing chip, a camera, and an image processing method. The top-level scheduling module wakes up the configuration arbitration module according to the wake-up signal sent by the first sensor module, and sends an interrupt signal to the main control chip of the second sensor module according to the detection result of the valid information corresponding to the first image collected by the first sensor module. The configuration arbitration module allocates the control authority of the image processing module between the central processing module and the configuration interface. The central processing module controls the image processing module to detect the first image. The configuration interface controls the image processing module to detect the second image collected by the second sensor module according to the control instruction sent by the main control chip. Through the implementation of the solution of the present application, the configuration arbitration module wakes up the central processing module and the configuration interface in stages, and the central processing module and the configuration interface uniformly control the operation of the image processing module via the configuration arbitration module, which can effectively reduce the overall power consumption of the chip and the complexity of the chip design.

Description

Technical Field

[0001] This application relates to the technical field of chip design, and particularly to an image processing chip, a camera, and an image processing method. Background Art

[0002] In practical applications, an image processing chip is used to detect images collected by a sensor module, and the image processing chip can support the detection of different types of images. Currently, an image processing module and multiple control units for controlling the image processing module to perform different image detection behaviors are configured on the image processing chip. Then, multiple paths corresponding to the multiple control units need to be configured for the image processing module, increasing the complexity of chip design; in addition, different control units are usually uniformly awakened in response to a wake-up instruction from a top-level scheduling unit, and the chip operating power consumption is relatively high. Summary of the Invention

[0003] Embodiments of this application provide an image processing chip, a camera, and an image processing method, which can at least solve the problems of high design complexity and high operating power consumption of the image processing chip provided in the related art.

[0004] In a first aspect of the embodiments of this application, an image processing chip is provided, including: a top-level scheduling module, a configuration arbitration module, a central processing module, a configuration interface, and an image processing module. The top-level scheduling module is electrically connected to the configuration arbitration module and the central processing module respectively. The configuration arbitration module is electrically connected to the central processing module, the configuration interface, and the image processing module respectively. The initial states of the configuration arbitration module, the central processing module, the configuration interface, and the image processing module are sleep states;

[0005] The top-level scheduling module is configured to detect a wake-up signal sent by a first sensor module, wake up the configuration arbitration module according to the wake-up signal, and send an interrupt signal to the main control chip of a second sensor module according to the detection result of the valid information corresponding to the first image collected by the first sensor module;

[0006] The configuration arbitration module is configured to allocate the control authority of the image processing module between the central processing module and the configuration interface;

[0007] The central processing module is configured to control the image processing module to detect the first image in a first time period;

[0008] The configuration interface is configured to control the image processing module to detect a second image collected by the second sensor module according to a control instruction sent by the main control chip in a second time period.

[0009] In the second aspect of the embodiments of the present application, a camera is provided, including the image processing chip, the first sensor module, and the second sensor module provided in the first aspect of the embodiments of the present application.

[0010] In the third aspect of the embodiments of the present application, an image processing method is provided, which is applied to the image processing chip provided in the first aspect of the embodiments of the present application. The image processing method includes:

[0011] The top-level scheduling module detects the wake-up signal sent by the first sensor module, and wakes up the configuration arbitration module according to the wake-up signal;

[0012] The configuration arbitration module allocates the control authority of the image processing module to the central processing module;

[0013] The central processing module controls the image processing module to detect the first image collected by the first sensor module in the first time period;

[0014] When the top-level scheduling module receives the valid information detection result corresponding to the first image, it sends an interrupt signal to the main control chip of the second sensor module;

[0015] The configuration arbitration module allocates the control authority of the image processing module to the configuration interface;

[0016] The configuration interface controls the image processing module to detect the second image collected by the second sensor module according to the control instruction sent by the main control chip in the second time period.

[0017] As can be seen from the above, according to the image processing chip, camera, and image processing method provided by the solution of the present application, the top-level scheduling module detects the wake-up signal sent by the first sensor module, and wakes up the configuration arbitration module according to the wake-up signal; the configuration arbitration module allocates the control authority of the image processing module to the central processing module; the central processing module controls the image processing module to detect the first image collected by the first sensor module in the first time period; when the top-level scheduling module receives the valid information detection result corresponding to the first image, it sends an interrupt signal to the main control chip of the second sensor module; the configuration arbitration module allocates the control authority of the image processing module to the configuration interface; the configuration interface controls the image processing module to detect the second image collected by the second sensor module according to the control instruction sent by the main control chip in the second time period. Through the implementation of the solution of the present application, the central processing module and the configuration interface are woken up in stages by the configuration arbitration module, which can effectively reduce the overall power consumption of the chip, and the central processing module and the configuration interface uniformly control the operation of the image processing module via the configuration arbitration module, reducing the complexity of chip design. Description of the Drawings

[0018] Figure 1Schematic structural diagram of an image processing chip provided for the related art;

[0019] Figure 2 Schematic structural diagram of an image processing chip provided for the first embodiment of the present application;

[0020] Figure 3 Schematic structural diagram of a camera provided for the first embodiment of the present application;

[0021] Figure 4 Basic process schematic diagram of an image processing method provided for the second embodiment of the present application;

[0022] Figure 5 Schematic structural diagram of a terminal device provided for the third embodiment of the present application. Detailed implementation manners

[0023] To make the objectives, features, and advantages of the present application more obvious and understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0024] In the description of the embodiments of the present application, it should be understood that the orientation or positional relationships indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0025] In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, the meaning of "a plurality" is two or more, unless otherwise specifically defined.

[0026] In the embodiments of the present application, unless otherwise clearly defined and limited, terms such as "installation", "connection", "connection", "fixation", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific situations.

[0027] The above are only the preferred embodiments of the present application and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

[0028] As Figure 1 shown is a schematic structural diagram of an image processing chip provided by the related art. The image processing chip mainly includes: a top-level scheduling module, a hardware state machine, a configuration interface, and an image processing module. The hardware state machine is integrated inside the top-level scheduling unit. Once integrated, it is not convenient to change, not conducive to later iteration and optimization or adapting to more scenario requirements. Moreover, the top-level scheduling module integrated with the hardware state machine and the configuration interface are respectively connected to the image processing module through a separate channel, resulting in a higher complexity of chip design. In addition, the top-level scheduling module wakes up the configuration interface and the hardware state machine uniformly, and the overall power consumption of the system is relatively large.

[0029] Based on this, in order to solve the problems of high design complexity and working power consumption of the image processing chip provided by the related art, the first embodiment of the present application provides an image processing chip. As Figure 2 shown is a schematic structural diagram of an image processing chip provided by this embodiment. The image processing chip mainly includes: a top-level scheduling module, a configuration arbitration module, a central processing module, a configuration interface, and an image processing module. The top-level scheduling module is electrically connected to the configuration arbitration module and the central processing module respectively. The configuration arbitration module is electrically connected to the central processing module, the configuration interface, and the image processing module respectively. The initial states of the configuration arbitration module, the central processing module, the configuration interface, and the image processing module are in a sleep state; among them,

[0030] The top-level scheduling module is used to detect the wake-up signal sent by the first sensor module, wake up the configuration arbitration module according to the wake-up signal, and send an interrupt signal to the main control chip of the second sensor module according to the detection result of the valid information corresponding to the first image collected by the first sensor module;

[0031] The configuration arbitration module is used to allocate the control authority of the image processing module between the central processing module and the configuration interface;

[0032] A central processing module for controlling an image processing module to detect a first image during a first period;

[0033] A configuration interface for controlling an image processing module to detect a second image collected by a second sensor module according to a control instruction sent by a main control chip during a second period.

[0034] In this embodiment, a low-power and low-cost central processing module and a configuration arbitration module are integrated inside the image processing chip. The central processing module includes, but is not limited to, Cortex M0+, riscv, an embedded CPU with comparable computing power, etc. In a preferred implementation, the central processing module includes a central processing unit, on-chip static memory, and / or non-volatile memory. The central processing unit is electrically connected to the configuration arbitration module, on-chip static memory, and / or non-volatile memory respectively. The central processing unit loads firmware from the non-volatile memory in the reset state. Of course, in actual applications, the non-volatile memory can also be set outside the chip. Setting it on-chip in this embodiment can reduce costs.

[0035] During the operation of the image processing chip, the top-level scheduling module continuously detects whether it receives a wake-up signal (i.e., the wakeup_in signal) sent by the first sensor module. When receiving this wake-up signal, it sends a wake-up instruction to the configuration arbitration module in the sleep state. Then, the configuration arbitration module activates the central processing module and the image processing module, and then allocates the control authority of the image processing module to the central processing module. During the first image processing stage, the central processing module controls the image processing module to detect the image collected by the first sensor module. If a valid detection result is obtained, the top-level scheduling module sends an interrupt signal (i.e., the wakeup_out signal) to the main control chip of the second sensor module outside the chip to wake up the main control chip, and at this time, the top-level scheduling module transfers the control authority of the image processing module to the configuration interface. The configuration interface responds to the control instruction of the main control chip and controls the image processing module to complete the detection of the second image collected by the second sensor module. Of course, when the top-level scheduling module does not receive the wake-up signal, other modules in the chip are in the power-off state, thus not increasing additional power consumption. It should be noted that for the main control chip, the interrupt signal will change its original working state. The initial state of the main control chip of the second sensor module is the sleep state, and when a valid interrupt signal is recognized, it switches to the wake-up state.

[0036] In the preferred implementation manner of this embodiment, the above-mentioned first sensor module is an EVS (Event-based Vision Sensor) module, and the second sensor module is an APS (Active Pixel Sensor) module. Of course, in practical applications, the second sensor module can also be a TOF (Time of Flight) module. This embodiment does not make a unique limitation on this.

[0037] It is worth noting that the EVS module has very low requirements for light and can work well under very low or very bright light conditions. It generates event vectors through changes in light intensity, thereby only outputting the image contours of the parts where the light intensity changes. In this way, compared with traditional image sensors, redundant information can be effectively reduced, and the computational amount of image processing and power consumption can be greatly reduced. The APS module is a traditional image sensor based on CMOS imaging technology, with high image details and image clarity, but also has relatively high power consumption. In practical applications, if the APS module is in the wake-up state for a long time, it will lead to high system power consumption. Based on this, in this embodiment, the EVS module is woken up in the first stage to perform image detection, and basic detection is achieved with low power consumption. If valid information is detected, the APS module is further woken up to further achieve accurate information detection. It should be understood that when detecting EVS images, the supported detection tasks include two types, namely motion detection and target detection. Both detection tasks can achieve intrusion confirmation. In this embodiment, only one of the detection tasks can be executed and after detecting valid information, the APS module can be woken up immediately, or the two detection tasks can be executed serially and after detecting valid information, the APS module can be woken up immediately.

[0038] Taking the license plate information detection scenario as an example, when the system is triggered to work, first the EVS module is woken up to collect EVS images, and then the EVS images are detected by the image processing module, which can specifically include motion detection and target recognition, roughly identifying whether the target entering the monitoring area is a vehicle. If so, valid detection information is obtained, and the APS module is triggered to work continuously. The APS module has relatively high power consumption and resolution, and the APS images collected have richer image details than the EVS images collected by the EVS module. Then, the APS images are subjected to target detection by the image processing module to accurately identify the license plate information of the vehicle in the APS images. Compared with directly triggering a high-power image sensor for accurate recognition in the object approaching scenario, the solution provided in this embodiment can avoid the invalid triggering behavior of the high-power image sensor, reducing the system data processing amount and power consumption.

[0039] It should also be noted that this embodiment can trigger the aforementioned wake-up signal in response to the effective intrusion detection result triggered by the ranging module, that is, before the EVS is triggered, this embodiment uses the ranging module (such as an infrared sensor, lidar, etc.) to continuously detect whether there is an object approaching the monitoring area in real time. If so, an effective intrusion detection result is triggered. Thus, the probability of false awakening of the image sensor module can be further reduced, and the power consumption of the image processing chip can be further reduced.

[0040] In addition, the image processing module of this embodiment may include multiple functional units, such as a motion detection unit, a scaling unit, a target recognition unit, etc. The multiple functional units work alone or in cooperation to complete specific image detection tasks.

[0041] In some embodiments of this embodiment, the configuration arbitration module is further configured to: wake up the first processing unit of the image processing module according to the first image detection task corresponding to the first image; continue to wake up the second processing unit of the image processing module according to the effective information detection result corresponding to the first image detection task; where the first image detection task is motion area recognition, and the second image detection task is target recognition.

[0042] Correspondingly, the central processing module is specifically configured to: asynchronously control the first processing unit and the second processing unit of the image processing module during the first time period to respectively execute the first image detection task and the second image detection task on the first image collected by the first sensor module.

[0043] Specifically, in practical applications, for the image collected by the first sensor module, two different image detection tasks can be executed serially, that is, first perform motion area recognition on the first image to detect whether the first image includes a motion area. If it does not include a motion area, an invalid information detection result corresponding to the first image is generated. If it includes a motion area, an effective information detection result corresponding to the first image detection task is generated; next, further identify whether the motion area includes a specific type of target. If it includes a specific type of target, an effective information detection result corresponding to the overall detection task of the first image is generated. If it does not include a specific type of target, an invalid information detection result corresponding to the first image is generated.

[0044] It should be understood that in the target monitoring scenario, two image detection tasks are executed successively. If two processing units are awakened simultaneously during the wake-up stage of the image processing module, power consumption will be wasted when the second image processing unit is in an idle state. Additionally, since there is no need to further execute the second image detection task for target recognition after generating an invalid information detection result for the first image detection task, awakening the second processing unit during the wake-up stage of the image processing module will cause unnecessary power consumption. Therefore, in this embodiment, different processing units in the image processing module are awakened in stages, and only the processing unit corresponding to the specific image detection task is awakened in each stage, which can effectively reduce the overall power consumption of the system.

[0045] In some other embodiments of this embodiment, the configuration arbitration module is further configured to: determine a target processing unit from the image processing module according to the task type of the image detection task, and control the awakening of the target processing unit.

[0046] Specifically, the image processing module of this embodiment is configured with multiple processing units, and according to different image detection tasks, the required processing units may be different, that is, not all image detection tasks require all processing units to cooperate to complete. Therefore, when the image processing module executes an image detection task, if all processing units in the image processing module are controlled to be awakened simultaneously, some processing units will be in an idle state, resulting in unnecessary power consumption. Based on this, when awakening the image processing module, the configuration arbitration module of this embodiment adaptively awakens specific processing units in the image processing module according to the actual image detection task, saving power while ensuring the effective execution of the image detection task.

[0047] In some embodiments of this embodiment, the top-level scheduling module is further configured to: send a sleep instruction to the configuration arbitration module according to the invalid information detection result corresponding to the first image; the configuration arbitration module is further configured to: control the central processing module, the image processing module, and itself to enter the sleep state according to the sleep instruction.

[0048] Specifically, the valid information detection result of this embodiment indicates that valid information (such as a moving area, a specific type of target) is detected in the first image, while the invalid information detection result indicates that there is no valid information in the first image. If the first image collected by the first sensor module does not contain valid information, the top-level scheduling module controls each module to enter the sleep state again to save system power consumption.

[0049] In some implementation manners of this embodiment, the top-level scheduling module is further configured to: obtain the information detection result directly reported by the image processing module; or, the central processing module is further configured to: receive the image recognition result reported by the image processing module via the configuration arbitration module, obtain the information detection result according to the image recognition result, and report the information detection result to the top-level scheduling module; wherein, the information detection result includes a valid information detection result and an invalid information detection result.

[0050] Specifically, in this embodiment, for the implementation manner of reporting the information detection result to the top-level scheduling module, in one implementation, the image processing module can be electrically connected to the top-level scheduling module, and then after the image processing module directly completes the image detection, it can report the corresponding information detection result to the top-level scheduling module; in another implementation, after the image processing module completes the image detection, it reports the image recognition result to the central processing module via the configuration arbitration module, and then the central processing module further obtains the information detection result according to the image recognition result, and finally the central processing unit reports the information detection result to the top-level scheduling module.

[0051] As Figure 3 shown is a schematic structural diagram of a camera provided in this embodiment. The camera includes the image processing chip 301, the first sensor module 302, and the second sensor module 303 described in the foregoing embodiment. According to the low-power chip architecture with a configurable wake-up process, it can fundamentally solve the problem of inflexible process solidification caused by the inability to control the wake-up process with software during the hardware wake-up process of the camera, and can adapt to more complex and specific scenarios. On the one hand, the increase in the area of the image processing chip can be ignored, which is beneficial to chip cost control; on the other hand, during normal use, the central processing module does not work, and the increase in static power consumption is also very limited. In the deep sleep state, the central processing module is in a power-down mode and does not generate power consumption at all.

[0052] Based on the technical solution of the embodiment of the present application above, the top-level scheduling module detects the wake-up signal sent by the first sensor module and wakes up the configuration arbitration module according to the wake-up signal; the configuration arbitration module allocates the control authority of the image processing module to the central processing module; the central processing module controls the image processing module to detect the first image collected by the first sensor module in the first period; when the top-level scheduling module receives the valid information detection result corresponding to the first image, it sends an interrupt signal to the main control chip of the second sensor module; the configuration arbitration module allocates the control authority of the image processing module to the configuration interface; the configuration interface controls the image processing module to detect the second image collected by the second sensor module according to the control instruction sent by the main control chip in the second period. Through the implementation of the solution of the present application, the central processing module and the configuration interface are woken up in stages by the configuration arbitration module, which can effectively reduce the overall power consumption of the chip, and the central processing module and the configuration interface uniformly control the operation of the image processing module via the configuration arbitration module, reducing the complexity of chip design.

[0053] To solve the problems of high design complexity and working power consumption of the image processing chip provided in the related art, the second embodiment of the present application provides an image processing method, which is applied to the image processing chip provided in the first embodiment. As Figure 4 is the basic process schematic diagram of the image processing chip provided in this embodiment, and this image processing method includes the following steps:

[0054] Step 401, the top-level scheduling module detects the wake-up signal sent by the first sensor module and wakes up the configuration arbitration module according to the wake-up signal;

[0055] Step 402, the configuration arbitration module allocates the control authority of the image processing module to the central processing module;

[0056] Step 403, the central processing module controls the image processing module to detect the first image collected by the first sensor module in the first period;

[0057] Step 404, when the top-level scheduling module receives the valid information detection result corresponding to the first image, it sends an interrupt signal to the main control chip of the second sensor module;

[0058] Step 405, the configuration arbitration module allocates the control authority of the image processing module to the configuration interface;

[0059] Step 406, the configuration interface controls the image processing module to detect the second image collected by the second sensor module according to the control instruction sent by the main control chip in the second period.

[0060] In an implementation manner of this embodiment, the image processing method further includes the following steps: when the top-level scheduling module receives the invalid information detection result corresponding to the first image, it sends a sleep instruction to the configuration arbitration module; the configuration arbitration module controls the central processing module, the image processing module, and itself to enter the sleep state according to the sleep instruction.

[0061] In an implementation manner of this embodiment, after the step in which the central processing module controls the image processing module to detect the first image collected by the first sensor module in the first time period, it further includes: the top-level scheduling module obtains the information detection result reported by the image processing module via the configuration arbitration module.

[0062] In another implementation manner of this embodiment, after the step in which the central processing module controls the image processing module to detect the first image collected by the first sensor module in the first time period, it further includes: the central processing module receives the image recognition result directly reported by the image processing module, then obtains the information detection result according to the image recognition result, and then reports the information detection result to the top-level scheduling module.

[0063] In an implementation manner of this embodiment, the step in which the configuration arbitration module allocates the control authority of the image processing module to the central processing module specifically includes: the configuration arbitration module controls the first processing unit of the image processing module to wake up according to the first image detection task corresponding to the first image, and then allocates the control authority of the first processing unit to the central processing module; the configuration arbitration module continues to control the second processing unit of the image processing module to wake up according to the valid information detection result corresponding to the first image detection task, and then allocates the control authority of the second processing unit to the central processing module; wherein, the first image detection task is motion area recognition, and the second image detection task is target recognition. Correspondingly, the step in which the central processing module controls the image processing module to detect the first image collected by the first sensor module in the first time period specifically includes: the central processing module asynchronously controls the first processing unit and the second processing unit of the image processing module in the first time period to respectively execute the first image detection task and the second image detection task for the first image collected by the first sensor module.

[0064] In an implementation manner of this embodiment, the step in which the configuration arbitration module allocates the control authority of the image processing module to the central processing module specifically includes: the configuration arbitration module determines the target processing unit from the image processing module according to the task type of the image detection task, controls the target processing unit to wake up, and then allocates the control authority of the target processing unit to the central processing module.

[0065] It should be noted that the image processing chip in the first embodiment can be applied to the image processing method provided in this embodiment. Those of ordinary skill in the art can clearly understand that for the convenience and simplicity of description, the specific working process of the image processing method described in this embodiment can refer to the corresponding product in the foregoing first embodiment and will not be elaborated here.

[0066] Based on the technical solution of the embodiment of the present application above, the top-level scheduling module detects the wake-up signal sent by the first sensor module and wakes up the configuration arbitration module according to the wake-up signal; the configuration arbitration module allocates the control authority of the image processing module to the central processing module; the central processing module controls the image processing module to detect the first image collected by the first sensor module in the first period; when the top-level scheduling module receives the valid information detection result corresponding to the first image, it sends an interrupt signal to the main control chip of the second sensor module; the configuration arbitration module allocates the control authority of the image processing module to the configuration interface; the configuration interface controls the image processing module to detect the second image collected by the second sensor module according to the control instruction sent by the main control chip in the second period. Through the implementation of the solution of the present application, the central processing module and the configuration interface are woken up in stages by the configuration arbitration module, which can effectively reduce the overall power consumption of the chip, and the central processing module and the configuration interface uniformly control the operation of the image processing module via the configuration arbitration module, reducing the complexity of chip design.

[0067] Figure 5 A terminal device provided in the third embodiment of the present application. This terminal device can be used to implement the image processing method in the foregoing second embodiment, and mainly includes:

[0068] A memory 501, a processor 502, and a computer program 503 stored on the memory 501 and executable on the processor 502. The memory 501 and the processor 502 are communicatively connected. When the processor 502 executes the computer program 503, the method in the foregoing second embodiment is implemented. Among them, the number of processors can be one or more.

[0069] The memory 501 can be a high-speed random access memory (RAM, Random Access Memory) or a non-volatile memory, such as a disk memory. The memory 501 is used to store executable program code, and the processor 502 is coupled to the memory 501.

[0070] Furthermore, the embodiment of the present application also provides a computer-readable storage medium, which can be set in the terminal device in the above embodiments, and the computer-readable storage medium can be the memory in the foregoing Figure 5 illustrated embodiments.

[0071] A computer program is stored on the computer-readable storage medium. When the program is executed by a processor, it implements the image processing method in the foregoing embodiments. Further, the computer-readable storage medium may also be various media such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a RAM, a magnetic disk, or an optical disc that can store program codes.

[0072] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of the apparatus or module can be in an electrical, mechanical or other form.

[0073] The modules described as separate components may or may not be physically separated. The components displayed as modules may or may not be physical modules, that is, they may be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0074] In addition, in each embodiment of the present application, the functional modules can be integrated into one processing module, or each module can exist physically alone, or two or more modules can be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software functional modules.

[0075] If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a readable storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the various embodiments of the present application. And the foregoing readable storage medium includes: various media such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disc that can store program codes.

[0076] It should be noted that, for the foregoing method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited by the described action sequence, because according to this application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0077] In the above embodiments, the descriptions of the respective embodiments have their own focuses. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0078] The above is the description of the image processing chip, camera, and image processing method provided by this application. For those skilled in the art, according to the idea of the embodiments of this application, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to this application.

Claims

1. An image processing chip, characterized in that, Including: A top-level scheduling module, a configuration arbitration module, a central processing module, a configuration interface, and an image processing module. The top-level scheduling module is electrically connected to the configuration arbitration module and the central processing module respectively. The configuration arbitration module is electrically connected to the central processing module, the configuration interface, and the image processing module respectively. The initial states of the configuration arbitration module, the central processing module, the configuration interface, and the image processing module are sleep states; The top-level scheduling module is used to detect a wake-up signal sent by a first sensor module, wake up the configuration arbitration module according to the wake-up signal, and send an interrupt signal to the main control chip of a second sensor module according to a detection result of valid information corresponding to a first image collected by the first sensor module; The configuration arbitration module is used to allocate the control authority of the image processing module between the central processing module and the configuration interface; The central processing module is used to control the image processing module to detect the first image in a first time period; The configuration interface is used to control the image processing module to detect a second image collected by the second sensor module according to a control instruction sent by the main control chip in a second time period.

2. The image processing chip according to claim 1, characterized in that, The first sensor module is an EVS module and / or the second sensor module is an APS module.

3. The image processing chip according to claim 1, characterized in that, The central processing module includes a central processing unit, an on-chip static memory, and / or a non-volatile memory. The central processing unit is electrically connected to the configuration arbitration module, the on-chip static memory, and / or the non-volatile memory respectively.

4. The image processing chip according to claim 1, characterized in that, The top-level scheduling module is further used to: send a sleep instruction to the configuration arbitration module according to a detection result of invalid information corresponding to the first image; The configuration arbitration module is further used to: control the central processing module, the image processing module, and itself to enter a sleep state according to the sleep instruction; 5. The image processing chip according to claim 4, characterized in that, The top-level scheduling module is further used to: obtain a detection result of information directly reported by the image processing module; Or, the central processing module is further used to: receive an image recognition result reported by the image processing module via the configuration arbitration module, obtain a detection result of information according to the image recognition result, and report the detection result of information to the top-level scheduling module; Wherein, the detection result of information includes the detection result of valid information and the detection result of invalid information.

6. The image processing chip according to any one of claims 1 to 5, characterized in that, The configuration arbitration module is further used to: control a first processing unit of the image processing module to wake up according to a first image detection task corresponding to the first image; continue to control a second processing unit of the image processing module to wake up according to a detection result of valid information corresponding to the first image detection task; wherein, the first image detection task is motion area recognition, and the second image detection task is target recognition; The central processing module is specifically configured to: asynchronously control the first processing unit and the second processing unit of the image processing module in a first time period to respectively execute the first image detection task and the second image detection task on the first image collected by the first sensor module.

7. The image processing chip according to any one of claims 1 to 5, characterized in that, The configuration arbitration module is further configured to: determine a target processing unit from the image processing module according to the task type of the image detection task, and control the target processing unit to wake up.

8. A camera, characterized in that, It includes the image processing chip, the first sensor module, and the second sensor module according to any one of claims 1 to 7.

9. An image processing method, applied to the image processing chip according to any one of claims 1 to 7, characterized in that, It includes: The top-level scheduling module detects a wake-up signal sent by the first sensor module, and wakes up the configuration arbitration module according to the wake-up signal; The configuration arbitration module allocates the control authority of the image processing module to the central processing module; The central processing module controls the image processing module to detect the first image collected by the first sensor module in a first time period; When the top-level scheduling module receives a valid information detection result corresponding to the first image, it sends an interrupt signal to the main control chip of the second sensor module; The configuration arbitration module allocates the control authority of the image processing module to the configuration interface; The configuration interface controls the image processing module to detect the second image collected by the second sensor module according to the control instruction sent by the main control chip in a second time period.

10. The image processing method according to claim 9, characterized in that, It further includes: When the top-level scheduling module receives an invalid information detection result corresponding to the first image, it sends a sleep instruction to the configuration arbitration module; The configuration arbitration module controls the central processing module, the image processing module, and itself to enter a sleep state according to the sleep instruction.

Images