Electronic packaging and manufacturing method thereof

Abstract

An electronic package and its manufacturing method include covering a plurality of electronic components with a packaging layer, wherein the packaging layer is defined as a spacing structure between at least two adjacent ones of the plurality of electronic components, and a recess is formed on the spacing structure to serve as a heat insulation area. Through the design of the heat insulation area, the plurality of electronic components can be effectively insulated from each other to prevent the heat generated by the high-power electronic components from being transferred to the low-power electronic components, thereby preventing the heat from affecting the operation of the low-power electronic components.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, in particular to an electronic package and a manufacturing method thereof. Background Art

[0002] With the rapid development of 5G, demand for electronic products is trending towards heterogeneous integration. To shorten the wiring distance between high-performance processing chips and memory and enhance signal integrity, multi-chip packaging (MCM / MCP) structures are gradually emerging to meet the demand for integrating high-performance processing chips with memory (DDR / HBW memory) in a single package.

[0003] like Figure 1 The multi-chip package structure 1 shown includes multiple semiconductor chips 11a, 11b bonded to a package substrate 10 via multiple solder bumps 13, and then formed into an encapsulation material 14 covering the multiple semiconductor chips 11a, 11b. By packaging multiple semiconductor chips into a single chip, this structure offers a higher number of I / Os, significantly increasing processor computing power and reducing signal transmission delays, enabling its application in high-end products with high-density circuits, high transmission speeds, high stacking counts, and large dimensions.

[0004] In addition, the operating temperature range of the conventional memory-type semiconductor chip 11 a needs to be strictly controlled to maintain normal operation.

[0005] However, a semiconductor chip 11b with high computing capabilities, such as a system-on-chip (SoC), generates a large amount of heat during operation. Therefore, when the semiconductor chips 11a and 11b are integrated into the same packaging material 14, the heat generated by the semiconductor chip 11b with high computing capabilities during operation will significantly affect the operation of the semiconductor chip 11a in the form of a memory.

[0006] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Summary of the Invention

[0007] In view of the above-mentioned defects of the prior art, the present invention provides an electronic package and a manufacturing method thereof, which can effectively insulate against heat.

[0008] The electronic package of the present invention comprises: a plurality of electronic components; and a packaging layer covering the plurality of electronic components, wherein the packaging layer is defined as a spacing structure between at least two adjacent electronic components, and a recess is formed on the spacing structure to serve as a heat insulation area.

[0009] The present invention also provides a method for manufacturing an electronic package, comprising: providing a plurality of electronic components; covering the plurality of electronic components with a packaging layer, wherein the packaging layer is defined as a spacing structure between at least two adjacent electronic components; and forming a recess on the spacing structure so that the recess serves as a heat insulation area.

[0010] In the aforementioned electronic package and its manufacturing method, the heat insulation area is in an air state.

[0011] In the aforementioned electronic package and its manufacturing method, the heat insulation area is filled with insulating material.

[0012] In the aforementioned electronic package and its manufacturing method, the thermal conductivity of the heat-insulating area is smaller than the thermal conductivity of the packaging layer.

[0013] In the aforementioned electronic package and its manufacturing method, the thermal conductivity of the thermal insulation area is less than 0.02 W / mK.

[0014] In the aforementioned electronic package and its manufacturing method, the width of the recess is at least 50 microns.

[0015] In the aforementioned electronic package and its manufacturing method, the recess does not penetrate the spacer structure. For example, the thickness of the packaging layer at the spacer structure is at least 10 microns.

[0016] The aforementioned electronic package and method of manufacturing the same further include supporting and electrically connecting the plurality of electronic components via a supporting structure, wherein the supporting structure has two opposing sides, such that the plurality of electronic components are disposed on one of the two opposing sides of the supporting structure, and a plurality of conductive elements are disposed on the other of the two opposing sides of the supporting structure. For example, the recess extends to the supporting structure. Furthermore, the recess penetrates the supporting structure.

[0017] In the aforementioned electronic package and its manufacturing method, the electronic component has an active surface and an inactive surface opposite to each other and side surfaces adjacent to the active surface and the inactive surface, so that the spacing structure connects the side surfaces of the plurality of electronic components. For example, the recess exposes the side surface of the electronic component.

[0018] The aforementioned electronic package and method for manufacturing the same further includes a heat sink bonded to the plurality of electronic components, covering the recess. For example, the heat sink is bonded to the plurality of electronic components via a bonding layer. Furthermore, the bonding layer fills the recess but does not completely fill the recess.

[0019] From the above, it can be seen that the electronic package and its manufacturing method of the present invention mainly achieve effective thermal insulation between the electronic components through the design of the insulation area, so as to prevent the high-power electronic components from transferring the heat they generate to the low-power electronic components. Therefore, compared with the existing technology, the present invention can effectively prevent the heat generated by the high-power electronic components from affecting the operation of the low-power electronic components, thereby improving the reliability of the electronic package. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Schematic diagram of the cross section of an existing multi-chip packaging structure.

[0021] Figures 2A to 2C The figure is a schematic cross-sectional view of a method for manufacturing an electronic package according to the present invention.

[0022] Figure 2B-1 for Figure 2B A partial top view schematic diagram of .

[0023] Figure 2C-1 for Figure 2C A partial cross-sectional enlarged view of another embodiment of the present invention.

[0024] Figure 3 for Figure 2A An enlarged cross-sectional view of another method of manufacturing the same.

[0025] Figure 4A and Figure 4B Schematic partial cross-sectional views of different embodiments of the electronic package of the present invention.

[0026] Figure 4B-1 for Figure 4B The overall schematic top view of the electronic package is shown.

[0027] Figure 4B-2 and Figure 4B-3 for Figure 4B-1 A top schematic diagram of other embodiments of the present invention.

[0028] Description of Reference Numerals

[0029] 1: Multi-chip packaging structure

[0030] 10:Packaging substrate

[0031] 11a, 11b: semiconductor chips

[0032] 13:Solder bumps

[0033] 14: Packaging materials

[0034] 2: Electronic packaging

[0035] 2a: Multi-chip package

[0036] 20: Bearing structure

[0037] 21: Electronic components

[0038] 21a: Action surface

[0039] 21b: Non-active surface

[0040] 21c, 23c, 43c: Side

[0041] 210: conductive bump

[0042] 22,32: Encapsulation layer

[0043] 22a: First surface

[0044] 22b, 32b: Second surface

[0045] 220,320,420,421: concave part

[0046] 23,43: Interval structure

[0047] 24: Conductive element

[0048] 25: Binding layer

[0049] 26: Heat sink

[0050] A: Gap

[0051] D: Width

[0052] H,H1,H2: Depth

[0053] P: Insulation area

[0054] S: airflow space

[0055] t: thickness. DETAILED DESCRIPTION

[0056] The following describes the embodiments of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0057] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment in size should still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and objectives that can be achieved by the present invention. At the same time, terms such as "upper", "lower", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0058] Figures 2A to 2C It is a cross-sectional schematic diagram of a method for manufacturing the electronic package 2 of the present invention.

[0059] like Figure 2AAs shown, a multi-chip package 2 a is provided, which includes a supporting structure 20 , a plurality of electronic components 21 and a packaging layer 22 .

[0060] The supporting structure 20 may be, for example, a package substrate having a core layer and a circuit structure, a package substrate having a coreless circuit structure, a through-silicon interposer (TSI) with conductive through-silicon vias (TSVs), or other board types including at least one insulating layer and at least one circuit layer bonded to the insulating layer, such as at least one fan-out redistribution layer (RDL). It should be understood that the supporting structure 20 may also be other chip-carrying board materials, such as a leadframe, wafer, or other board with metal routing, and is not limited to the above.

[0061] In this embodiment, the carrier substrate of the supporting structure 20 can be manufactured in a variety of ways. For example, a wafer-based process can be used to manufacture the circuit layer, where silicon nitride or silicon oxide is formed as the insulating layer via chemical vapor deposition (CVD). Alternatively, a conventional non-wafer-based process can be used to form the circuit layer, where a relatively low-cost polymer dielectric material such as polyimide (PI), polybenzoxazole (PBO), prepreg (PP), molding compound, photosensitive dielectric layer, or other materials can be used as the insulating layer via coating.

[0062] In addition, the supporting structure 20 can form a plurality of conductive elements 24 (such as Figure 2B ), serving as an external contact for connecting to an electronic device such as a circuit board (not shown). Specifically, the conductive element 24 can be a metal pillar such as a copper pillar, a metal bump coated with an insulating block, a solder ball, a solder ball with a copper core ball, or other conductive structures.

[0063] The plurality of electronic components 21 are disposed separately from each other on the upper side of the supporting structure 20 .

[0064] The electronic component 21 is an active component, a passive component, or a combination thereof. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, or an inductor. In this embodiment, the electronic component 21 is a semiconductor chip having an active surface 21a and an inactive surface 21b opposite each other, and a side surface 21c adjacent to the active surface 21a and the inactive surface 21b. The electrode pads on the active surface 21a are flip-chip mounted on the support structure 20 via a plurality of conductive bumps 210, such as solder, metal pillars, or other materials, and electrically connected to the circuit layer. Alternatively, the electronic component 21 can be electrically connected to the circuit layer of the support structure 20 via a plurality of bonding wires (not shown) via bonding. Alternatively, the electronic component 21 can directly contact the circuit layer of the support structure 20. Therefore, the desired type and number of electronic components can be mounted on the support structure 20 to enhance its electrical functionality. There are many ways to electrically connect the electronic component 21 to the support structure 20, and they are not limited to the above.

[0065] In addition, a gap A is formed between two adjacent side surfaces 21 c of the electronic components 21 .

[0066] The packaging layer 22 is formed on the supporting structure 20 and in the gap A to cover the electronic components 21 .

[0067] In this embodiment, the packaging layer 22 is formed of an insulating material, such as polyimide (PI) or epoxy resin packaging colloid, which can be formed by molding, lamination, or coating.

[0068] In addition, the packaging layer 22 has a first surface 22a and a second surface 22b opposite to each other, and the first surface 22a is combined with the supporting structure 20, and the inactive surface 21b of the electronic component 21 is flush with the second surface 22b of the packaging layer 22, so that the electronic components 21 are exposed on the second surface 22b of the packaging layer 22. Alternatively, the packaging layer 32 can also cover the inactive surface 21b of the electronic component 21, such as Figure 3 As shown, the second surface 32b of the packaging layer 32 is higher than the inactive surface 21b of the electronic component 21. It should be understood that Figure 3 The encapsulation layer 32 shown is subjected to a flattening process on its second surface 32b by grinding, cutting or etching, etc. Figure 2A An embodiment of the encapsulation layer 22 is shown.

[0069] In addition, the encapsulation layer 22 fills the gap A to serve as a spacing structure 23 between at least two adjacent electronic components 21 of the plurality of electronic components 21. For example, the spacing structure 23 is connected to the side surfaces 21c of the adjacent electronic components 21, so that the electronic components 21 are connected to each other.

[0070] like Figure 2B As shown, a recess 220 is formed on the second surface 22b of the packaging layer 22 corresponding to each of the spacing structures 23. A plurality of conductive elements 24 are formed on the underside of the supporting structure 20 and are electrically connected to the supporting structure 20.

[0071] In this embodiment, a portion of the packaging layer 22 is removed by cutting, laser or etching to form the recess 220, and the width D of the recess 220 can be consistent from the notch to the bottom (i.e., the width D of the recess 220 from top to bottom) (e.g., Figure 2B Further, the recess 220 communicates with the two side surfaces 23c of the front and rear sides of the spacing structure 23, as shown in FIG. Figure 2B-1 shown.

[0072] In addition, the depth H of the recess 220 can be designed according to the requirements, such as Figure 2B The recess 220 shown does not penetrate the spacing structure 23 (for example, the bottom surface of the recess 220 and the active surface 21a of the electronic component 21 are roughly at the same height relative to the supporting structure 20); or, the depth of the recess 220 can penetrate the spacing structure 23 and expose the surface of the supporting structure 20.

[0073] Or, as Figure 4A The depth H1 of the recess 420 shown in FIG. 1 extends to the supporting structure 20 and may even penetrate the supporting structure 20 (eg, Figure 4B As shown in FIG. 4 , the depth H2 of the recess 421 is shown. It should be understood that when the recess 421 passes through the supporting structure 20, the recess 421 may not separate the two side surfaces 43c of the front and rear sides of the spacing structure 43 as required. Figure 4B-1 As shown, the spacing structure 43 may even include a plurality of recesses 421, such as Figure 4B-2 or Figure 4B-3 If the recess 421 is selected to disconnect the two opposite side surfaces 43c of the spacing structure 43, the packaging layer 22 can be connected to the heat sink 26 via the bonding layer 25 described later.

[0074] In addition, when the recess 220 does not penetrate the spacing structure 23, a distance of at least 10 micrometers (um) can be maintained between the bottom surface of the recess 220 and the supporting structure 20, that is, the thickness t of the packaging layer 22 at the spacing structure 23 is at least 10 micrometers (um), so as to increase the strength of the electronic package 2.

[0075] In addition, if Figure 2CAs shown, in subsequent processes, a bonding layer 25 can be formed on the inactive surface 21b of the electronic component 21 and the second surface 22b of the packaging layer 22 as needed, exposing the recess 220. Next, a heat sink 26 is placed on the inactive surface 21b of the plurality of electronic components 21 through the bonding layer 25, and the bonding layer 25 is then thermally cured.

[0076] In this embodiment, the bonding layer 25 is a liquid heat dissipation adhesive or other resin adhesive to serve as a thermal interface material (TIM). The bonding layer 25 will not fill the recess 220. Even if the bonding layer 25 fills the recess 220, it will not fill the recess 220 completely. Figure 2C-1 As shown, the recess 220 forms an air flow space S connected to the heat sink 26 .

[0077] In addition, the heat dissipation element 26 is in the form of a heat sink, and its lower side contacts the bonding layer 25. It should be understood that there are many types of heat dissipation elements 26, and they are not limited to the above.

[0078] Therefore, the method for manufacturing the electronic package 2 of the present invention forms recesses 220, 420, 421 in the spacing structures 23, 43 between two adjacent electronic components 21 to serve as a high thermal resistance (e.g., air state) insulation area P, so that the electronic components 21 can be effectively insulated from each other to prevent the heat generated by the high-power (e.g., 2-watt) electronic component 21 from being transferred to the low-power (e.g., 0.3-watt) electronic component 21. The width D of the recess 220 is at least 50 microns (um), or even equal to the width of the spacing structures 23, 43, and the side surfaces 21c (e.g., 0.3-watt) of the electronic components 21 are exposed. Figure 3 The wall of the recess 320 shown is flush with the side surface 21 ), which optimizes the thermal insulation effect.

[0079] In addition, the thermal insulation area P can be in an air state (whose thermal resistance is relatively large) or can be filled with an insulating material (such as the bonding layer 25), and the thermal conductivity coefficient of the thermal insulation area P is smaller than the thermal conductivity coefficient of the packaging layers 22, 32. For example, the thermal conductivity coefficient of the thermal insulation area P is smaller than 0.02W / mK. Therefore, the electronic package 2 can effectively prevent the heat generated by the electronic components 21 (high-power components) such as the system-on-chip (SoC) from affecting the operation of the electronic components 21 (low-power components) such as the memory through the thermal insulation area P.

[0080] Furthermore, the electronic package 2 of the present invention can be of many types and is not limited to the above. For example, a wafer-level chip scale packaging (WLCSP) electronic package may embed the electronic components 21 in the packaging layer 22 and directly form the plurality of conductive elements 24 on the active surfaces 21a of the electronic components 21 to serve as external contacts for connection to an electronic device such as a circuit board (not shown), thereby omitting the fabrication of the carrier structure 20.

[0081] The present invention further provides an electronic package 2 , which includes a plurality of electronic components 21 and a packaging layer 22 , 32 covering the electronic components 21 .

[0082] The packaging layer 22 , 32 defines a spacing structure 23 , 43 located between at least two adjacent electronic components 21 of the plurality of electronic components 21 . A recess 220 , 320 , 420 , 421 is formed on the spacing structure 23 , 43 to serve as a heat insulation area P.

[0083] In one embodiment, the thermal insulation area P is in an air state, and may also be filled with an insulating material.

[0084] In one embodiment, the thermal conductivity of the thermal isolation region P is smaller than the thermal conductivity of the packaging layers 22 and 32 .

[0085] In one embodiment, the thermal conductivity of the thermal insulation region P is less than 0.02 W / mK.

[0086] In one embodiment, the width D of the recess 220 , 320 , 420 , 421 is at least 50 μm.

[0087] In one embodiment, the recess 220, 320 does not penetrate the spacer structure 23. For example, the thickness t of the encapsulation layer 22, 32 at the spacer structure 23 is at least 10 micrometers.

[0088] In one embodiment, the electronic package 2 further includes a supporting structure 20 for supporting and electrically connecting the plurality of electronic components 21. The supporting structure 20 has two opposing sides, such that the plurality of electronic components 21 are disposed on one of the two opposing sides of the supporting structure 20. A plurality of conductive elements 24 are disposed on the other of the two opposing sides of the supporting structure 20, such that the plurality of conductive elements 24 are electrically connected to the plurality of electronic components 21 via the supporting structure 20. In one embodiment, the recesses 420 and 421 extend to the supporting structure 20. Furthermore, the recess 421 penetrates the two opposing sides of the supporting structure 20.

[0089] In one embodiment, the electronic component 21 has an active surface 21 a and an inactive surface 21 b opposite to each other and a side surface 21 c adjacent to the active surface 21 a and the inactive surface 21 b , so that the spacing structures 23 , 43 connect the side surfaces 21 c of the electronic components 21 .

[0090] In one embodiment, the electronic package 2 further includes a heat sink 26 bonded to the plurality of electronic components 21, covering the recesses 220, 320, 420, 421. For example, the heat sink 26 is bonded to the plurality of electronic components 21 via a bonding layer 25. Furthermore, the bonding layer 25 fills the recesses 220, 320, 420, 421 but does not completely fill the recesses 220, 320, 420, 421.

[0091] In summary, the electronic package and its manufacturing method of the present invention, through the design of the thermal insulation area, can effectively insulate the electronic components to prevent the high-power electronic components from transferring the heat they generate to the low-power electronic components. Therefore, the present invention can effectively prevent the heat generated by the high-power electronic components from affecting the operation of the low-power electronic components, thereby improving the reliability of the electronic package.

[0092] The above embodiments are intended only to illustrate the principles and effects of the present invention and are not intended to limit the present invention. Any skilled artisan may modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be as set forth in the appended claims.

Claims

1. An electronic package, characterized in that: include: Multiple electronic components; a packaging layer covering the plurality of electronic components, wherein the packaging layer is defined as a spacing structure between at least two adjacent electronic components, and a recess is formed on the spacing structure to serve as a heat insulation area; and A supporting structure, supporting and electrically connecting the plurality of electronic components; The recess penetrates the supporting structure and does not separate the two side surfaces of the spacer structure which are opposite to the front side and the rear side.

2. The electronic package according to claim 1, wherein The insulation area is in an air state.

3. The electronic package according to claim 1, wherein: The heat-insulating area is filled with insulating material.

4. The electronic package according to claim 1, wherein: The thermal conductivity of the heat-insulating area is smaller than the thermal conductivity of the packaging layer.

5. The electronic package according to claim 1, wherein: The thermal conductivity of the insulation area is less than 0.02 W / mK.

6. The electronic package according to claim 1, wherein: The width of the recess is at least 50 microns.

7. The electronic package according to claim 1, wherein: The thickness of the packaging layer at the spacer structure is at least 10 micrometers.

8. The electronic package according to claim 1, wherein: The supporting structure has two opposite sides, so that the multiple electronic components are arranged on one of the two opposite sides of the supporting structure, and multiple conductive components are arranged on the other of the two opposite sides of the supporting structure.

9. The electronic package according to claim 1, wherein: The electronic component has an active surface and an inactive surface opposite to each other and side surfaces adjacent to the active surface and the inactive surface, so that the spacing structure connects the side surfaces of the plurality of electronic components.

10. The electronic package according to claim 9, wherein The recess exposes the side surface of the electronic component.

11. The electronic package according to claim 1, wherein: The electronic package also includes a heat sink coupled to the plurality of electronic components and covering the recess.

12. The electronic package according to claim 11, wherein: The heat sink is bonded to the plurality of electronic components via a bonding layer.

13. The electronic package according to claim 12, wherein: The bonding layer fills in the recess but does not completely fill the recess.

14. A method for manufacturing an electronic package, characterized in that: include: Providing a supporting structure to support and electrically connect multiple electronic components; Encapsulating the plurality of electronic components with a packaging layer, wherein the packaging layer is defined as a spacing structure between at least two adjacent electronic components; and forming a recess on the spacer structure so that the recess serves as a heat insulation area; The recess penetrates the supporting structure and does not separate the two side surfaces of the spacer structure which are opposite to the front side and the rear side.

15. The method for manufacturing an electronic package according to claim 14, wherein: The insulation area is in an air state.

16. The method for manufacturing an electronic package according to claim 14, wherein: The heat-insulating area is filled with insulating material.

17. The method for manufacturing an electronic package according to claim 14, wherein: The thermal conductivity of the heat-insulating area is smaller than the thermal conductivity of the packaging layer.

18. The method for manufacturing an electronic package according to claim 14, wherein: The thermal conductivity of the insulation area is less than 0.02 W / mK.

19. The method for manufacturing an electronic package according to claim 14, wherein: The width of the recess is at least 50 microns.

20. The method for manufacturing an electronic package according to claim 14, wherein: The thickness of the packaging layer at the spacer structure is at least 10 micrometers.

21. The method for manufacturing an electronic package according to claim 14, wherein: The supporting structure has two opposite sides, so that the multiple electronic components are arranged on one of the two opposite sides of the supporting structure, and multiple conductive components are arranged on the other of the two opposite sides of the supporting structure.

22. The method for manufacturing an electronic package according to claim 14, wherein: The electronic component has an active surface and an inactive surface opposite to each other and side surfaces adjacent to the active surface and the inactive surface, so that the spacing structure connects the side surfaces of the plurality of electronic components.

23. The method for manufacturing an electronic package according to claim 22, wherein: The recess exposes the side surface of the electronic component.

24. The method for manufacturing an electronic package according to claim 14, wherein: The manufacturing method further comprises arranging a heat dissipation member covering the concave portion on the plurality of electronic components.

25. The method for manufacturing an electronic package according to claim 24, wherein: The heat sink is bonded to the plurality of electronic components via a bonding layer.

26. The method for manufacturing an electronic package according to claim 25, wherein: The bonding layer fills in the recess but does not completely fill the recess.

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