Far infrared sensing element and manufacturing method and sensing dielectric layer thickness determination method

Abstract

A far-infrared sensing element and a manufacturing method and a method for determining the thickness of a sensing dielectric layer. The far-infrared sensing element is formed on a substrate, and comprises: a sensing area formed on the substrate, the sensing area is used to sense far-infrared signals; and a sensing dielectric layer formed on the sensing area, having a sensing dielectric layer thickness, and the sensing dielectric layer thickness is determined by a sacrificial metal layer.

Description

Technical Field

[0001] The present invention relates to a far infrared sensing element, and more particularly to a far infrared sensing element in which a sacrificial metal layer is used to determine the thickness of a dielectric layer of the far infrared sensing element. The present invention also relates to a manufacturing method of the far infrared sensing element and a method for determining the thickness of the dielectric layer. Background Art

[0002] Figure 1 A cross-sectional schematic diagram of a known far infrared sensing element is shown. The far infrared sensing element 10 is formed on a substrate 11 and has a sensing area 16. The sensing area 16 is formed on the substrate 11 and is used to sense a far infrared signal FIR. The far infrared sensing element 10 includes a dielectric layer 12, and the sensing area 16 is located in the dielectric layer 12. Specifically, the sensing area 16 has a stacking structure 161 and partition structures 162 and 163. From a top view (not shown), the partition structures 162 and 163 form a ring structure surrounding the stacking structure 161. The stacking structure 161 and the partition structures 162 and 163 each include a polysilicon layer poly1 and a polysilicon layer poly2.

[0003] When the conventional far infrared sensor element 10 is manufactured by CMOS process, a peripheral circuit 15 is usually formed on the substrate 11, wherein the peripheral circuit 15 includes at least one metal oxide semiconductor (MOS) element 17, a plurality of metal layers M1-M4 (four layers are shown in the example, but the number is not limited to four), and a plurality of conductive plugs V. The conductive plugs V electrically connect the plurality of metal layers M1-M4 and the MOS element 17. In addition, the aforementioned structures are insulated by a dielectric layer 12.

[0004] However, in the conventional far infrared sensor element 10, the thickness h0 of the dielectric layer 12 on the sensing region 16 cannot be easily adjusted due to the limitation of the CMOS process. This will make it impossible to accurately control and adjust the sensing performance and frame rate of the far infrared sensor element 10 when sensing the far infrared signal FIR.

[0005] In view of this, the present invention aims at addressing the above-mentioned deficiencies in the prior art and proposes an innovative far-infrared sensing element and a manufacturing method thereof and a method for determining the thickness of a dielectric layer thereof. Summary of the invention

[0006] In one aspect, the present invention provides a far infrared sensing element formed on a substrate. The far infrared sensing element comprises a sensing region and a sensing dielectric layer. The sensing region is formed on the substrate and is used to sense a far infrared signal. The sensing dielectric layer is formed on the sensing region and has a sensing dielectric layer thickness, wherein the sensing dielectric layer thickness is determined by a sacrificial metal layer.

[0007] In a preferred embodiment, the thickness of the sensing dielectric layer is determined by the following process steps. First, the sensing dielectric layer is formed on the sensing area, and the sensing dielectric layer has the sensing dielectric layer thickness. Then, the sacrificial metal layer is deposited on the sensing dielectric layer. Next, an interlayer dielectric layer is formed on the sacrificial metal layer. Then, the interlayer dielectric layer is etched by a first etching process step, wherein in the first etching process step, the etching speed of the interlayer dielectric layer is higher than the etching speed of the sacrificial metal layer, and the first etching process step uses the sacrificial metal layer as its etching stop layer. Then, the sacrificial metal layer is etched by a second etching process step.

[0008] From another perspective, the present invention provides a method for manufacturing a far-infrared sensing element, which includes the following steps. First, a sensing area is formed on a substrate, wherein the sensing area is used to sense a far-infrared signal. Thereafter, a sensing dielectric layer is formed on the sensing area, wherein the sensing dielectric layer has a sensing dielectric layer thickness. Next, a sacrificial metal layer is deposited on the sensing dielectric layer. Then, an interlayer dielectric layer is formed on the sacrificial metal layer. Then, the interlayer dielectric layer is etched using a first etching process step, wherein in the first etching process step, the etching speed of the interlayer dielectric layer is higher than the etching speed of the sacrificial metal layer, and the first etching process step uses the sacrificial metal layer as its etching stop layer. Finally, the sacrificial metal layer is etched using a second etching process step.

[0009] From another perspective, the present invention provides a method for determining the thickness of a sensing dielectric layer of a far-infrared sensing element, wherein the far-infrared sensing element is formed on a substrate. The far-infrared sensing element includes a sensing area and a sensing dielectric layer. The sensing area is used to sense a far-infrared signal. The sensing dielectric layer is formed on the sensing area and has a sensing dielectric layer thickness, wherein the method for determining the thickness of the sensing dielectric layer of the far-infrared sensing element includes the following steps. First, a sacrificial metal layer is deposited on the sensing dielectric layer. Thereafter, an interlayer dielectric layer is formed on the sacrificial metal layer. Next, the interlayer dielectric layer is etched using a first etching process step, wherein in the first etching process step, the speed of etching the interlayer dielectric layer is higher than the speed of etching the sacrificial metal layer, and the first etching process step uses the sacrificial metal layer as its etching stop layer. Finally, the sacrificial metal layer is etched using a second etching process step.

[0010] In a preferred embodiment, a peripheral circuit is additionally formed on the substrate, the peripheral circuit includes at least one metal oxide semiconductor element and a plurality of metal layers, and one of the plurality of metal layers and the sacrificial metal layer are formed by the same metal deposition process step.

[0011] In a preferred embodiment, the far infrared sensing element further includes a blocking layer formed on the sensing dielectric layer.

[0012] In a preferred embodiment, the thickness of the sensing dielectric layer is also determined by the following process steps: depositing the barrier layer between the sensing dielectric layer and the sacrificial metal layer; wherein in the second etching process step, the speed of etching the sacrificial metal layer is higher than the speed of etching the barrier layer, and the second etching process step uses the barrier layer as its etching stop layer.

[0013] In a preferred embodiment, the first etching process step is an anisotropic etching process, and the second etching step is an isotropic etching process.

[0014] In a preferred embodiment, the second etching process step is a wet etching process step, and the etching solution includes a tetramethylammonium hydroxide (TMAH) solution and / or a potassium hydroxide (KOH) solution.

[0015] In a preferred embodiment, the far infrared ray sensing element comprises a thermopile sensing element.

[0016] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, characteristics and effects of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A cross-sectional schematic diagram showing a conventional far infrared sensor element.

[0018] Figure 2 FIG. 4 is a cross-sectional schematic diagram showing a far infrared sensor element according to an embodiment of the present invention.

[0019] Figure 3 FIG. 4 is a cross-sectional schematic diagram showing a far infrared sensor element according to an embodiment of the present invention.

[0020] Figure 4A-4L FIG. 4 is a flow chart of a method for manufacturing a far infrared sensor element according to an embodiment of the present invention.

[0021] Figure 5 FIG. 4 is a cross-sectional schematic diagram showing a far infrared sensor element according to an embodiment of the present invention.

[0022] Explanation of symbols in the figure

[0023] 10, 20, 30: Far infrared sensor element

[0024] 11, 21, 31: substrate

[0025] 21A, 31A: Cavity

[0026] 21B: Insulation layer

[0027] 12, 22, 32: Dielectric layer

[0028] 22', 32': Sensing dielectric layer

[0029] 22”, 32”: Interlayer dielectric layer

[0030] 15, 25, 35: Peripheral circuit

[0031] 16, 26, 36: Sensing area

[0032] 17, 27, 37: MOS components

[0033] 161, 261, 361: stacked structure

[0034] 162, 163, 262, 263, 362, 363: partition structure

[0035] h0, h1, h2: sensing dielectric layer thickness

[0036] FIR: Far Infrared Signal

[0037] M1, M1', M2, M3, M4: metal layers

[0038] M2': Sacrificial metal layer

[0039] Poly1, Poly2: polysilicon layer

[0040] Sig: signal to be tested

[0041] V: Conductive plug DETAILED DESCRIPTION

[0042] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of the preferred embodiments with reference to the accompanying drawings. The drawings in the present invention are schematic, mainly intended to show the process steps and the up-down order relationship between the layers, and the shapes, thicknesses and widths are not drawn according to scale.

[0043] Figure 2 FIG. 1 is a cross-sectional schematic diagram showing a far infrared ray sensing element according to an embodiment of the present invention. Figure 2 As shown, the far infrared sensing element 20 of the present invention is formed on a substrate 21 and has a sensing area 26. The sensing area 26 is formed on the substrate 21 and is used to sense the far infrared signal FIR. The far infrared sensing element 20 includes a sensing dielectric layer 22' formed on the sensing area 26. The sensing dielectric layer 22' has a sensing dielectric layer thickness h1, and the sensing dielectric layer thickness h1 is determined by a sacrificial metal layer M2'. Specifically, the sensing area 26 has a stacking structure 261 and separation structures 262 and 263. From a top view (not shown), the separation structures 262 and 263 are, for example but not limited to, a ring structure surrounding the stacking structure 261. The stacking structure 261 and the separation structures 262 and 263 each include, for example but not limited to, a polysilicon layer poly1 and a polysilicon layer poly2.

[0044] When the far infrared sensing element 20 according to the present invention is manufactured by CMOS technology, a peripheral circuit 25 is additionally formed on the substrate 21, wherein the peripheral circuit 25 includes at least one metal oxide semiconductor element 27, multiple metal layers M1-M4 (four layers are shown in the example, but the number is not limited to four) and multiple layers of conductive plugs V. The conductive plugs V electrically connect the multiple metal layers M1-M4 and the MOS element 27. In addition, the aforementioned structures are insulated by a dielectric layer 22. The multiple metal layers M1-M4 include, for example but not limited to, metal layers of aluminum, copper, aluminum-copper alloy or other conductive materials. The conductive plugs V include, for example but not limited to, conductive plugs of tungsten, polysilicon, aluminum, copper, aluminum-copper alloy or other conductive materials. In a preferred embodiment, the dielectric layer 22 and the sensing dielectric layer 22' both include silicon dioxide layers.

[0045] In the present embodiment, the substrate 21 is, for example but not limited to, a silicon substrate. In a preferred embodiment, the substrate 21 has a cavity 21A, and the sensing area 26 is located on the cavity 21A of the substrate 21. The sensing area 26 can be used to sense far infrared signals. It should be noted that the infrared signal is an electromagnetic wave signal with a wavelength between microwaves and visible light. Generally speaking, the wavelength of infrared rays is between 0.7 μm and 1000 μm, and can be divided into near infrared rays, mid-infrared rays, far infrared rays and ultra-far infrared rays, which are well known to those skilled in the art and will not be described in detail here. In a preferred embodiment, the sensing area 26 is used to sense the far infrared signal FIR. In a preferred embodiment, the far infrared sensing element 20 further includes an insulating layer 21B, which is, for example but not limited to, a shallow trench isolation (STI) structure, and may also be a local oxidation of silicon (LOCOS) structure or a chemical vapor deposition (CVD) oxidation region, which is well known to those skilled in the art and will not be described in detail herein.

[0046] like Figure 2 As shown, the thickness h1 of the sensing dielectric layer of the present embodiment is determined by the sacrificial metal layer M2'. In a preferred embodiment, the sacrificial metal layer M2' and the metal layer M2 in a peripheral circuit 25 formed on the substrate 21 are formed by the same metal deposition process step. The peripheral circuit 25, for example, includes a metal oxide semiconductor element 27 and four metal layers M1-M4, and one of the metal layers M2 in the metal layers M1-M4 and the sacrificial metal layer M2' are formed by the same metal deposition process step.

[0047] In a preferred embodiment, the sensing dielectric layer thickness h1 is determined by the following process steps. First, a sensing dielectric layer 22' is formed on the sensing area 26, and the sensing dielectric layer 22' has a sensing dielectric layer thickness h1. Then, the sacrificial metal layer M2' is deposited on the sensing dielectric layer 22'. Next, an interlayer dielectric layer 22" is formed on the sacrificial metal layer M2' (described in detail later). Then, the interlayer dielectric layer 22" is etched using a first etching process step, wherein in the first etching process step, the etching speed of the interlayer dielectric layer 22" is higher than the etching speed of the sacrificial metal layer M2', and the first etching process step uses the sacrificial metal layer M2' as its etching stop layer. Next, the sacrificial metal layer M2' is etched using a second etching process step.

[0048] In a preferred embodiment, the first etching process step is an anisotropic etching process, and the second etching process step is an isotropic etching process. In a preferred embodiment, the second etching process step is a wet etching process step, and the etching solution includes tetramethylammonium hydroxide solution and / or potassium hydroxide solution.

[0049] Please continue reading Figure 2 Compared with the far-infrared sensing element 10 of the prior art, the sensing dielectric layer thickness h1 of the far-infrared sensing element 20 is adjustable. For example, a cavity is provided on the sensing dielectric layer 22' of the far-infrared sensing element 20, so that the far-infrared signal FIR to be sensed by the far-infrared sensing element 20 can reach the sensing area 26 through the relatively thin sensing dielectric layer 22'. Compared with the far-infrared sensing element 10 of the prior art, the present invention can improve the accuracy and stability of signal sensing, and improve the sensing performance and the screen refresh rate.

[0050] According to the present invention, the sacrificial metal layer M2' and the substrate 21 do not necessarily have to be formed by the same metal deposition process step as the metal layer M2 in the peripheral circuit 25. In a preferred embodiment, the sacrificial metal layer M2' can also be formed by the same metal deposition process step as the metal layer M1, M3 or M4 in the peripheral circuit 25 to adjust the thickness h1 of the sensing dielectric layer. In addition, the sacrificial metal layer M2' can also be a sacrificial metal layer M2' that is not formed by the same metal deposition process step as any of the metal layers M1 to M4 in the peripheral circuit 25, but is formed separately. In a preferred embodiment, the sacrificial metal layer M2' and one of the metal layers M1 to M4 in the peripheral circuit 25 are formed by the same metal deposition process step, which can reduce manufacturing costs.

[0051] In a preferred embodiment, the far infrared sensor element 20 includes a thermopile sensor element.

[0052] Figure 3 FIG. 1 is a cross-sectional schematic diagram showing a far infrared ray sensing element according to an embodiment of the present invention. Figure 3As shown, the far infrared sensing element 30 of the present invention is formed on a substrate 31 and has a sensing area 36. The sensing area 36 is formed on the substrate 31 and is used to sense the far infrared signal FIR. The far infrared sensing element 30 includes a sensing dielectric layer 32' formed on the sensing area 36. The sensing dielectric layer 32' has a sensing dielectric layer thickness h2, and the sensing dielectric layer thickness h2 is determined by a sacrificial metal layer M2'. Specifically, the sensing area 36 has a stacking structure 361 and separation structures 362 and 363. From a top view (not shown), the separation structures 362 and 363 form a ring structure surrounding the stacking structure 361. The stacking structure 361 and the separation structures 362 and 363 each include, for example but not limited to, a polysilicon layer poly1 and a polysilicon layer poly2.

[0053] When the far infrared sensing element 30 according to the present invention is manufactured by CMOS process, a peripheral circuit 35 is additionally formed on the substrate 31, wherein the peripheral circuit 35 includes at least one metal oxide semiconductor element 37, a plurality of metal layers M1-M4 (four layers are shown in the example, but the number is not limited to four), and a plurality of conductive plugs V. The conductive plugs V electrically connect the plurality of metal layers M1-M4 and the MOS element 37. In addition, the aforementioned structures are insulated by a dielectric layer 32.

[0054] This embodiment and Figure 2 The difference of the embodiment shown is that in this embodiment, the far infrared sensing element 30 further includes a blocking layer 38 formed on the sensing dielectric layer 32'. The blocking layer 38 includes, for example but not limited to, a silicon nitride layer, and the function of the blocking layer 38 will be described in detail later.

[0055] In a preferred embodiment, the sensing dielectric layer thickness h2 is determined by the following process steps. First, a sensing dielectric layer 32' is formed on the sensing area 36, ​​and the sensing dielectric layer 32' has a sensing dielectric layer thickness h2. Then, a barrier layer 38 is deposited on the sensing dielectric layer 32'. Next, a sacrificial metal layer M2' is deposited on the barrier layer 38. Then, an interlayer dielectric layer 32" is formed on the sacrificial metal layer M2' (described in detail later). Next, the interlayer dielectric layer 32" is etched using a first etching process step, wherein in the first etching process step, the etching speed of the interlayer dielectric layer 32" is higher than the etching speed of the sacrificial metal layer M2', and the first etching process step uses the sacrificial metal layer M2' as its etching stop layer. Next, the sacrificial metal layer M2' is etched using a second etching process step.

[0056] In the vertical direction, the barrier layer 38 is located between the sensing dielectric layer 32' and the sacrificial metal layer M2'. In the second etching process step, the etching speed of the sacrificial metal layer M2' is higher than the etching speed of the barrier layer 38, and the barrier layer 38 is used as the etching stop layer in the second etching process step.

[0057] Figure 4A-4L FIG. 1 is a flow chart showing a method for manufacturing a far infrared sensor element 30 according to an embodiment of the present invention. Figure 4A-4L The manufacturing method of the far infrared sensing element and the method for determining the thickness of the sensing dielectric layer according to the present invention can be described. Figure 4A As shown, a sensing region 36 and a MOS element 37 are first formed on a substrate 31. The sensing region 36 is used to sense a far infrared signal FIR. The sensing region 36 has a stacking structure 361 and separation structures 362 and 363. From a top view (not shown), the separation structures 362 and 363 form a ring structure surrounding the stacking structure 361. The stacking structure 361 and the separation structures 362 and 363 respectively include, for example but not limited to, a polysilicon layer poly1 and a polysilicon layer poly2.

[0058] Then, if Figure 4B As shown, a first dielectric layer 32a is formed, and a MOS device 37 and a sensing region 36 are buried in the first dielectric layer 32a, so that the MOS device 37 and the sensing region 36 are located in the first dielectric layer 32a. The first dielectric layer 32a is used to electrically isolate other electrical structures from the MOS device 37 and the sensing region 36.

[0059] Then, if Figure 4C As shown, a conductive plug V is formed in the first dielectric layer 32a. The conductive plug V is conductive and is used to electrically connect each metal layer and each electrical structure. In subsequent process steps, other conductive plugs V will be formed.

[0060] Then, if Figure 4D As shown, a metal layer M1 is formed on the first dielectric layer 32a. The metal layer M1 is connected to the first dielectric layer 32a and electrically connected to the conductive plug V.

[0061] Then, if Figure 4E As shown, a second dielectric layer 32b is formed on the first dielectric layer 32a, and the metal layer M1 is buried in the second dielectric layer 32b, so that the metal layer M1 is located in the second dielectric layer 32b. Figure 4E As shown, a blocking layer 38 is further formed on the second dielectric layer 32 b , and the blocking layer 38 is located directly above the sensing region 36 .

[0062] like Figure 4EAs shown, the first dielectric layer 32a and the second dielectric layer 32b directly above the sensing region 36 are used as the sensing dielectric layer 32'. The sensing dielectric layer 32' has a sensing dielectric layer thickness h2. The deposition barrier layer 38 is between the sensing dielectric layer 32' and the subsequently formed sacrificial metal layer M2'.

[0063] Then, if Figure 4F As shown, another conductive plug V is formed on the metal layer M1 and electrically connected to the metal layer M1.

[0064] Then, if Figure 4G As shown, the metal layer M2 and the sacrificial metal layer M2' are formed by the same metal deposition process step. The metal layer M2 is located in the peripheral circuit 35, on the second dielectric layer 32b, and directly above the metal layer M1; and the sacrificial metal layer M2' is located in the far infrared sensing element 30, directly above the sensing area 36, ​​and connected to the barrier layer 38. That is, the sacrificial metal layer M2' is deposited on the sensing dielectric layer 32'.

[0065] Then, if Figure 4H As shown, a third dielectric layer 32c, metal layers M3 and M4, and a metal plug V on the metal layer M2 are formed. The third dielectric layer 32c is formed on the second dielectric layer 32b, and the metal layers M3 and M4 and the conductive plug V on the metal layer M2 are buried in the third dielectric layer 32c, so that the metal layers M3 and M4 and the conductive plug V on the metal layer M2 are located in the third dielectric layer 32c. Figure 4H As shown, a portion of the third dielectric layer 32c is directly above the sacrificial metal layer M2′ and the sensing region 36 and is used as an interlayer dielectric layer 32″. The first dielectric layer 32a, the second dielectric layer 32b and the third dielectric layer 32c are collectively referred to as the dielectric layer 32.

[0066] Then, if Fig. 4I As shown, a photoresist layer 39 is formed on the third dielectric layer 32c to serve as a blocking layer in the first etching process step.

[0067] Then, if Figure 4J As shown, in the first etching process step, the interlayer dielectric layer 32' and a portion of the sensing dielectric layer 32' are etched. In the first etching process step, the speed of etching the interlayer dielectric layer 32' is higher than the speed of etching the sacrificial metal layer M2', and the first etching process step uses the sacrificial metal layer M2' as its etching stop layer. For example, the speed of etching the oxide layer (such as a silicon dioxide layer) and the nitride layer (such as a silicon nitride layer) in the first etching process step is much higher than the speed of etching the metal layer (the sacrificial metal layer M2' shown in the figure) and the semiconductor layer (the substrate 31 shown in the figure, such as a single crystal silicon layer), and in a preferred embodiment, the first etching process step is an anisotropic dry etching process, and therefore, it will etch into a layer such as Figure 4JGrooves as shown.

[0068] Then, if Figure 4K As shown, in the second etching process step, the sacrificial metal layer M2' is etched, and a portion of the substrate 31 is etched to form a cavity 31A in the substrate 31. In the second etching process step, the etching speed of the sacrificial metal layer M2 is higher than the etching speed of the stop layer 38, and the second etching process step uses the stop layer 38 as its etching stop layer. The second etching process step is a wet etching process step, such as an isotropic etching process, and its etching solution includes, for example, tetramethylammonium hydroxide solution and / or potassium hydroxide solution.

[0069] The peripheral circuit 35 formed on the substrate 31 includes at least one metal oxide semiconductor element 37 and a plurality of metal layers M1-M4, and one of the metal layers M1-M4, which is the metal layer M2 in this embodiment, is formed by the same metal deposition process as the sacrificial metal layer M2'.

[0070] The first etching process step is an anisotropic etching process, and the second etching step is an isotropic etching process.

[0071] Then, if Figure 4L As shown, for example, a silicon nitride layer 38' is formed on the dielectric layer 32, and a portion of the dielectric layer 32 is etched by an etching process to expose a portion of the metal pad of the top metal layer M4 that needs to be electrically connected to an external circuit.

[0072] Figure 5 FIG. 1 is a cross-sectional schematic diagram showing a far infrared ray sensing element according to an embodiment of the present invention. Figure 5 As shown, the far infrared sensing element 30 and the peripheral circuit 35 of this embodiment are formed on the substrate 31. In addition, in this embodiment, the stacking structure 261 and the separation structures 262 and 263 respectively include, for example but not limited to, a metal layer M1' and a polysilicon layer poly1 from top to bottom. In a preferred embodiment, the stacking structure 261 has at least two layers of heat conductive materials, and the Seebeck coefficients of the two layers of heat conductive materials are different from each other. The materials of the metal layer M1' and the polysilicon layer Poly1 are both heat conductive materials, but it is worth noting that the Seebeck coefficient of the metal layer M1 is different from the Seebeck coefficient of the polysilicon layer Poly1, and the temperature is sensed accordingly.

[0073] It should be noted that the far infrared sensing element 30 does not necessarily have to have a single stacking structure 261 . In another embodiment, the far infrared sensing element 30 may have two or more stacking structures 261 .

[0074] The bonding layer 33 is located on the dielectric layer 32. The filter layer 34 is connected to the dielectric layer 32 through the bonding layer 33. The filter layer 34 can help the far infrared sensing element 30 filter signals other than far infrared rays.

[0075] The filter layer 14 receives a signal to be tested Sig and only allows the far infrared signal FIR to pass through. In one embodiment, the thickness of the filter layer 34 may be, for example but not limited to, 5 to 15 μm. In one embodiment, the material of the filter layer 34 may be, for example but not limited to, polyethylene (PE), polypropylene / polypropene (PP) or polyethylene terephthalate (PET). In addition to filtering light, the filter layer 34 may also prevent dirt from entering the stacked structure 361.

[0076] The present invention has been described above with respect to the preferred embodiments, but the above is only to make it easy for those skilled in the art to understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, those skilled in the art can think of various equivalent changes. For example, other process steps or structures, such as a critical voltage adjustment area, etc., can be added without affecting the main characteristics of the component; for example, lithography technology is not limited to mask technology, but may also include electron beam lithography technology. All of these can be derived by analogy based on the teachings of the present invention. In addition, the various embodiments described are not limited to individual applications, but may also be used in combination, such as but not limited to the use of two embodiments together. Therefore, the scope of the present invention should cover the above and all other equivalent changes. In addition, any embodiment of the present invention does not necessarily achieve all purposes or advantages, and therefore, any of the claims should not be limited to this.

Claims

1. A far infrared sensor element, comprising: A sensing area formed on a substrate, the sensing area is used to sense a far infrared signal; and A sensing dielectric layer is formed on the sensing region and has a sensing dielectric layer thickness, and the sensing dielectric layer thickness is determined by a sacrificial metal layer; in, The thickness of the sensing dielectric layer is determined by the following process steps: forming the sensing dielectric layer on the sensing region, wherein the sensing dielectric layer has the sensing dielectric layer thickness; depositing the sacrificial metal layer on the sensing dielectric layer; forming an interlayer dielectric layer on the sacrificial metal layer; Etching the interlayer dielectric layer by a first etching process step, wherein in the first etching process step, the etching speed of the interlayer dielectric layer is higher than the etching speed of the sacrificial metal layer, and the first etching process step uses the sacrificial metal layer as an etching stop layer; as well as The sacrificial metal layer is etched by a second etching process step.

2. The far infrared sensor element according to claim 1, wherein: A peripheral circuit is additionally formed on the substrate. The peripheral circuit includes at least one metal oxide semiconductor element and a plurality of metal layers. One of the plurality of metal layers and the sacrificial metal layer are formed by the same metal deposition process step.

3. The far infrared sensor element according to claim 1, wherein: The invention also comprises a blocking layer formed on the sensing dielectric layer.

4. The far infrared ray sensing element according to claim 3, wherein: The thickness of the sensing dielectric layer is also determined by the following process steps: depositing the barrier layer between the sensing dielectric layer and the sacrificial metal layer; In the second etching process step, the etching speed of the sacrificial metal layer is higher than the etching speed of the barrier layer, and the second etching process step uses the barrier layer as its etching stop layer.

5. The far infrared ray sensing element according to claim 1, wherein: The first etching process step is an anisotropic etching process, and the second etching step is an isotropic etching process.

6. The far infrared ray sensing element according to claim 1, wherein: The second etching process step is a wet etching process step, and the etching solution includes tetramethylammonium hydroxide solution and / or potassium hydroxide solution.

7. The far infrared ray sensing element according to claim 1, wherein: The far infrared ray sensing element includes a thermopile sensing element.

8. A method for manufacturing a far infrared sensor element, comprising: forming a sensing area on a substrate, wherein the sensing area is used to sense a far infrared signal; forming a sensing dielectric layer on the sensing region, wherein the sensing dielectric layer has a sensing dielectric layer thickness; depositing a sacrificial metal layer on the sensing dielectric layer; forming an interlayer dielectric layer on the sacrificial metal layer; Etching the interlayer dielectric layer by a first etching process step, wherein in the first etching process step, the etching speed of the interlayer dielectric layer is higher than the etching speed of the sacrificial metal layer, and the first etching process step uses the sacrificial metal layer as an etching stop layer; The sacrificial metal layer is etched by a second etching process step.

9. The method for manufacturing a far-infrared sensor element according to claim 8, wherein: A peripheral circuit is additionally formed on the substrate. The peripheral circuit includes at least one metal oxide semiconductor element and a plurality of metal layers. One of the plurality of metal layers and the sacrificial metal layer are formed by the same metal deposition process step.

10. The method for manufacturing a far-infrared sensor element according to claim 8, wherein: Also includes: Depositing a barrier layer between the sensing dielectric layer and the sacrificial metal layer; In the second etching process step, the etching speed of the sacrificial metal layer is higher than the etching speed of the barrier layer, and the second etching process step uses the barrier layer as its etching stop layer.

11. The method for manufacturing a far infrared sensor element according to claim 8, wherein: The first etching process step is an anisotropic etching process, and the second etching step is an isotropic etching process.

12. The method for manufacturing a far infrared sensor element according to claim 8, wherein: The second etching process step is a wet etching process step, and the etching solution includes tetramethylammonium hydroxide solution and / or potassium hydroxide solution.

13. The method for manufacturing a far infrared sensor element according to claim 8, wherein: The far infrared ray sensing element includes a thermopile sensing element.

14. A method for determining the thickness of a sensing dielectric layer of a far infrared sensing element, wherein: The far infrared sensing element is formed on a substrate. The far infrared sensing element includes: a sensing area for sensing a far infrared signal; and a sensing dielectric layer formed on the sensing area and having a sensing dielectric layer thickness. The method for determining the sensing dielectric layer thickness of the far infrared sensing element includes: depositing a sacrificial metal layer on the sensing dielectric layer; forming an interlayer dielectric layer on the sacrificial metal layer; Etching the interlayer dielectric layer by a first etching process step, wherein in the first etching process step, the etching speed of the interlayer dielectric layer is higher than the etching speed of the sacrificial metal layer, and the first etching process step uses the sacrificial metal layer as an etching stop layer; The sacrificial metal layer is etched by a second etching process step.

15. The method for determining the thickness of the sensing dielectric layer of the far infrared sensing element as claimed in claim 14, wherein: A peripheral circuit is additionally formed on the substrate. The peripheral circuit includes at least one metal oxide semiconductor element and a plurality of metal layers. One of the plurality of metal layers and the sacrificial metal layer are formed by the same metal deposition process step.

16. The method for determining the thickness of the sensing dielectric layer of the far infrared sensing element as claimed in claim 14, wherein: Also includes: Depositing a barrier layer between the sensing dielectric layer and the sacrificial metal layer; In the second etching process step, the etching speed of the sacrificial metal layer is higher than the etching speed of the barrier layer, and the second etching process step uses the barrier layer as its etching stop layer.

17. The method for determining the thickness of the sensing dielectric layer of the far infrared sensing element as claimed in claim 14, wherein: The first etching process step is an anisotropic etching process, and the second etching step is an isotropic etching process.

18. The method for determining the thickness of the sensing dielectric layer of the far infrared sensing element as claimed in claim 14, wherein: The second etching process step is a wet etching process step, and the etching solution includes tetramethylammonium hydroxide solution and / or potassium hydroxide solution.

19. The method for determining the thickness of the sensing dielectric layer of the far infrared sensing element as claimed in claim 14, wherein: The far infrared ray sensing element includes a thermopile sensing element.

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