Trench silicon carbide transistor and method of manufacturing the same
By introducing gate trench and PN junction structures into silicon carbide metal-oxide-semiconductor field-effect transistors, the problem of temperature detection failure was solved, enabling accurate temperature detection and signal amplification.
Patent Information
- Application Number
- CN202211063707.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-08-31
- Publication Date
- 2025-12-12
- Estimated Expiration
- 2042-08-31
AI Technical Summary
Existing silicon carbide metal-oxide-semiconductor field-effect transistors cannot detect their own temperature.
A gate trench structure is introduced into a silicon carbide metal-oxide-semiconductor field-effect transistor, and a PN junction structure is set at its bottom. Temperature detection is achieved by utilizing the linear relationship between the forward voltage of the PN junction structure and the temperature.
Accurate temperature detection of the silicon carbide metal oxide semiconductor field-effect transistor was achieved, and the temperature detection signal was amplified by a high-resistance PN junction structure.
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Figure CN115394835B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the field of semiconductor devices, and particularly relates to a trench type silicon carbide transistor and a manufacturing method thereof. BACKGROUND
[0002] With the rapid development of power electronics, users have higher and higher requirements for silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs), so that silicon carbide metal-oxide-semiconductor field effect transistors have attracted more and more attention in the industry.
[0003] Silicon carbide metal-oxide-semiconductor field effect transistors have the advantages of high working frequency, low switching loss and large power density. However, the existing silicon carbide metal-oxide-semiconductor field effect transistors cannot detect the temperature of themselves. SUMMARY
[0004] The embodiments of the present application provide a trench type silicon carbide transistor and a manufacturing method thereof, which can realize temperature detection of silicon carbide metal-oxide-semiconductor field effect transistors.
[0005] In one aspect, the embodiments of the present application provide a trench type silicon carbide transistor, comprising:
[0006] A silicon carbide substrate of a first doping type, the silicon carbide substrate comprising a first surface, and a first doping type epitaxial layer disposed on the first surface;
[0007] A well region of a second doping type disposed in the epitaxial layer;
[0008] A gate trench structure disposed in the well region, the gate trench structure comprising a gate oxide layer covering a surface of the gate trench structure, and a gate and a PN junction structure located above the gate oxide layer at a bottom of the gate trench structure, the gate and the PN junction structure being insulated from each other;
[0009] A first doping region of the first doping type disposed on one side of the gate trench structure and in contact with the gate trench structure;
[0010] A second doping region of the second doping type disposed on the other side of the gate trench structure and spaced apart from the gate trench structure;
[0011] The first doping type is opposite to the second doping type.
[0012] In some embodiments, the length of the gate in a direction parallel to the silicon carbide substrate is equal to the length of the PN junction structure in the direction parallel to the silicon carbide substrate, and the length of the gate in a direction perpendicular to the silicon carbide substrate is equal to the length of the PN junction structure in the direction perpendicular to the silicon carbide substrate.
[0013] In some embodiments, the PN junction structure comprises:
[0014] The first structure and the second structure are disposed on the gate oxide layer at the bottom of the gate trench structure, and the contact surface between the first structure and the second structure is parallel to the first surface.
[0015] The doping type of the first structure is opposite to the doping type of the second structure.
[0016] In some embodiments, the PN junction structure comprises:
[0017] The first structure and the second structure are disposed on the gate oxide layer at the bottom of the gate trench structure, and the contact surface between the first structure and the second structure is perpendicular to the first surface.
[0018] The doping type of the first structure is opposite to the doping type of the second structure.
[0019] In some embodiments, the length of the first structure in a direction parallel to the silicon carbide substrate is equal to the length of the second structure in the direction parallel to the silicon carbide substrate, and the length of the first structure in a direction perpendicular to the silicon carbide substrate is equal to the length of the second structure in the direction perpendicular to the silicon carbide substrate.
[0020] In some embodiments, the projection of the well region in a direction perpendicular to the silicon carbide substrate does not overlap with the projection of the gate in the direction perpendicular to the silicon carbide substrate.
[0021] In some embodiments, the silicon carbide substrate further comprises a second surface opposite to the first surface, and the second surface is provided with a drain structure.
[0022] In a second aspect, the embodiments of the present application provide a trench type silicon carbide transistor manufacturing method, comprising:
[0023] A silicon carbide substrate of a first doping type is provided, and the silicon carbide substrate comprises a first surface, and the first surface is provided with an epitaxial layer of the first doping type;
[0024] A well region of a second doping type is formed on the surface of the epitaxial layer away from the first surface;
[0025] A first doping region of the first doping type and a second doping region of the second doping type are formed in the well region, and the first doping region and the second doping region are embedded in the well region.
[0026] forming a trench structure in the epitaxial layer;
[0027] forming a gate oxide layer on a surface of the trench structure;
[0028] forming a gate and a PN junction structure on the gate oxide layer at the bottom of the trench structure, the gate and the PN junction structure being insulated from each other.
[0029] In some optional embodiments, forming the gate and the PN junction structure on the gate oxide layer at the bottom of the trench structure comprises:
[0030] forming a gate and a third structure on the gate oxide layer at the bottom of the trench structure;
[0031] forming a first structure and a second structure within the third structure, a contact surface between the first structure and the second structure being parallel to the first surface;
[0032] a doping type of the first structure being opposite to a doping type of the second structure, and a doping type of the third structure being the same as the doping type of the first structure or the doping type of the second structure.
[0033] In some optional embodiments, forming the gate and the PN junction structure on the gate oxide layer at the bottom of the trench structure comprises:
[0034] forming a gate and a third structure on the gate oxide layer at the bottom of the trench structure;
[0035] forming a first structure and a second structure within the third structure, a contact surface between the first structure and the second structure being perpendicular to the first surface;
[0036] a doping type of the first structure being opposite to a doping type of the second structure, and a doping type of the third structure being the same as the doping type of the first structure or the doping type of the second structure.
[0037] The trench type silicon carbide transistor provided by the embodiment of the present application comprises a well region, a gate trench structure, a first doped region and a second doped region arranged in an epitaxial layer, wherein the gate trench structure comprises a gate oxide layer covering the surface of the gate trench structure, and a gate and a PN junction structure on the gate oxide layer at the bottom of the gate trench structure. By arranging the PN junction structure on the gate oxide layer at the bottom of the gate trench structure, the temperature detection of the silicon carbide metal oxide semiconductor field effect transistor itself can be realized by using the linear relationship between the forward voltage of the PN junction structure and the temperature under a certain current mode. In addition, on the one hand, since the PN junction structure is uniformly distributed in the silicon carbide metal oxide semiconductor field effect transistor, the accuracy of the temperature detection of the silicon carbide metal oxide semiconductor field effect transistor itself can be improved; on the other hand, since the resistance of the PN junction structure in the silicon carbide metal oxide semiconductor field effect transistor is large enough, the temperature detection signal can be amplified. BRIEF DESCRIPTION OF DRAWINGS
[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly introduced. Those skilled in the art can obtain other drawings according to these drawings without creating any creative labor.
[0039] Figure 1 is a structure schematic diagram of an embodiment of the trench type silicon carbide transistor provided by the present application;
[0040] Figure 2 is another structure schematic diagram of an embodiment of the trench type silicon carbide transistor provided by the present application;
[0041] Figure 3 is still another structure schematic diagram of an embodiment of the trench type silicon carbide transistor provided by the present application;
[0042] Figure 4 is a structure schematic diagram of the chip layout of the temperature detection diode in the trench type silicon carbide transistor provided by the present application;
[0043] Figure 5 is a flow schematic diagram of an embodiment of the trench type silicon carbide transistor manufacturing method provided by the present application;
[0044] Figure 6 is a cross-sectional structure schematic diagram of the silicon carbide substrate provided by the present application;
[0045] Figure 7 is a cross-sectional structure schematic diagram of the well region provided by the present application;
[0046] Figure 8is a schematic diagram of a cross-sectional structure of forming a first doped region and a second doped region provided by the present application;
[0047] Figure 9 is a schematic diagram of a cross-sectional structure of forming a trench structure provided by the present application;
[0048] Figure 10 is a schematic diagram of a cross-sectional structure of forming a gate oxide layer provided by the present application;
[0049] Figure 11 is a schematic diagram of a cross-sectional structure of forming a gate and a third structure provided by the present application;
[0050] Figure 12 is a schematic diagram of a cross-sectional structure of forming a gate and a PN junction structure provided by the present application;
[0051] Figure 13 is a schematic diagram of another cross-sectional structure of forming a gate and a PN junction structure provided by the present application;
[0052] Figure 14 is a schematic diagram of a cross-sectional structure of forming a drain structure provided by the present application.
[0053] Explanation of the elements in the drawings:
[0054] 1: silicon carbide substrate; 11: first surface; 12: second surface;
[0055] 2: epitaxial layer; 21: well region; 22: gate trench structure; 221: gate oxide layer; 222: gate; 223: PN junction structure; 2231: first structure; 2232: second structure; 23: first doped region; 24: second doped region; 25: interlayer dielectric; 26: TSD anode; 27: TSD cathode; 28: trench structure; 29: third structure;
[0056] 3: drain structure.
[0057] In the drawings, the same parts are designated by the same reference numerals. The drawings are not drawn to scale. DETAILED DESCRIPTION
[0058] The features and exemplary embodiments of various aspects of the present application will be described in detail below with reference to the drawings. The following description is made in connection with the preferred embodiments illustrated in the drawings, and is given to provide a better understanding of the present application. It should be understood that the present application is not limited to these preferred embodiments. The present application can be practiced without some of the specific details of these embodiments. The following description of the embodiments is merely provided to give a better understanding of the present application.
[0059] It is to be noted that, in the present document, relational terms such as first and second, and the like can be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.
[0060] To solve the problems in the prior art, the embodiments of the present application provide a trench type silicon carbide transistor and a manufacturing method thereof. First, the trench type silicon carbide transistor provided by the embodiments of the present application is introduced.
[0061] Figure 1 A structure schematic diagram of an embodiment of the trench type silicon carbide transistor provided by an embodiment of the present application is shown.
[0062] As shown in Figure 1 , the trench type silicon carbide transistor provided by the embodiments of the present application can include:
[0063] a silicon carbide substrate 1 of a first doping type, the silicon carbide substrate including a first surface 11, and a first doping type epitaxial layer 2 disposed on the first surface 11;
[0064] a well region 21 of a second doping type disposed in the epitaxial layer 2;
[0065] a gate trench structure 22 disposed in the well region 21, the gate trench structure 22 can include a gate oxide layer 221 covering a surface of the gate trench structure 22, and a gate 222 and a PN junction structure 223 located on the gate oxide layer 221 at a bottom of the gate trench structure 22, the gate 222 and the PN junction structure 223 being insulated from each other;
[0066] a first doping region 23 of the first doping type disposed on one side of the gate trench structure 22 and in contact with the gate trench structure 22;
[0067] a second doping region 24 of the second doping type disposed on another side of the gate trench structure 22 and spaced from the gate trench structure 22;
[0068] The first doping type is opposite to the second doping type.
[0069] The trench type silicon carbide transistor provided by the embodiment of the present application comprises a well region, a gate trench structure, a first doped region and a second doped region arranged in an epitaxial layer, wherein the gate trench structure comprises a gate oxide layer covering the surface of the gate trench structure, and a gate and a PN junction structure on the gate oxide layer at the bottom of the gate trench structure. By arranging the PN junction structure on the gate oxide layer at the bottom of the gate trench structure, the temperature detection of the silicon carbide metal oxide semiconductor field effect transistor itself can be realized by using the linear relationship between the forward voltage of the PN junction structure and the temperature under a certain current mode. In addition, on the one hand, since the PN junction structure is uniformly distributed in the silicon carbide metal oxide semiconductor field effect transistor, the accuracy of the temperature detection of the silicon carbide metal oxide semiconductor field effect transistor itself can be improved; on the other hand, since the resistance of the PN junction structure in the silicon carbide metal oxide semiconductor field effect transistor is large enough, the temperature detection signal can be amplified.
[0070] In the embodiment, the first doped type can be N type, and the second doped type can be P type. The silicon carbide substrate 1 of the first doped type can be an N type silicon carbide substrate; the epitaxial layer 2 of the first doped type can be an N type epitaxial layer; the well region 21 of the second doped type can be a P type well region; the first doped region 23 of the first doped type can be an N type first doped region; and the second doped region 24 of the second doped type can be a P type second doped region.
[0071] The epitaxial layer 2 can be at least one epitaxial layer. The epitaxial layer 2 can be formed of at least one semiconductor material such as silicon carbide. In the embodiment, the epitaxial layer 2 is taken as an example of a silicon carbide epitaxial layer. Silicon carbide has a wider band gap than silicon, and thus can maintain stability at high temperatures compared with silicon. In addition, since the breakdown field of silicon carbide is higher than that of silicon, silicon carbide can also be stably operated at high voltage compared with silicon.
[0072] Optionally, an interlayer dielectric 25 (ILD) is arranged between the gate 222 and the PN junction structure 223, so as to realize the mutual insulation between the gate and the PN junction structure. The composition material of the interlayer dielectric 25 can be the same as or different from that of the gate oxide layer 221, which is not limited herein.
[0073] Specifically, the gate 222 and the PN junction structure 223 are insulated from each other in the entire trench type silicon carbide transistor, the gate 222 functions as a trench, and when a positive voltage is applied to the gate trench structure 22, a reverse type electron layer, i.e., an electron layer of a first doping type, is formed in the well region 21 in contact with the gate 222. The PN junction formed by the well region 21 and the epitaxial layer 2 bears a voltage when a reverse voltage is applied to the source structure (not shown) and the drain structure (not shown). The PN junction structure 223 can be understood as a temperature sensitive diode (TSD) integrated in the trench type silicon carbide transistor.
[0074] In some alternative embodiments, the length of the gate 222 in the direction parallel to the silicon carbide substrate 1 can be equal to the length of the PN junction structure 223 in the direction parallel to the silicon carbide substrate 1, and the length of the gate 222 in the direction perpendicular to the silicon carbide substrate 1 can be equal to the length of the PN junction structure 223 in the direction perpendicular to the silicon carbide substrate 1. It can be understood that, in the alternative embodiments, the length of the gate 222 in the direction parallel to the silicon carbide substrate 1 can be different from the length of the PN junction structure 223 in the direction parallel to the silicon carbide substrate 1, and / or the length of the gate 222 in the direction perpendicular to the silicon carbide substrate 1 can be different from the length of the PN junction structure 223 in the direction perpendicular to the silicon carbide substrate 1. Figure 1 As shown in the cross-sectional structure diagram, the cross-sectional area of the gate 222 can be equal to the cross-sectional area of the PN junction structure 223.
[0075] In the present embodiment, the length of the gate in the direction parallel to the silicon carbide substrate is equal to the length of the PN junction structure in the direction parallel to the silicon carbide substrate, and the length of the gate in the direction perpendicular to the silicon carbide substrate is equal to the length of the PN junction structure in the direction perpendicular to the silicon carbide substrate, which can reduce the difficulty of the process.
[0076] In some alternative embodiments, the length of the gate 222 in the direction parallel to the silicon carbide substrate 1 can be equal to the length of the PN junction structure 223 in the direction parallel to the silicon carbide substrate 1, and the length of the gate 222 in the direction perpendicular to the silicon carbide substrate 1 can be equal to the length of the PN junction structure 223 in the direction perpendicular to the silicon carbide substrate 1. It can be understood that, in the alternative embodiments, the length of the gate 222 in the direction parallel to the silicon carbide substrate 1 can be different from the length of the PN junction structure 223 in the direction parallel to the silicon carbide substrate 1, and / or the length of the gate 222 in the direction perpendicular to the silicon carbide substrate 1 can be different from the length of the PN junction structure 223 in the direction perpendicular to the silicon carbide substrate 1.
[0077] As an example, the length of the gate 222 in the direction parallel to the silicon carbide substrate 1 can be greater than the length of the PN junction structure 223 in the direction parallel to the silicon carbide substrate 1, and / or the length of the gate 222 in the direction perpendicular to the silicon carbide substrate 1 can be greater than the length of the PN junction structure 223 in the direction perpendicular to the silicon carbide substrate 1.
[0078] As shown in the cross-sectional structure diagram, the cross-sectional area of the gate 222 can be equal to the cross-sectional area of the PN junction structure 223. Figure 2 As shown in some alternative embodiments, the PN junction structure 223 can include:
[0079] The first structure 2231 and the second structure 2232 are arranged on the gate oxide layer 221 at the bottom of the gate trench structure 22, and the contact surface between the first structure 2231 and the second structure 2232 is parallel to the first surface 11.
[0080] The doping type of the first structure 2231 is opposite to that of the second structure 2232.
[0081] In the embodiment, the doping type of the first structure 2231 is P type, the doping type of the second structure 2232 is N type, and the first structure 2231 is arranged on the side far from the bottom of the gate trench structure 22, and the second structure 2232 is arranged on the side close to the bottom of the gate trench structure 22. Correspondingly, the second structure 2232 can also be arranged on the side far from the bottom of the gate trench structure 22, and the first structure 2231 can also be arranged on the side close to the bottom of the gate trench structure 22.
[0082] Since the forward voltage of the PN junction structure 223 has a linear relationship with the temperature under a certain current mode, the temperature detection of the silicon carbide metal oxide semiconductor field effect transistor itself can be realized.
[0083] As shown in FIG. 2, in some alternative embodiments, the PN junction structure 223 can include: Figure 3 The first structure 2231 and the second structure 2232 are arranged on the gate oxide layer 221 at the bottom of the gate trench structure 22, and the contact surface between the first structure 2231 and the second structure 2232 is perpendicular to the first surface 11;
[0084] The doping type of the first structure 2231 is opposite to that of the second structure 2232.
[0085] In the embodiment, the doping type of the first structure 2231 is P type, the doping type of the second structure 2232 is N type, and the first structure 2231 is arranged on the side close to the gate 222, and the second structure 2232 is arranged on the side far from the gate 222. Correspondingly, the second structure 2232 can also be arranged on the side close to the gate 222, and the first structure 2231 can also be arranged on the side far from the gate 222.
[0086] Since the forward voltage of the PN junction structure 223 has a linear relationship with the temperature under a certain current mode, the temperature detection of the silicon carbide metal oxide semiconductor field effect transistor itself can be realized.
[0087] In some alternative embodiments, the length of the first structure 2231 in the direction parallel to the silicon carbide substrate 1 is equal to the length of the second structure 2232 in the direction parallel to the silicon carbide substrate 1, and the length of the first structure 2231 in the direction perpendicular to the silicon carbide substrate 1 is equal to the length of the second structure 2232 in the direction perpendicular to the silicon carbide substrate 1.
[0088] In some alternative embodiments, the length of the first structure 2231 in the direction parallel to the silicon carbide substrate 1 is equal to the length of the second structure 2232 in the direction parallel to the silicon carbide substrate 1, and the length of the first structure 2231 in the direction perpendicular to the silicon carbide substrate 1 is equal to the length of the second structure 2232 in the direction perpendicular to the silicon carbide substrate 1.
[0089] In the embodiment, the length of the first structure in the direction parallel to the silicon carbide substrate is equal to the length of the second structure in the direction parallel to the silicon carbide substrate, and the length of the first structure in the direction perpendicular to the silicon carbide substrate is equal to the length of the second structure in the direction perpendicular to the silicon carbide substrate, that is, the cross-sectional area of the first structure is equal to the cross-sectional area of the second structure, which can reduce the difficulty of process manufacturing.
[0090] In other optional embodiments, the length of the first structure 2231 in the direction parallel to the silicon carbide substrate 1 can be different from the length of the second structure 2232 in the direction parallel to the silicon carbide substrate 1, and / or the length of the first structure 2231 in the direction perpendicular to the silicon carbide substrate 1 can be different from the length of the second structure 2232 in the direction perpendicular to the silicon carbide substrate 1.
[0091] As an example, the length of the first structure 2231 in the direction parallel to the silicon carbide substrate 1 can be less than the length of the second structure 2232 in the direction parallel to the silicon carbide substrate 1, and / or the length of the first structure 2231 in the direction perpendicular to the silicon carbide substrate 1 can be less than the length of the second structure 2232 in the direction perpendicular to the silicon carbide substrate 1.
[0092] In some optional embodiments, the projection of the well region 21 in the direction perpendicular to the silicon carbide substrate 1 does not overlap with the projection of the gate 222 in the direction perpendicular to the silicon carbide substrate 1.
[0093] Still referring to Figure 3 The well region 21 can include a bottom well region 211 and a side well region 212. The bottom well region 211 is in contact with the bottom part of the gate trench structure 22, and the side well region 212 is in contact with the side part of the gate trench structure 22.
[0094] Specifically, the projection of the well region 21 in the direction perpendicular to the silicon carbide substrate 1 does not overlap with the projection of the gate 222 in the direction perpendicular to the silicon carbide substrate 1, which can be understood as that the distance between the bottom well region 211 and the gate 222 in the direction parallel to the silicon carbide substrate 1 is greater than or equal to 0.
[0095] It can be understood that, in the case that the projection of the well region 21 in the direction perpendicular to the silicon carbide substrate 1 overlaps with the projection of the gate 222 in the direction perpendicular to the silicon carbide substrate 1, the bottom well region 211 will also form an inversion electron layer, that is, an electron layer of the first doping type, when a positive voltage is applied to the gate trench structure 22. Therefore, in order to prevent the bottom well region 211 from forming an inversion electron layer when a positive voltage is applied to the gate trench structure 22, the projection of the well region 21 in the direction perpendicular to the silicon carbide substrate 1 does not overlap with the projection of the gate 222 in the direction perpendicular to the silicon carbide substrate 1.
[0096] In some optional embodiments, the silicon carbide substrate 1 can further include a second surface 12 opposite to the first surface 11, and the second surface 12 is provided with the drain structure 3.
[0097] Figure 4 A structure diagram of a chip layout of a temperature detection diode in a trench type silicon carbide transistor provided by the present application is shown. As shown in the figure, Figure 4 The temperature detection diode can include a TSD anode 26 and a TSD cathode 27, the doping type of the TSD cathode 27 can be N type, the doping type of the TSD anode 26 can be P type, and the doping type between the TSD cathode 27 and the TSD anode 26 can be P type.
[0098] It is worth noting that the first doping type in the embodiment is N type, and the second doping type is P type. However, in actual implementation, the silicon carbide substrate 1 is not limited to N type, but can also be P type. When the silicon carbide substrate 1 is P type, the conductivity type of the corresponding structures such as the epitaxial layer 2, the well region 21, the first doped region 23 and the second doped region 24 will also change accordingly.
[0099] Based on the trench type silicon carbide transistor provided in the above embodiment, the present application further provides a trench type silicon carbide transistor manufacturing method. The trench type silicon carbide transistor manufacturing method will be described below.
[0100] Figure 5 A flowchart of an embodiment of a trench type silicon carbide transistor manufacturing method provided by the present application is shown.
[0101] As shown in the figure, Figure 5 The trench type silicon carbide transistor manufacturing method can include S501 to S506. Please refer to Figures 6 to 14 , Figures 6 to 14 A series of process cross-sectional structure diagrams corresponding to the trench type silicon carbide transistor manufacturing method provided by the present application are shown.
[0102] S501, a silicon carbide substrate 1 of a first doping type is provided, and the silicon carbide substrate 1 includes a first surface 11, and the first surface 11 is provided with an epitaxial layer 2 of the first doping type.
[0103] In the embodiment, the silicon carbide substrate 1 of the first doping type is an N type silicon carbide substrate 1.
[0104] As shown in the figure, Figure 6 In some optional embodiments, an N type silicon carbide substrate 1 is first provided, and then epitaxy is performed on the silicon carbide substrate 1 to form an N type epitaxial layer 2.
[0105] S502, a well region 21 of a second doping type is formed on the surface of the epitaxial layer 2 away from the first surface 11.
[0106] In this embodiment, the second doped type well region 21 is a P-type well region.
[0107] like Figure 7 As shown, in some alternative embodiments, P-type ion doping is performed on the surface of the epitaxial layer 2 away from the first surface 11 to form a P-type well region 21.
[0108] S503, A first doped region 23 of the first doping type and a second doped region 24 of the second doping type are formed on the surface of the epitaxial layer 2 away from the first surface 11 and buried inside the well region 21.
[0109] In this embodiment, the first doped region 23 of the first doping type is an N-type first doped region, and the second doped region 24 of the second doping type is a P-type second doped region.
[0110] like Figure 8 As shown, in some optional embodiments, a first doped region 23 of a first doped type and a second doped region 24 of a second doped type are formed on the surface of the epitaxial layer 2 away from the first surface 11, buried inside the well region 21. This may include:
[0111] Ion doping of the first doping type is performed on the surface of the epitaxial layer 2 away from the first surface 11 to form a first doped region 23 buried inside the well region 21.
[0112] A second type of ion doping is performed on the surface of the epitaxial layer 2 away from the first surface 11 to form a second doped region 24 buried inside the well region 22.
[0113] As an example, forming a first doped region 23 of a first doped type and a second doped region 24 of a second doped type buried inside the well region 21 on the surface of the epitaxial layer 2 away from the first surface 11 can include:
[0114] N-type ion doping is performed on the surface of the epitaxial layer 2 away from the first surface 11 to form a first doped region 23 buried inside the well region 21.
[0115] P-type ion doping is performed on the surface of the epitaxial layer 2 away from the first surface 11 to form a second doped region 23 buried inside the well region 22.
[0116] S504. A trench structure 28 is formed in the epitaxial layer 2.
[0117] like Figure 9 As shown, in some optional embodiments, forming a trench structure 28 in the epitaxial layer 2 may include:
[0118] Trench etching is performed on the surface of the epitaxial layer 2 away from the first surface 11 to form a trench structure 29 in the epitaxial layer 2.
[0119] Optionally, a mask can be used to perform trench etching on the surface of the epitaxial layer 2 away from the first surface 11 to form a trench structure 28 in the epitaxial layer 2.
[0120] S505, A gate oxide layer 221 is formed on the surface of the trench structure 28.
[0121] like Figure 10 As shown, in some optional embodiments, forming a gate oxide layer 221 on the surface of the trench structure 28 may include:
[0122] Oxidation is performed on the surface of the trench structure 28 to form a gate oxide layer 221.
[0123] S506. A gate 222 and a PN junction structure 223 are formed on the gate oxide layer 221 at the bottom of the trench structure 28, and the gate 222 and the PN junction structure 223 are insulated from each other.
[0124] like Figure 11 and 12 As shown, in some optional embodiments, a gate 222 and a PN junction structure 223 are formed on the gate oxide layer 221 at the bottom of the trench structure 28, which may include:
[0125] A gate 222 and a third structure 29 are formed on the gate oxide layer 221 at the bottom of the trench structure 28;
[0126] A first structure 2231 and a second structure 2232 are formed within the third structure 29, and the contact surface between the first structure 2231 and the second structure 2232 is parallel to the first surface 11.
[0127] The doping type of the first structure 2231 is opposite to that of the second structure 2232, and the doping type of the third structure 29 is the same as that of the first structure 2231 or the second structure 2232.
[0128] In this embodiment, the doping type of the first structure 2231 is P-type, the doping type of the second structure 2232 is N-type, and the doping type of the third structure 29 is N-type.
[0129] In some alternative embodiments, a gate 222 and a third structure 29 are formed on the gate oxide layer 221 at the bottom of the trench structure 28, which may include:
[0130] A gate 222 is formed on the gate oxide layer 211 at the bottom of the trench structure 28;
[0131] An interlayer dielectric 25 is formed on the side of the gate 222 away from the first doped region 23;
[0132] A third structure 29 is formed on the side of the interlayer dielectric 25 away from the gate 222.
[0133] In some alternative embodiments, forming the first structure 2231 and the second structure 2232 within the third structure 29 may include:
[0134] A second structure 2232 is formed on one side near the bottom of the gate trench structure 22;
[0135] P-type heavy doping is performed on the other side away from the bottom of the gate trench structure 22 to form the first structure 2231;
[0136] Alternatively, P-type heavy doping can be performed on one side near the bottom of the gate trench structure 22 to form the first structure 2231;
[0137] A second structure 2232 is formed on the other side away from the bottom of the gate trench structure 22;
[0138] A gate oxide layer 211 is formed on a surface away from the first surface 11.
[0139] Since there is a linear relationship between the forward voltage and temperature of the PN junction structure 223 under a certain current mode, it is possible to realize the temperature detection of the silicon carbide metal oxide semiconductor field-effect transistor itself.
[0140] like Figure 11 and 13 As shown, in other embodiments, forming a gate 222 and a PN junction structure 223 on the gate oxide layer 221 at the bottom of the trench structure 28 may include:
[0141] A gate 222 and a third structure 29 are formed on the gate oxide layer 221 at the bottom of the trench structure 28;
[0142] A first structure 2231 and a second structure 2232 are formed within the third structure 29, and the contact surface between the first structure 2231 and the second structure 2232 is perpendicular to the first surface 11.
[0143] The doping type of the first structure 2231 is opposite to that of the second structure 2231, and the doping type of the third structure 29 is the same as that of the first structure 2231 or the second structure 2232.
[0144] In some alternative embodiments, a gate 222 and a third structure 29 are formed on the gate oxide layer 221 at the bottom of the trench structure 28, which may include:
[0145] A gate 222 is formed on the gate oxide layer 211 at the bottom of the trench structure 28;
[0146] An interlayer dielectric 25 is formed on the side of the gate 222 away from the first doped region 23;
[0147] A third structure 29 is formed on the side of the interlayer dielectric 25 away from the gate 222.
[0148] In some alternative embodiments, forming the first structure 2231 and the second structure 2232 within the third structure 29 may include:
[0149] P-type heavy doping is performed on the side near the gate 222 to form the first structure 2231;
[0150] A second structure 2232 is formed on the other side away from the gate 2223;
[0151] Alternatively, a second structure 2232 may be formed on the side near the gate 222;
[0152] P-type heavy doping is performed on the side away from the gate 2223 to form the first structure 2231;
[0153] A gate oxide layer 211 is formed on a surface away from the first surface 11.
[0154] Since there is a linear relationship between the forward voltage and temperature of the PN junction structure 223 under a certain current mode, it is possible to realize the temperature detection of the silicon carbide metal oxide semiconductor field-effect transistor itself.
[0155] Optionally, after forming the gate 222 and the PN junction structure 223 on the gate oxide layer 221 at the bottom of the trench structure 28, a gate insulating layer may also be formed; metal deposition; passivation treatment; back masking; and back metal formation, etc.
[0156] In some alternative embodiments, the length of the gate 222 in the direction parallel to the silicon carbide substrate 1 is equal to the length of the PN junction structure 2232 in the direction parallel to the silicon carbide substrate 1, and the length of the gate 222 in the direction perpendicular to the silicon carbide substrate 1 is equal to the length of the PN junction structure 223 in the direction perpendicular to the silicon carbide substrate 1.
[0157] In some alternative embodiments, the length of the first structure 2231 in the direction parallel to the silicon carbide substrate 1 is equal to the length of the second structure 2232 in the direction parallel to the silicon carbide substrate 1, and the length of the first structure 2231 in the direction perpendicular to the silicon carbide substrate 1 is equal to the length of the second structure 2232 in the direction perpendicular to the silicon carbide substrate 1.
[0158] In some alternative embodiments, the projection of the well region 21 in the direction perpendicular to the silicon carbide substrate 1 does not overlap with the projection of the gate 222 in the direction perpendicular to the silicon carbide substrate 1.
[0159] As Figure 14 shown, in some optional embodiments, the silicon carbide substrate 1 further comprises a second surface 12 opposite to the first surface 11, and the second surface 12 is provided with the drain structure 3.
[0160] It is worth noting that the present embodiment takes N-type as the first doping type and P-type as the second doping type as an example. However, in actual implementation, the silicon carbide substrate 1 is not limited to N-type, but can also be P-type. When the silicon carbide substrate 1 is P-type, the conductive type of the corresponding structures such as the epitaxial layer 2, the well region 21, the first doped region 23 and the second doped region 24 also changes accordingly.
[0161] As to the trench type silicon carbide transistor manufacturing method in the above embodiment, the structures and advantages have been described in detail in the embodiment about the trench type silicon carbide transistor, and will not be described in detail here.
[0162] The above is merely specific implementation of the present application, and those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the above-described system, module and unit can refer to the corresponding process in the foregoing method embodiments, which will not be described here. It should be understood that the protection scope of the present application is not limited to this, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application.
Claims
1. A trench silicon carbide transistor, characterized by, Comprising: a silicon carbide substrate of a first doping type, the silicon carbide substrate comprising a first surface, the first surface being provided with an epitaxial layer of the first doping type; a well region of a second doping type provided within the epitaxial layer; a gate trench structure provided within the well region, the gate trench structure comprising a gate oxide layer covering a surface of the gate trench structure, and a gate and a PN junction structure on the gate oxide layer at a bottom of the gate trench structure, the gate and the PN junction structure being insulated from each other; a first doped region of the first doping type provided at one side of the gate trench structure and in contact with the gate trench structure; a second doped region of the second doping type provided at another side of the gate trench structure and in contact with the gate trench structure; the first doping type being opposite to the second doping type; a length of the gate in a direction parallel to the silicon carbide substrate being equal to a length of the PN junction structure in the direction parallel to the silicon carbide substrate, and a length of the gate in a direction perpendicular to the silicon carbide substrate being equal to a length of the PN junction structure in the direction perpendicular to the silicon carbide substrate; the PN junction structure comprising: a first structure and a second structure provided on the gate oxide layer at the bottom of the gate trench structure, a contact surface between the first structure and the second structure being perpendicular to the first surface; a doping type of the first structure being opposite to a doping type of the second structure.
2. The trench silicon carbide transistor of Claim 1, wherein a length of the first structure in the direction parallel to the silicon carbide substrate being equal to a length of the second structure in the direction parallel to the silicon carbide substrate, and a length of the first structure in the direction perpendicular to the silicon carbide substrate being equal to a length of the second structure in the direction perpendicular to the silicon carbide substrate.
3. The trench silicon carbide transistor of Claim 1, wherein, a projection of the well region in the direction perpendicular to the silicon carbide substrate not overlapping with a projection of the gate in the direction perpendicular to the silicon carbide substrate.
4. The trench silicon carbide transistor of Claim 1, wherein, the silicon carbide substrate further comprising a second surface opposite to the first surface, the second surface being provided with a drain structure.
5. A method of manufacturing a trench silicon carbide transistor, characterized by, Comprising: providing a silicon carbide substrate of a first doping type, the silicon carbide substrate comprising a first surface, the first surface being provided with an epitaxial layer of the first doping type; forming a well region of a second doping type on a surface of the epitaxial layer away from the first surface; forming a first doped region of the first doping type and a second doped region of the second doping type embedded within the well region on the surface of the epitaxial layer away from the first surface; forming a trench structure in the epitaxial layer; forming a gate oxide layer on a surface of the trench structure; forming a gate and a PN junction structure on the gate oxide layer at a bottom of the trench structure, the gate and the PN junction structure being insulated from each other; the forming a gate and a PN junction structure on the gate oxide layer at the bottom of the trench structure, comprising: forming a gate and a third structure on the gate oxide layer at the bottom of the trench structure; forming a first structure and a second structure within the third structure, a contact surface between the first structure and the second structure being perpendicular to the first surface; The doping type of the first structure is opposite to the doping type of the second structure, and the doping type of the third structure is the same as the doping type of the first structure or the doping type of the second structure.
Citation Information
Patent Citations
A preparation method of a shielded gate power device
CN109037071A
Groove type silicon carbide transistor
CN218123412U