RRAM Bottom Electrode Structure, Manufacturing Method, Resistive Random Access Memory, and Electronic Device

Abstract

The present invention provides an RRAM lower electrode structure, a manufacturing method, a resistive random access memory (RRAM), and an electronic device, comprising a lower electrode through-hole, a lower electrode plate layer, and a passivation layer. The lower electrode through-hole is disposed within an insulating layer, and the bottom of the lower electrode through-hole is disposed on a metal wiring layer. A conductive material layer is disposed within the lower electrode through-hole. The top of the conductive material layer is in an arc shape. The lower electrode plate layer is disposed on top of the conductive material layer, and the end of the lower electrode plate layer is disposed on the insulating layer, so that the lower electrode plate layer has an arc-shaped dome shape. The passivation layer is disposed on top of the lower electrode plate layer. A passivation layer opening is disposed at the top of the passivation layer, and the dome of the lower electrode plate layer is exposed outside the passivation layer through the passivation layer opening. The present invention can solve the problem of unstable subsequent erasing and writing of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and more particularly to an RRAM lower electrode structure, a manufacturing method, a resistive random access memory, and an electronic device. Background Art

[0002] RRAM devices have a typical "sandwich" structure, with a (MIM) structure consisting of a resistive switching layer material capable of undergoing resistance transitions between the upper and lower electrodes. Under an applied bias, the device's resistance switches between high and low resistance states, enabling the storage of "0" and "1."

[0003] RRAM has a compact and simple structure, and its process is compatible with CMOS, so its common structure is integrated between metal wiring layers in the CMOS process. TE is the top electrode, SL is the resistive switching layer, BE is the bottom electrode, CF is the conductive filament, and Via is the through-hole connecting the RRAM to the underlying metal layer. Because the top and bottom plates and the resistive switching layer are parallel in this typical structure, when voltage is applied to the plates, the location of the conductive filaments is not fixed; multiple conductive filaments may be generated in multiple areas, resulting in instability in subsequent erase and write operations on the device. Summary of the Invention

[0004] In view of the above problems, the purpose of the present invention is to provide an RRAM lower electrode structure, manufacturing method, resistive random access memory and electronic device to solve the current problem that due to the parallel upper and lower plates and the resistive random access layer, when voltage is applied to the plates, the position of the conductive filaments generated is fixed, and multiple conductive filaments are generated in multiple areas, resulting in instability in the subsequent erasing and writing of the device.

[0005] The present invention provides an RRAM lower electrode structure, comprising a lower electrode through hole, a lower electrode plate layer and a passivation layer; wherein the lower electrode through hole is arranged in an insulating layer, and the bottom of the lower electrode through hole is arranged on a metal wiring layer; a conductive material layer is arranged in the lower electrode through hole; the top of the conductive material layer is in an arc shape; the lower electrode plate layer is arranged on top of the conductive material layer, and the end of the lower electrode plate layer is arranged on the insulating layer, so that the lower electrode plate layer has an arc-shaped dome shape; the passivation layer is arranged on the upper part of the lower electrode plate layer; and a passivation layer opening is provided on the top of the passivation layer, and the dome of the lower electrode plate layer is exposed to the outside of the passivation layer through the passivation layer opening.

[0006] In addition, a preferred solution is that the lower electrode layer is a lower electrode metal layer or a lower electrode metal nitride layer.

[0007] In addition, a preferred solution is that the material of the lower plate metal layer is W or Pt; and / or the material of the lower plate metal nitride layer is TiN or TaN.

[0008] In addition, a preferred solution is that the material of the passivation layer is any one of WNx, WOx, PtOx, TiO, and TaO.

[0009] In addition, a preferred solution is that the material of the metal connection layer is copper metal.

[0010] The present invention provides a method for manufacturing the RRAM bottom electrode structure as described above, comprising the following steps:

[0011] Processing a lower electrode through hole on the insulating layer by a through-hole grinding process so that the bottom end of the lower electrode through hole is connected to the top end of the metal wiring layer, and filling the lower electrode through hole with a conductive material to form a conductive material layer in the lower electrode through hole;

[0012] The top of the conductive material layer is made to protrude from the insulating layer by a thinning process of the insulating layer, and the protruding portion of the conductive material layer is formed into an arc shape by a wet or planar etching process, or the top of the conductive material layer is made lower than the insulating layer by a thinning process of the conductive material layer, and the top of the conductive material layer is formed into an arc shape by a grinding process or a wet etching process, thereby obtaining a conductive material layer with an arc-shaped top;

[0013] uniformly growing a lower electrode layer along the plane of the insulating layer and the arc-shaped top of the conductive material layer to obtain a lower electrode layer;

[0014] Performing a passivation treatment on the upper surface of the lower electrode layer to form a passivation layer on the upper surface of the lower electrode layer;

[0015] The passivation layer is opened by a planar etching process, a passivation layer opening is formed on the passivation layer, and the dome of the lower electrode layer is exposed outside the passivation layer through the passivation layer opening to obtain the lower electrode structure of the resistive random access memory.

[0016] In addition, a preferred solution is that the insulating layer thinning process is used to make the top of the conductive material layer protrude from the insulating layer, and a wet or planar etching process is used to form the protruding portion of the conductive material layer into an arc shape, and the conductive material layer with an arc-shaped top includes:

[0017] The top of the conductive material layer protrudes from the insulating layer by making the selection ratio of the polishing liquid to the insulating layer greater than the selection ratio of the polishing liquid to the conductive material layer or by making the etching speed of the insulating layer greater than the etching speed of the conductive material layer;

[0018] A wet or planar etching process is adopted, by etching the conductive material layer at a faster rate than the insulating layer, and the etching rate in the region with a large edge contact angle is faster than that in the region with a small middle contact angle, so that the protruding portion of the conductive material layer forms an arc shape, thereby obtaining a conductive material layer with an arc-shaped top.

[0019] In addition, a preferred solution is that the conductive material layer is thinned so that the top of the conductive material layer is lower than the insulating layer, and the top of the conductive material layer is formed into an arc shape by a grinding process or a wet etching process, and the conductive material layer with an arc-shaped top is obtained, which includes:

[0020] A top portion of the conductive material layer is lower than the insulating layer by a grinding process or a wet process having a greater selectivity ratio for the conductive material layer than a selectivity ratio for the insulating layer;

[0021] A grinding process or a wet etching process is adopted, by grinding or etching the conductive material layer at a higher speed than the insulating layer, so that the top of the conductive material layer forms an arc shape, thereby obtaining a conductive material layer with an arc-shaped top.

[0022] The resistive random access memory provided by the present invention comprises an upper electrode structure, a resistive random access layer and the RRAM lower electrode structure as described above; wherein,

[0023] The resistive layer is disposed between the upper electrode structure and the passivation layer, and the dome of the lower electrode layer contacts the bottom of the resistive layer.

[0024] The electronic device provided by the present invention includes the resistive random access memory as described above.

[0025] As can be seen from the above technical solutions, the RRAM lower electrode structure, manufacturing method, resistive random access memory, and electronic device provided by the present invention have an arc-shaped top of the conductive material layer, so that the lower electrode layer grown on the top of the conductive material layer and the insulating layer has an arc-shaped dome shape. Due to the dome structure and the uneven passivation layer and the dome of the lower electrode layer exposed outside the passivation layer, they can contact the bottom of the resistive random access layer, so that conductive filaments can only be generated in the upper part of the dome. Because of the presence of the passivation layer in other areas, the generation of conductive filaments is fundamentally restricted, thereby improving the stability of device performance.

[0026] In order to achieve the above and related purposes, one or more aspects of the present invention include the features that will be described in detail later. The following description and the accompanying drawings describe some exemplary aspects of the present invention in detail. However, these aspects indicate only some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to include all of these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] By referring to the following description in conjunction with the accompanying drawings, and with a more complete understanding of the present invention, other objects and results of the present invention will become more clear and easy to understand. In the accompanying drawings:

[0028] Figure 1 Schematic diagram of the structure of the RRAM bottom electrode according to an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of a manufacturing process of a RRAM bottom electrode structure according to an embodiment of the present invention;

[0030] Figure 3 A schematic diagram of a manufacturing process of a RRAM bottom electrode structure according to another embodiment of the present invention;

[0031] Figure 4 FIG. 4 is a flow chart of a method for manufacturing a RRAM bottom electrode structure according to an embodiment of the present invention.

[0032] In the accompanying drawings, 1-lower electrode through hole, 2-lower electrode layer, 3-passivation layer, 31-passivation layer opening, 4-insulating layer, 5-metal wiring layer, 6-conductive material layer, 7-resistive layer, 8-conductive wire, 9-upper electrode structure.

[0033] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0034] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. However, it will be apparent that these embodiments may be practiced without these specific details.

[0035] In response to the aforementioned problem that, because the upper and lower plates and the resistive switching layer are currently parallel, when voltage is applied to the plates, the positions of the conductive filaments generated are fixed, and multiple conductive filaments are generated in multiple areas, resulting in instability in the subsequent erasing and writing of the device, a RRAM lower electrode structure, manufacturing method, resistive switching memory and electronic device are proposed.

[0036] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] In order to illustrate the resistive random access memory and its manufacturing method and electronic device provided by the present invention Figure 1 shows the structure of the RRAM lower electrode structure according to an embodiment of the present invention; Figure 2 The following is a diagram showing a manufacturing process of a RRAM lower electrode structure according to an embodiment of the present invention; Figure 3 FIG2 shows a manufacturing process of an RRAM lower electrode structure according to another embodiment of the present invention; Figure 4The flowchart of the method for manufacturing the RRAM bottom electrode structure according to an embodiment of the present invention is shown.

[0038] like Figure 1 As shown, the RRAM lower electrode structure provided by the present invention includes a lower electrode through hole 1, a lower electrode plate layer 2 and a passivation layer 3; wherein, the lower electrode through hole 1 is arranged in the insulating layer 4, and the bottom of the lower electrode through hole 1 is arranged on the metal wiring layer 5; a conductive material layer 6 is arranged in the lower electrode through hole 1; the top of the conductive material layer 6 is in an arc shape; the lower electrode plate layer 2 is arranged on the top of the conductive material layer 6, and the end of the lower electrode plate layer 2 is arranged on the insulating layer 4, so that the lower electrode plate layer 2 is in the shape of an arc dome; the passivation layer 3 is arranged on the upper part of the lower electrode plate layer 2; and a passivation layer opening 31 is provided on the top of the passivation layer 3, and the dome of the lower electrode plate layer 2 is exposed to the outside of the passivation layer 3 through the passivation layer opening 31.

[0039] By making the top of the conductive material layer 6 into an arc shape, the lower electrode layer 2 grown on the top of the conductive material layer 6 and the insulating layer 4 is in the shape of an arc dome. Due to the dome structure and the uneven passivation layer 3 and the dome of the lower electrode layer 2 exposed outside the passivation layer 3 can contact the bottom of the resistive layer 7, the conductive filament 8 can only be generated in the upper part of the dome. Because of the presence of the passivation layer in other areas, the generation of the conductive filament 8 is fundamentally restricted, thereby improving the stability of the device performance.

[0040] As a preferred embodiment of the present invention, the lower plate layer 2 is a lower plate metal layer or a lower plate metal nitride layer.

[0041] As a preferred embodiment of the present invention, the material of the lower plate metal layer is W or Pt; and / or the material of the lower plate metal nitride layer is TiN or TaN.

[0042] As a preferred embodiment of the present invention, the material of the passivation layer 3 is any one of WNx, WOx, PtOx, TiO, and TaO.

[0043] As a preferred embodiment of the present invention, the metal wiring layer 5 is made of copper.

[0044] like Figures 2 to 4 As shown together, the method for manufacturing the RRAM bottom electrode structure provided by the present invention includes the following steps:

[0045] S1. Processing a lower electrode through-hole 1 on the insulating layer 4 by a through-hole grinding process so that the bottom end of the lower electrode through-hole 1 is connected to the top end of the metal wiring layer 5, and filling the lower electrode through-hole 1 with a conductive material to form a conductive material layer 6 in the lower electrode through-hole 1;

[0046] S2. The top of the conductive material layer 6 is made to protrude from the insulating layer 4 by a thinning process of the insulating layer, and the protruding portion of the conductive material layer 6 is formed into an arc shape by a wet or planar etching process. Alternatively, the top of the conductive material layer 6 is made lower than the insulating layer 4 by a thinning process of the conductive material layer, and the top of the conductive material layer 6 is formed into an arc shape by a grinding process or a wet etching process, thereby obtaining a conductive material layer 6 with an arc-shaped top.

[0047] S3, uniformly growing the lower electrode layer 2 along the plane of the insulating layer 4 and the arc-shaped top of the conductive material layer 6 to obtain the lower electrode layer 2;

[0048] S4, performing a passivation treatment on the upper surface of the lower electrode layer 2 to form a passivation layer 3 on the upper surface of the lower electrode layer 2;

[0049] S5. Open the passivation layer 3 by a planar etching process, form a passivation layer opening 31 on the passivation layer 3, and expose the dome of the lower electrode layer 2 outside the passivation layer 3 through the passivation layer opening 31 to obtain the lower electrode structure of the resistive random access memory.

[0050] In the manufacturing method of the RRAM lower electrode structure provided by the present invention, two main methods can be used in the process of processing the dome shape of the conductive material layer 6. One is to first thin the conductive material layer 6 and then make the surface of the conductive material layer 6 convex spherical, then grow the lower electrode layer 2 and the passivation layer 3, and then partially open the passivation layer 3 at the top of the arc to form it.

[0051] The other method is to first thin the conductive material layer 6 and make the surface convex into a spherical shape, then thin the insulating layer, grow the lower plate layer 2 and the passivation layer 3, and then partially open the passivation layer 3 at the top of the arc.

[0052] By controlling the planar etching process, the passivation layer 3 can be stripped from the upper portion of the dome while preserving the passivation layer in other areas. This creates a novel lower electrode structure: composed of a dome-shaped metal and a discontinuous metal passivation layer. Due to the presence of the passivation layer 3, which is also non-uniform, this novel lower electrode creates a strong barrier at the passivation layer 3, blocking the path formed by the conductive filament 8. Only the upper portion of the dome, where the passivation layer 3 is absent, can, together with the resistive switching layer 7 and the top plate layer 2, form the sole conductive path for the RRAM device.

[0053] like Figure 2 As shown, as a preferred embodiment of the present invention, the top of the conductive material layer 6 is made to protrude from the insulating layer 4 by an insulating layer thinning process, and a wet or planar etching process is used to form the protruding portion of the conductive material layer 6 into an arc shape. The conductive material layer 6 with an arc-shaped top includes:

[0054] The top of the conductive material layer 6 is made to protrude from the insulating layer 4 by making the selectivity of the polishing liquid to the insulating layer 4 greater than the selectivity of the polishing liquid to the conductive material layer 6 or by making the etching speed of the insulating layer 4 greater than the etching speed of the conductive material layer 6;

[0055] By adopting a wet or planar etching process, the etching speed of the conductive material layer 6 is greater than the etching speed of the insulating layer 4, and the etching speed in the area with a large edge contact angle is greater than that in the area with a small middle contact angle, so that the protruding part of the conductive material layer 6 is formed into an arc shape, and a conductive material layer 6 with an arc shape at the top is obtained.

[0056] After the normal through-hole grinding process, an additional insulating layer thinning process is added, which is achieved by relying on the selectivity of the grinding liquid to the insulating layer being greater than that of the conductive material layer 6, or by a planar etching process, which is achieved by relying on the etching rate of the insulating layer being greater than that of the conductive material layer 6; by a wet process or a planar etching process, which is achieved by relying on the etching rate of the conductive material layer 6 being greater than that of the insulating layer 4, and the etching rate in the area with a large edge contact angle is greater than that in the area with a small middle contact angle; the lower plate layer is grown, and the insulating layer 4 is formed along the plane and the insulating layer 4. The raised spherical through-holes are uniformly grown; the lower plate layer is passivated, primarily through surface oxidation and nitridation of the lower plate metal layer or the lower plate nitride metal layer; the passivation layer 3 is opened through a planar etching process. Since the etching rate is fastest in the raised dome region, the dome region is opened by controlling the etching rate while retaining part of the passivation layer 3 in other areas. This completes the novel lower electrode structure. Finally, through subsequent growth of the resistive switching layer and upper electrode, photolithography, and etching processes, the entire RRAM device is completed.

[0057] As a preferred embodiment of the present invention, the top of the conductive material layer is made lower than the insulating layer by thinning the conductive material layer, and the top of the conductive material layer is formed into an arc shape by a grinding process or a wet etching process. The conductive material layer with an arc-shaped top includes:

[0058] The top of the conductive material layer 6 is made lower than the insulating layer 4 by a grinding process or a wet process having a greater selectivity ratio for the conductive material layer 6 than for the insulating layer 4;

[0059] By adopting a grinding process or a wet etching process, the grinding or etching speed of the conductive material layer 6 is greater than the grinding or etching speed of the insulating layer 4, so that the top of the conductive material layer 6 is formed into an arc shape, thereby obtaining a conductive material layer 6 with an arc-shaped top.

[0060] After the normal through-hole grinding process, an additional conductive material layer 6 thinning process is added, relying on the grinding process or wet process to select the conductive material layer 6 more than the insulating layer 4 material to achieve this. The insulating layer is thinned by grinding or wet etching, relying on the grinding or etching speed of the conductive material layer 6 to be greater than the etching rate of the insulating layer. Because the conductive material layer 6 generally has a potential difference with the inner lining layer of the sidewall, a certain galvanic effect is caused, which easily forms a spherical structure. The lower electrode layer is grown, growing uniformly along the plane of the insulating layer 4 and the raised spherical through-hole; the lower electrode layer is passivated, and the passivation process is mainly completed by surface oxidation and nitridation of the lower electrode metal layer; the passivation layer 3 is opened by a planar etching process. Since the etching rate is fastest in the raised dome area, the dome area is opened by controlling a certain etching rate, while retaining part of the passivation layer 3 in other areas. In this way, the new lower electrode structure is completed. Finally, after the subsequent growth of the resistive layer and the upper electrode, photolithography and etching processes, the entire RRAM device can be completed.

[0061] The resistive random access memory provided by the present invention includes an upper electrode structure 9, a resistive random access layer 7 and the RRAM lower electrode structure as described above; wherein the resistive random access layer 7 is arranged between the upper electrode structure 9 and the passivation layer 3, and the dome of the lower electrode layer 2 contacts the bottom of the resistive random access layer 7.

[0062] The electronic device provided by the present invention includes the resistive random access memory as described above.

[0063] By making the top of the conductive material layer into an arc shape, the lower electrode layer grown on the top of the conductive material layer and the insulating layer has an arc-shaped dome shape. Due to the dome structure and the uneven passivation layer, the dome of the lower electrode layer exposed outside the passivation layer can contact the bottom of the resistive layer, so that conductive filaments can only be generated in the upper part of the dome. The presence of the passivation layer in other areas fundamentally limits the generation of conductive filaments, thereby improving the stability of device performance.

[0064] The RRAM bottom electrode structure, manufacturing method, resistive random access memory, and electronic device proposed in accordance with the present invention have been described above by way of example with reference to the accompanying drawings. However, those skilled in the art will appreciate that various modifications may be made to the RRAM bottom electrode structure, manufacturing method, resistive random access memory, and electronic device proposed in accordance with the present invention without departing from the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the contents of the appended claims.

Claims

1. A RRAM bottom electrode structure, characterized in that: It includes a lower electrode through hole, a lower electrode layer and a passivation layer; wherein, The lower electrode through hole is arranged in the insulating layer, and the bottom of the lower electrode through hole is arranged on the metal wiring layer; a conductive material layer is arranged in the lower electrode through hole; and the top of the conductive material layer is in an arc shape; The lower electrode layer is arranged on top of the conductive material layer, and the end of the lower electrode layer is arranged on the insulating layer, so that the lower electrode layer is in the shape of a circular arc dome; The passivation layer is arranged on the upper part of the lower electrode layer; and a passivation layer opening is arranged on the top of the passivation layer, and the passivation layer opening is located at the arc-shaped dome of the lower electrode layer; the dome of the lower electrode layer is exposed to the outside of the passivation layer through the passivation layer opening.

2. The RRAM bottom electrode structure according to claim 1, wherein: The lower plate layer is a lower plate metal layer or a lower plate metal nitride layer.

3. The RRAM bottom electrode structure according to claim 2, wherein: The material of the lower plate metal layer is W or Pt; and / or; The material of the metal nitride layer of the lower electrode plate is TiN or TaN.

4. The RRAM bottom electrode structure according to claim 1, wherein: The material of the passivation layer is any one of WNx, WOx, PtOx, TiO, and TaO.

5. The RRAM bottom electrode structure according to claim 1, wherein: The material of the metal connection layer is copper metal.

6. The method for manufacturing the RRAM bottom electrode structure according to any one of claims 1 to 5, wherein: The steps include: Processing a lower electrode through hole on the insulating layer by a through-hole grinding process so that the bottom end of the lower electrode through hole is connected to the top end of the metal wiring layer, and filling the lower electrode through hole with a conductive material to form a conductive material layer in the lower electrode through hole; The top of the conductive material layer is made to protrude from the insulating layer by a thinning process of the insulating layer, and the protruding portion of the conductive material layer is formed into an arc shape by a wet or planar etching process, or the top of the conductive material layer is made lower than the insulating layer by a thinning process of the conductive material layer, and the top of the conductive material layer is formed into an arc shape by a grinding process or a wet etching process, thereby obtaining a conductive material layer with an arc-shaped top; uniformly growing a lower electrode layer along the plane of the insulating layer and the arc-shaped top of the conductive material layer to obtain a lower electrode layer; Performing a passivation treatment on the upper surface of the lower electrode layer to form a passivation layer on the upper surface of the lower electrode layer; The passivation layer is opened by a planar etching process, a passivation layer opening is formed on the passivation layer, and the dome of the lower electrode layer is exposed outside the passivation layer through the passivation layer opening to obtain the lower electrode structure of the resistive random access memory.

7. The method for manufacturing the RRAM bottom electrode structure according to claim 6, wherein: The insulating layer thinning process is used to make the top of the conductive material layer protrude from the insulating layer, and a wet or planar etching process is used to form the protruding portion of the conductive material layer into an arc shape. The conductive material layer with an arc-shaped top includes: The top of the conductive material layer protrudes from the insulating layer by making the selection ratio of the polishing liquid to the insulating layer greater than the selection ratio of the polishing liquid to the conductive material layer or by making the etching speed of the insulating layer greater than the etching speed of the conductive material layer; A wet or planar etching process is adopted, by etching the conductive material layer at a faster rate than the insulating layer, and the etching rate in the region with a large edge contact angle is faster than that in the region with a small middle contact angle, so that the protruding portion of the conductive material layer forms an arc shape, thereby obtaining a conductive material layer with an arc-shaped top.

8. The method for manufacturing the RRAM bottom electrode structure according to claim 6, wherein: The method of thinning the conductive material layer so that the top of the conductive material layer is lower than the insulating layer and forming the top of the conductive material layer into an arc shape by a grinding process or a wet etching process to obtain the conductive material layer with an arc-shaped top includes: A top portion of the conductive material layer is lower than the insulating layer by a grinding process or a wet process having a greater selectivity ratio for the conductive material layer than a selectivity ratio for the insulating layer; A grinding process or a wet etching process is adopted, by grinding or etching the conductive material layer at a higher speed than the insulating layer, so that the top of the conductive material layer forms an arc shape, thereby obtaining a conductive material layer with an arc-shaped top.

9. A resistive random access memory, characterized in that: It comprises an upper electrode structure, a resistive switching layer and the RRAM lower electrode structure according to any one of claims 1 to 5; wherein, The resistive layer is disposed between the upper electrode structure and the passivation layer, and the dome of the lower electrode layer contacts the bottom of the resistive layer.

10. An electronic device, characterized in that: The electronic device includes the resistive memory according to claim 9.

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