A brushless DC motor control circuit and method with overcurrent protection

Abstract

The present invention relates to a brushless DC motor control circuit and method with overcurrent protection, which belongs to the field of brushless DC motor commutation technology, and solves the problems of large switch loss and motor loss in the existing motor commutation control circuit. It includes: a commutation control logic circuit, which is used to receive and process a direction control signal, a PWM signal, a position Hall signal output by a brushless DC motor, an overcurrent protection signal, and a signal after a position Hall signal and a direction control signal are subjected to a non-logical operation, and generate a commutation control logic signal adapted to the H‑ON_L‑PWM modulation mode; a drive circuit, which is used to amplify the commutation control logic signal and obtain a drive signal; a power main circuit, which is used to perform an H‑ON_L‑PWM modulation process based on the drive signal, output a motor input control signal, and use the input control signal to drive the brushless DC motor to work; and is also used to output an overcurrent signal when the brushless DC motor is detected to be overcurrent; an overcurrent protection circuit, which is controlled by the overcurrent signal and generates an overcurrent protection signal.

Description

Technical Field

[0001] The invention relates to the technical field of brushless DC motor commutation, and in particular to a brushless DC motor control circuit and method with overcurrent protection. Background Art

[0002] In the prior art, the brushless DC motor commutation control circuit is mainly implemented in the following ways: collecting the position Hall signal based on the position sensor, outputting the control signal based on the commutation control algorithm to control the bridge drive circuit to realize the motor commutation, and processing the commutation signal based on the bridge drive circuit and the processor chip, and outputting the signal to control the motor rotation. The advantages of this method are mature technology and simple control algorithm, but the disadvantage is that due to the need for processor chips and peripheral circuits, the circuit is complex, large in size, and high in cost, which is limited when used in low-cost applications;

[0003] In addition, if an overcurrent protection circuit is set in the commutation control circuit, the motor will be forced to brake when the motor overcurrent is detected. However, the drive circuit and processor chip are still processing the working state, resulting in large switching loss and motor loss.

[0004] Finally, the prior art lacks a brushless DC motor commutation control circuit for the H-ON_L-PWM modulation method, which limits the application scenarios of the brushless DC motor commutation control circuit. Summary of the invention

[0005] In view of the above analysis, the embodiments of the present invention aim to provide a brushless DC motor control circuit and method with overcurrent protection, so as to solve the problems of large switching loss and motor loss in the existing motor commutation control circuit, and lack of brushless DC motor commutation control circuit for H-ON_L-PWM modulation method.

[0006] On the one hand, the present invention discloses a brushless DC motor control circuit with overcurrent protection, comprising:

[0007] A commutation control logic circuit is used to receive and process a direction control signal, a PWM signal, a position Hall signal output by a brushless DC motor, an overcurrent protection signal, and a signal after a logical negation operation of the position Hall signal and the direction control signal, and generate a commutation control logic signal adapted to an H-ON_L-PWM modulation mode;

[0008] A driving circuit, used for amplifying the commutation control logic signal to obtain a driving signal;

[0009] A power main circuit, used to perform an H-ON_L-PWM modulation process based on the drive signal, output a motor input control signal, and drive the brushless DC motor to work using the input control signal; and also used to output an overcurrent signal when an overcurrent of the brushless DC motor is detected;

[0010] The overcurrent protection circuit is controlled by the overcurrent signal and generates the overcurrent protection signal.

[0011] On the basis of the above scheme, the present invention also makes the following improvements:

[0012] Furthermore, the corresponding relationship between the position Hall signals HA, HB, HC and the direction control signal DIR in the commutation control logic circuit and the commutation control logic signals S1-S6 is:

[0013] If HA, HB, HC, and DIR are "1011" or "0100", signal S1 is at a high level, signals S2, S3, S4, and S5 are at a low level, and signal S6 is a PWM signal;

[0014] If HA, HB, HC, and DIR are "1001" or "0110", signal S1 is at a high level, signals S3, S4, S5, and S6 are all at low levels, and signal S2 is a PWM signal;

[0015] If HA, HB, HC, and DIR are "1101" or "0010", signal S3 is at a high level, signals S1, S4, S5, and S6 are all at low levels, and signal S2 is a PWM signal;

[0016] If HA, HB, HC, and DIR are "0101" or "1010", signal S3 is at a high level, signals S1, S2, S5, and S6 are all at low levels, and signal S4 is a PWM signal;

[0017] If HA, HB, HC, and DIR are "0111" or "1000", signal S5 is at a high level, signals S1, S2, S3, and S6 are all at low levels, and signal S4 is a PWM signal;

[0018] If HA, HB, HC, and DIR are "0011" or "1100", signal S5 is at a high level, signals S1, S2, S3, and S4 are all at low levels, and signal S6 is a PWM signal;

[0019] When DIR is 1, the motor rotates forward, and when DIR is 0, the motor rotates reversely.

[0020] Further, the signals S1, S3, and S5 are respectively used to control the opening or closing of the power tubes VT1, VT3, and VT5 in the upper bridge arm of the power main circuit; the signals S2, S4, and S6 are respectively used to control the opening or closing of the power tubes VT4, VT6, and VT2 in the lower bridge arm of the power main circuit; in the power main circuit, VT1 and VT4 are on one bridge arm, VT3 and VT6 are on one bridge arm, and VT5 and VT2 are on one bridge arm.

[0021] Further, if the signal S1 is at a high level, the signals S2, S3, S4, and S5 are all at low levels, and the signal S6 is a PWM signal, then the input control signal UA of the A-phase brushless DC motor is DC+ / 2; the input control signal UB of the B-phase brushless DC motor is an alternating change between DC+ / 2 and 0; the input control signal UC of the C-phase brushless DC motor is a linear decrease from DC+ / 2 to -DC+ / 2; the alternating change between DC+ / 2 and 0 is: when the PWM signal is at a high level, it is 0, and when the PWM signal is at a low level, it is DC+ / 2;

[0022] If signal S1 is high, signals S3, S4, S5, and S6 are all low, and signal S2 is a PWM signal, then UA is DC+ / 2; UC is an alternating change between DC+ / 2 and 0; UB is a linear increase from -DC+ / 2 to DC+ / 2;

[0023] If signal S3 is at a high level, signals S1, S4, S5, and S6 are all at low levels, and signal S2 is a PWM signal, then UB is DC+ / 2, UC is an alternating change between DC+ / 2 and 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2;

[0024] If signal S3 is at a high level, signals S1, S2, S5, and S6 are all at low levels, and signal S4 is a PWM signal, then UB is DC+ / 2, UA is an alternating change between DC+ / 2 and 0, and UC is a linear increase from -DC+ / 2 to DC+ / 2;

[0025] If signal S5 is at a high level, signals S1, S2, S3, and S6 are all at low levels, and signal S4 is a PWM signal, then UC is DC+ / 2, UA is an alternating change between DC+ / 2 and 0, and UB is a linear decrease from DC+ / 2 to -DC+ / 2;

[0026] If signal S5 is at a high level, signals S1, S2, S3, and S4 are all at low levels, and signal S6 is a PWM signal, then UC is DC+ / 2, UB is an alternating change between DC+ / 2 and 0, and UA is a linear increase from -DC+ / 2 to DC+ / 2.

[0027] Further, when the overcurrent protection circuit receives the overcurrent signal output by the power main circuit, the overcurrent protection signal output by the overcurrent protection circuit is a low level; otherwise, the output overcurrent protection signal is a high level;

[0028] The overcurrent protection signal is input to the commutation control logic circuit. When the overcurrent protection signal is at a low level, the commutation control logic signals S2, S4 and S6 are pulled down.

[0029] Furthermore, the commutation control logic circuit includes: S1-S6 control logic modules, each of which is composed of an AND gate and an OR gate, and the signals of HA, HB, and HC after the logical negation operation are HA1, HB1, and HC1 respectively, and the signals of DIR after the logical negation operation are DIR1; the signal ST is an overcurrent protection signal; wherein:

[0030] The S1 control logic module includes AND gates 1-4 and OR gate 1; the two input ends of AND gate 1 receive signals HA and HB1 respectively, and the two input ends of AND gate 2 are connected to the output end of AND gate 1 and signal DIR respectively; the two input ends of AND gate 3 receive signals HA1 and HB respectively, and the two input ends of AND gate 4 are connected to the output end of AND gate 3 and signal DIR1 respectively; the two input ends of OR gate 1 are connected to the output ends of AND gate 2 and AND gate 4 respectively, and the output end of OR gate 1 outputs signal S1;

[0031] The S3 control logic module includes AND gates 5-8 and an OR gate 2; the two input ends of the AND gate 5 receive signals HB and HC1 respectively, and the two input ends of the AND gate 6 are connected to the output end of the AND gate 5 and the signal DIR respectively; the two input ends of the AND gate 7 receive signals HB1 and HC respectively, and the two input ends of the AND gate 8 are connected to the output end of the AND gate 7 and the signal DIR1 respectively; the two input ends of the OR gate 2 are connected to the output ends of the AND gate 6 and the AND gate 8 respectively, and the output end of the OR gate 2 outputs the signal S3;

[0032] The S5 control logic module includes AND gates 9-12 and an OR gate 3; the two input ends of the AND gate 9 receive signals HC and HA1 respectively, and the two input ends of the AND gate 10 are respectively connected to the output end of the AND gate 9 and the signal DIR; the two input ends of the AND gate 11 receive signals HC1 and HA respectively, and the two input ends of the AND gate 12 are respectively connected to the output end of the AND gate 11 and the signal DIR1; the two input ends of the OR gate 3 are respectively connected to the output ends of the AND gate 10 and the AND gate 12, and the output end of the OR gate 3 outputs a signal S5;

[0033] The S2 control logic module includes AND gates 13-19 and an OR gate 4; the two input ends of the AND gate 13 receive signals HC and HA1 respectively, and the two input ends of the AND gate 14 receive signals DIR1 and ST respectively; the two input ends of the AND gate 15 are connected to the output ends of the AND gates 13 and 14 respectively; the two input ends of the AND gate 16 receive signals HC1 and HA respectively, and the two input ends of the AND gate 17 receive signals DIR and ST respectively; the two input ends of the AND gate 18 are connected to the output ends of the AND gate 16 and the AND gate 17 respectively; the two input ends of the OR gate 4 are connected to the output ends of the AND gate 15 and the AND gate 18 respectively, the two input ends of the AND gate 19 are connected to the output end of the OR gate 4 and the PWM signal respectively, and the output end of the AND gate 19 outputs the signal S2;

[0034] The S4 control logic module includes AND gates 20-26 and an OR gate 5; the two input ends of the AND gate 20 receive signals HA and HB1 respectively, and the two input ends of the AND gate 21 receive signals DIR1 and ST respectively; the two input ends of the AND gate 22 are connected to the output ends of the AND gate 20 and the AND gate 21 respectively; the two input ends of the AND gate 23 receive signals HA1 and HB respectively, and the two input ends of the AND gate 24 receive signals DIR and ST respectively; the two input ends of the AND gate 25 are connected to the output ends of the AND gate 23 and the AND gate 24 respectively; the two input ends of the OR gate 5 are connected to the output ends of the AND gate 22 and the AND gate 25 respectively, the two input ends of the AND gate 26 are connected to the output end of the OR gate 5 and the PWM signal respectively, and the output end of the AND gate 26 outputs the signal S4;

[0035] The S6 control logic module includes AND gates 27-33 and OR gate 6; the two input ends of AND gate 27 receive signals HB and HC1 respectively, and the two input ends of AND gate 28 receive signals DIR1 and ST respectively; the two input ends of AND gate 29 are connected to the output ends of AND gate 27 and AND gate 28 respectively; the two input ends of AND gate 30 receive signals HB1 and HC respectively, and the two input ends of AND gate 31 receive signals DIR and ST respectively; the two input ends of AND gate 32 are connected to the output ends of AND gate 30 and AND gate 31 respectively; the two input ends of OR gate 6 are connected to the output ends of AND gate 29 and AND gate 32 respectively, the two input ends of AND gate 33 are connected to the output end of OR gate 6 and the PWM signal respectively, and the output end of AND gate 33 outputs signal S6.

[0036] Furthermore, the circuit also includes a logical NOT circuit for performing the NOT logic operation on the position Hall signal and the direction control signal output by the brushless DC motor.

[0037] On the other hand, the present invention also discloses a brushless DC motor control method with overcurrent protection, comprising the following steps:

[0038] Based on the direction control signal, the PWM signal, the position Hall signal output by the brushless DC motor, the overcurrent protection signal, and the signal after the position Hall signal and the direction control signal are subjected to a negation logic operation, a commutation control logic signal adapted to the H-ON_L-PWM modulation mode is generated;

[0039] amplifying the commutation control logic signal to obtain a driving signal;

[0040] Based on the driving signal, the power main circuit is driven to perform the H-ON_L-PWM modulation process, output the motor input control signal, and use the input control signal to drive the brushless DC motor to work;

[0041] When it is detected that the brushless DC motor is overcurrent, the main power circuit outputs an overcurrent signal and generates the overcurrent protection signal controlled by the overcurrent signal.

[0042] On the basis of the above scheme, the present invention also makes the following improvements:

[0043] Furthermore, the method further comprises:

[0044] When it is detected that the brushless DC motor is overcurrent, the commutation control logic signals S2, S4 and S6 are pulled down based on the overcurrent protection signal.

[0045] Furthermore, the driving signal is generated based on a driving circuit, wherein the driving circuit includes three IR2110 driving chips, and each IR2110 driving chip is used to drive the upper and lower power tubes of the same bridge arm in the power main circuit.

[0046] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0047] The brushless DC motor control circuit and method with overcurrent protection provided by the present invention can realize the commutation control of the brushless DC motor by adopting a commutation control logic circuit, and only one PWM signal and one square control signal are used. The commutation drive circuit is adapted to the H-ON_L-PWM modulation mode, and can realize the commutation control of the brushless DC motor when the power main circuit is the H-ON_L-PWM modulation mode. The circuit has the advantages of high reliability, small size, low cost, etc.

[0048] By setting an overcurrent protection circuit in the control circuit and controlling the commutation control logic circuit based on the overcurrent protection circuit, when the motor overcurrent is detected, the overcurrent protection circuit is used to control the output of the commutation control logic circuit, thereby realizing the control of the switch tube in the drive circuit and the power main circuit, which can effectively reduce or avoid switching loss and motor loss, and control the motor action at the same time. In addition, the automatic recovery of a single instantaneous overcurrent fault can be realized without manual operation by the user and without a dedicated controller chip, which simplifies the control logic and significantly improves the reliability of the brushless DC motor control circuit.

[0049] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0051] Figure 1 The brushless DC motor control circuit with overcurrent protection in Embodiment 1 of the present invention;

[0052] Figure 2 The logical NOT circuit in Embodiment 1 of the present invention;

[0053] Figure 3 The phase-change control logic circuit in Embodiment 1 of the present invention;

[0054] Figure 4 The driving circuit in Embodiment 1 of the present invention;

[0055] Figure 5 The main power circuit in Embodiment 1 of the present invention;

[0056] Figure 6 The overcurrent protection circuit in Embodiment 1 of the present invention;

[0057] Figure 7 This is a flow chart of a brushless DC motor control method with overcurrent protection in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0058] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0059] Example 1

[0060] A specific embodiment 1 of the present invention discloses a brushless DC motor control circuit with overcurrent protection, the structural diagram of which is shown in FIG. Figure 1 As shown, it includes: a commutation control logic circuit (adapted to the H-ON_L-PWM modulation mode), which is used to receive and process the direction control signal, the PWM signal, the position Hall signal output by the brushless DC motor, the overcurrent protection signal, and the signal after the position Hall signal and the direction control signal are subjected to a non-logical operation, and generate a commutation control logic signal adapted to the H-ON_L-PWM modulation mode; a drive circuit, which is used to amplify the commutation control logic signal to obtain a drive signal; a power main circuit (based on the H-ON_L-PWM modulation mode), which is used to perform the H-ON_L-PWM modulation process based on the drive signal, output a motor input control signal, and use the input control signal to drive the brushless DC motor to work; and is also used to output an overcurrent signal when the brushless DC motor is detected to be overcurrent; an overcurrent protection circuit, which is controlled by the overcurrent signal and generates the overcurrent protection signal.

[0061] Compared with the prior art, the brushless DC motor control circuit with overcurrent protection provided in this embodiment is designed in conjunction with the H-ON_L-PWM modulation method adopted by the power main circuit. The commutation control of the brushless DC motor can be achieved through only one PWM signal and one direction control signal. It has the advantages of simple circuit structure, high reliability, and small size. At the same time, the output of the commutation control logic circuit is controlled by the overcurrent protection circuit, which is beneficial to reducing switching loss and motor loss.

[0062] It should be noted that the direction control signal in this embodiment is used to indicate whether the brushless DC motor rotates forward or reversely. In this embodiment, when the motor is controlled to rotate forward, the direction control signal DIR is set to a high level; when the motor is controlled to rotate reversely, the direction control signal DIR is set to a low level; in addition, the PWM signal in this embodiment is used to adjust the speed of the brushless DC motor. Optionally, the frequency of the PWM signal can be set to 5k~20kz, and the duty cycle d of the PWM signal ranges from 0 to 1. The motor speed regulation can be achieved by changing the duty cycle of the PWM signal: the larger the duty cycle, the higher the corresponding motor speed; the smaller the duty cycle, the smaller the corresponding motor speed; a duty cycle of 1 corresponds to the highest adjustable speed, and a duty cycle of 0 corresponds to the lowest adjustable speed (i.e., 0 speed).

[0063] Exemplarily, the circuit also includes a logical NOT circuit, such as Figure 2 As shown, it is used to perform negation logic operations on the position Hall signal and the direction control signal respectively.

[0064] like Figure 1As shown, the position Hall signals output by the brushless DC motor include the A-phase position Hall signal HA, the B-phase position Hall signal HB, and the C-phase position Hall signal HC; the corresponding signals of the position Hall signals HA, HB, HC and the direction control signal DIR after the logical NOT circuit performs the NOT logic operation are represented as HA1, HB1, HC1, and DIR1 respectively; the commutation control logic circuit processes the signals HA, HB, HC, DIR, HA1, HB1, HC1, DIR1 and the PWM signal, and outputs the commutation logic signals S1-S6; among which, the signals S1, S3, S5 is the switching control logic signal for the power tubes VT1, VT3, and VT5 in the upper bridge arm of the power main circuit; signals S2, S4, and S6 are the switching control logic signals for the power tubes VT4, VT6, and VT2 in the lower bridge arm of the power main circuit; in the power main circuit, VT1 and VT4 are on the same bridge arm, and the connection point of VT1 and VT4 outputs signal UA; VT3 and VT6 are on the same bridge arm, and the connection point of VT3 and VT6 outputs signal UB; VT5 and VT2 are on the same bridge arm, and the connection point of VT5 and VT2 outputs signal UC. After being driven by the driving circuit, signals S1-S6 output driving signals G1-G6, wherein signal S1 drives the amplified output signal G1, signal S2 drives the amplified output signal G2, signal S3 drives the amplified output signal G3, signal S4 drives the amplified output signal G4, signal S5 drives the amplified output signal G5, and signal S6 drives the amplified output signal G6. The power main circuit adjusts the opening or closing of the power tubes VT1-VT6 according to the drive signals G1-G6, and outputs the brushless DC motor input control signals UA, UB, UC, and uses UA, UB, UC to control the rotation of the brushless DC motor. Specifically, the signals G4, G6, and G2 implement PWM chopping control, and the frequency and duty cycle are the same as the input PWM signal. The signals G1, G3, and G5 are in a constant on or constant off state, and no PWM chopping is performed. Therefore, the lower bridge arms VT4, VT6, and VT2 of the power main circuit are in a PWM chopping mode, and the upper bridge arms VT1, VT3, and VT5 are in a constant on or constant off state, and no PWM chopping is performed. Therefore, when the power main circuit control mode adopts H-ON_L-PWM, it is beneficial to reduce switching losses and motor losses.

[0065] When the motor rotates one circle, the position Hall signals HA, HB, and HC will have six states, namely "101", "100", "110", "010", "011", and "001". Assuming that the duty cycle of the PWM signal is d (the range of duty cycle d is 0 to 1), then when the PWM modulation mode is H-ON_L-PWM mode, the corresponding relationship between the position Hall signals HA, HB, HC and the direction control signal DIR in the commutation control logic circuit and the commutation control logic signals S1-S6 is:

[0066] When the motor rotates forward, DIR is 1; at this time,

[0067] If HA, HB, HC are "101" (that is, the states of HA, HB, HC are 1, 0, 1 respectively), after passing through the logic NOT circuit, the signals HA1, HB1, HC1 are "010", DIR1 is "0", after passing through the commutation circuit, S1 is high level, S2, S3, S4, S5 are all low level, S6 is a PWM signal with a duty cycle of d, after passing through the drive circuit, the waveform of G1 is high level, G2, G3, G4, G5 are all low level, G6 is a PWM signal with a duty cycle of d, when passing through the power main circuit, VT6 of the power main circuit is modulated by the G6 signal and is in an open and close alternating action (When G6 is 1, VT6 is turned on, and when G6 is 0, VT6 is turned off), VT2, VT3, VT4, and VT5 of the power main circuit are all turned off, and VT1 is turned on due to the high level of G1. At this time, the A-phase brushless DC motor input control signal UA of the power main circuit is DC+ / 2; the B-phase brushless DC motor input control signal UB is an alternating change between DC+ / 2 and 0; the C-phase brushless DC motor input control signal UC is a linear decrease from DC+ / 2 to -DC+ / 2; the alternating change between DC+ / 2 and 0 is: when the PWM signal takes a high level, it is 0, and when the PWM signal takes a low level, it is DC+ / 2;

[0068] If HA, HB, and HC are "100" (that is, the states of HA, HB, and HC are 1, 0, and 0, respectively), after passing through the logic NOT circuit, the signals HA1, HB1, and HC1 are "011", and DIR1 is "0". After passing through the commutation circuit, S1 is high, S3, S4, S5, and S6 are all low, and S2 is a PWM signal with a duty cycle of d. After passing through the drive circuit, G1 is high, G3, G4, G5, and G6 are all low, and G2 is a PWM signal with a duty cycle of d. When the PWM signal passes through the power main circuit, VT2 of the power main circuit is modulated by the G2 signal and is in an alternating on-off action (when G2 is 1, VT2 is on, and when G2 is 0, VT2 is off), VT3, VT4, VT5, and VT6 of the power main circuit are all off, and VT1 is turned on due to the high level of G1. At this time, UA of the power main circuit is DC+ / 2; UC is an alternating change between DC+ / 2 and 0; UB is a linear increase from -DC+ / 2 to DC+ / 2;

[0069] If HA, HB, and HC are "110" (that is, the states of HA, HB, and HC are 1, 1, and 0, respectively), after passing through the logic NOT circuit, the signals HA1, HB1, and HC1 are "001", and DIR1 is "0". After passing through the commutation circuit, S3 is high, S1, S4, S5, and S6 are all low, and S2 is a PWM signal with a duty cycle of d. After passing through the drive circuit, G3 is high, G1, G4, G5, and G6 are all low, and G2 is a PWM signal with a duty cycle of d. When the PWM signal passes through the power main circuit, VT2 of the power main circuit is modulated by the G2 signal and is in an alternating on-off action (when G2 is 1, VT2 is on, and when G2 is 0, VT2 is off), VT1, VT4, VT5, and VT6 of the power main circuit are all off, and VT3 is turned on due to the high level of G3. At this time, UB of the power main circuit is DC+ / 2, UC is an alternating change between DC+ / 2 and 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2;

[0070] If HA, HB, HC are "010" (that is, the states of HA, HB, HC are 0, 1, 0 respectively), after the logic NOT circuit, the signals HA1, HB1, HC1 are "101", DIR1 is "0", after the commutation circuit, S3 is high level, S1, S2, S5, S6 are all low level, S4 is a PWM signal with a duty cycle of d, after the drive circuit, G3 is high level, G1, G2, G5, G6 are all low level, G4 is a PWM signal with a duty cycle of d When the PWM signal passes through the power main circuit, VT4 of the power main circuit is modulated by the G4 signal and is in an alternating on-off action (when G4 is 1, VT4 is on, and when G4 is 0, VT4 is off), VT1, VT2, VT5, and VT6 of the power main circuit are all off, and VT3 is turned on due to the high level of G3. At this time, UB of the power main circuit is DC+ / 2, UA is an alternating change between DC+ / 2 and 0, and UC is a linear increase from -DC+ / 2 to DC+ / 2;

[0071] If HA, HB, and HC are "011" (that is, the states of HA, HB, and HC are 0, 1, and 1, respectively), after passing through the logic NOT circuit, the signals HA1, HB1, and HC1 are "100", and DIR1 is "0". After passing through the commutation circuit, S5 is high, S1, S2, S3, and S6 are all low, and S4 is a PWM signal with a duty cycle of d. After passing through the drive circuit, G5 is high, G1, G2, G3, and G6 are all low, and G4 is a PWM signal with a duty cycle of d. When the PWM signal passes through the power main circuit, VT4 of the power main circuit is modulated by the G4 signal and is in an alternating on-off action (when G4 is 1, VT4 is on, and when G4 is 0, VT4 is off), VT1, VT2, VT3, and VT6 of the power main circuit are all off, and VT5 is turned on due to the high level of G5. At this time, UC of the power main circuit is DC+ / 2, UA is an alternating change between DC+ / 2 and 0, and UB is a linear decrease from DC+ / 2 to -DC+ / 2;

[0072] If HA, HB, and HC are "001" (that is, the states of HA, HB, and HC are 0, 0, and 1, respectively), after the logic NOT circuit, the signals HA1, HB1, and HC1 are "110", and DIR1 is "0". After the commutation circuit, S5 is high, and S1, S2, S3, and S4 are all low. The waveform of S6 is a PWM signal with a duty cycle of d. After the drive circuit, G5 is high, and G1, G2, G3, and G4 are all low. The waveform of G6 is a duty cycle. When the PWM signal with a ratio of d passes through the power main circuit, VT6 of the power main circuit is modulated by the G6 signal and is in an alternating on-off action (when G6 is 1, VT6 is on, and when G6 is 0, VT6 is off), VT1, VT2, VT3, and VT4 of the power main circuit are all off, and VT5 is turned on due to the high level of G5. At this time, UC of the power main circuit is DC+ / 2, UB is an alternating change between DC+ / 2 and 0, and UA is a linear increase from -DC+ / 2 to DC+ / 2;

[0073] When the motor reverses, DIR is 0; at this time,

[0074] If HA, HB, HC are "010" (that is, the states of HA, HB, HC are 0, 1, 0 respectively), after passing through the logic NOT circuit, the signals HA1, HB1, HC1 are "101", DIR1 is "1", after passing through the commutation circuit, S1 is high level, S2, S3, S4, S5 are all low level, the waveform of S6 is a PWM signal with a duty cycle of d, after passing through the drive circuit, G1 is high level, G2, G3, G4, G5 are all low level, the waveform of G6 is a PWM signal with a duty cycle of d, when passing through the power main circuit, VT6 of the power main circuit is modulated by the G6 signal and In the on-off alternating action (when G6 is 1, VT6 is on, when G6 is 0, VT6 is off), VT2, VT3, VT4, and VT5 of the power main circuit are all off, and VT1 is on due to the high level of G1. At this time, the A-phase brushless DC motor input control signal UA of the power main circuit is DC+ / 2; the B-phase brushless DC motor input control signal UB is an alternating change between DC+ / 2 and 0, which is 0 when the PWM signal is high and DC+ / 2 when the PWM signal is low; the C-phase brushless DC motor input control signal UC is a linear decrease from DC+ / 2 to -DC+ / 2;

[0075] If HA, HB, and HC are "011" (that is, the states of HA, HB, and HC are 0, 1, and 1, respectively), after passing through the logic NOT circuit, the signals HA1, HB1, and HC1 are "100", and DIR1 is "1". After passing through the commutation circuit, S1 is high, S3, S4, S5, and S6 are all low, and S2 is a PWM signal with a duty cycle of d. After passing through the drive circuit, G1 is high, G3, G4, G5, and G6 are all low, and G2 is a PWM signal with a duty cycle of d. When the PWM signal passes through the power main circuit, VT2 of the power main circuit is modulated by the G2 signal and is in an alternating on-off action (when G2 is 1, VT2 is on, and when G2 is 0, VT2 is off), VT3, VT4, VT5, and VT6 of the power main circuit are all off, and VT1 is turned on due to the high level of G1. At this time, UA of the power main circuit is DC+ / 2; UC is an alternating change between DC+ / 2 and 0; UB is a linear increase from -DC+ / 2 to DC+ / 2;

[0076] If HA, HB, and HC are "001" (that is, the states of HA, HB, and HC are 0, 0, and 1, respectively), after passing through the logic NOT circuit, the signals HA1, HB1, and HC1 are "110", and DIR1 is "1". After passing through the commutation circuit, S3 is high, S1, S4, S5, and S6 are all low, and S2 is a PWM signal with a duty cycle of d. After passing through the drive circuit, G3 is high, G1, G4, G5, and G6 are all low, and G2 is a PWM signal with a duty cycle of d. When the PWM signal passes through the power main circuit, VT2 of the power main circuit is modulated by the G2 signal and is in an alternating on-off action (when G2 is 1, VT2 is on, and when G2 is 0, VT2 is off), VT1, VT4, VT5, and VT6 of the power main circuit are all off, and VT3 is turned on due to the high level of G3. At this time, UB of the power main circuit is DC+ / 2, UC is an alternating change between DC+ / 2 and 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2;

[0077] If HA, HB, and HC are "101" (that is, the states of HA, HB, and HC are 1, 0, and 1, respectively), after passing through the logic NOT circuit, the signals HA1, HB1, and HC1 are "010", and DIR1 is "1". After passing through the commutation circuit, S3 is high, S1, S2, S5, and S6 are all low, and S4 is a PWM signal with a duty cycle of d. After passing through the drive circuit, G3 is high, G1, G2, G5, and G6 are all low, and G4 is a PWM signal with a duty cycle of d. When the PWM signal passes through the power main circuit, VT4 of the power main circuit is modulated by the G4 signal and is in an alternating on-off action (when G4 is 1, VT4 is on, and when G4 is 0, VT4 is off), VT1, VT2, VT5, and VT6 of the power main circuit are all off, and VT3 is turned on due to the high level of G3. At this time, UB of the power main circuit is DC+ / 2, UA is an alternating change between DC+ / 2 and 0, and UC is a linear increase from -DC+ / 2 to DC+ / 2;

[0078] If HA, HB, and HC are "100" (that is, the states of HA, HB, and HC are 1, 0, and 0, respectively), after passing through the logic NOT circuit, the signals HA1, HB1, and HC1 are "011", and DIR1 is "1". After passing through the commutation circuit, S5 is high, S1, S2, S3, and S6 are all low, and S4 is a PWM signal with a duty cycle of d. After passing through the drive circuit, G5 is high, G1, G2, G3, and G6 are all low, and G4 is a PWM signal with a duty cycle of d. When the PWM signal passes through the power main circuit, VT4 of the power main circuit is modulated by the G4 signal and is in an alternating on-off action (when G4 is 1, VT4 is on, and when G4 is 0, VT4 is off), VT1, VT2, VT3, and VT6 of the power main circuit are all off, and VT5 is turned on due to the high level of G5. At this time, UC of the power main circuit is DC+ / 2, UA is an alternating change between DC+ / 2 and 0, and UB is a linear decrease from DC+ / 2 to -DC+ / 2;

[0079] If HA, HB, and HC are "110" (that is, the states of HA, HB, and HC are 1, 1, and 0, respectively), after passing through the logic NOT circuit, the signals HA1, HB1, and HC1 are "001", and DIR1 is "1". After passing through the commutation circuit, S5 is high, and S1, S2, S3, and S4 are all low. The waveform of S6 is a PWM signal with a duty cycle of d. After passing through the drive circuit, G5 is high, and G1, G2, G3, and G4 are all low. The waveform of G6 is a duty cycle. When the PWM signal with a ratio of d passes through the power main circuit, VT6 of the power main circuit is modulated by the G6 signal and is in an alternating on and off action (when G6 is 1, VT6 is turned on, and when G6 is 0, VT6 is turned off), VT1, VT2, VT3, and VT4 of the power main circuit are all turned off, and VT5 is turned on due to the high level of G5. At this time, UC of the power main circuit is DC+ / 2, UB is an alternating change between DC+ / 2 and 0, and UA is a linear increase from -DC+ / 2 to DC+ / 2.

[0080] Preferably, the commutation control logic circuit is as follows Figure 3As shown, it includes: S1-S6 control logic modules, each of which is composed of an AND gate and an OR gate, and the signals of HA, HB, and HC after the logical operation of negation are HA1, HB1, and HC1 respectively, and the signal of DIR after the logical operation of negation is DIR1; the signal ST is an overcurrent protection signal; wherein: the S1 control logic module includes AND gates 1-4 and OR gate 1; the two input ends of AND gate 1 receive signals HA and HB1 respectively, and the two input ends of AND gate 2 are respectively connected to the output end of AND gate 1 and the signal DIR; the two input ends of AND gate 3 receive signals HA1 and HB respectively, and the two input ends of AND gate 4 are respectively connected to the output end of AND gate 3 and the signal DIR1; the two input ends of OR gate 1 are respectively connected to the input ends of AND gate 2 and AND gate 4 The output end of the OR gate 1 outputs a signal S1; the S3 control logic module includes AND gates 5-8 and OR gate 2; the two input ends of the AND gate 5 receive signals HB and HC1 respectively, and the two input ends of the AND gate 6 are connected to the output end of the AND gate 5 and the signal DIR respectively; the two input ends of the AND gate 7 receive signals HB1 and HC respectively, and the two input ends of the AND gate 8 are connected to the output end of the AND gate 7 and the signal DIR1 respectively; the two input ends of the OR gate 2 are connected to the output ends of the AND gate 6 and the AND gate 8 respectively, and the output end of the OR gate 2 outputs a signal S3; the S5 control logic module includes AND gates 9-12 and OR gate 3; the two input ends of the AND gate 9 receive signals HC and HA1 respectively, and the two input ends of the AND gate 10 are connected to the output end of the AND gate 9 and the signal DIR respectively ; The two input ends of AND gate 11 receive signals HC1 and HA respectively, and the two input ends of AND gate 12 are connected to the output end of AND gate 11 and signal DIR1 respectively; the two input ends of OR gate 3 are connected to the output ends of AND gate 10 and AND gate 12 respectively, and the output end of OR gate 3 outputs signal S5; S2 control logic module includes AND gates 13-19 and OR gate 4; the two input ends of AND gate 13 receive signals HC and HA1 respectively, and the two input ends of AND gate 14 receive signals DIR1 and signal ST respectively; the two input ends of AND gate 15 are connected to the output ends of AND gate 13 and AND gate 14 respectively; the two input ends of AND gate 16 receive signals HC1 and HA respectively, and the two input ends of AND gate 17 receive signals DIR and overcurrent protection signal ST respectively ; The two input ends of AND gate 18 are respectively connected to the output ends of AND gate 16 and AND gate 17; The two input ends of OR gate 4 are respectively connected to the output ends of AND gate 15 and AND gate 18, The two input ends of AND gate 19 are respectively connected to the output end of OR gate 4 and the PWM signal, and the output end of AND gate 19 outputs signal S2; S4 control logic module includes AND gates 20-26 and OR gate 5; The two input ends of AND gate 20 receive signals HA and HB1 respectively, and the two input ends of AND gate 21 receive signals DIR1 and ST respectively; The two input ends of AND gate 22 are respectively connected to the output ends of AND gate 20 and AND gate 21; The two input ends of AND gate 23 receive signals HA1 and HB respectively, and the two input ends of AND gate 24 receive signals DIR and ST respectively;The two input ends of AND gate 25 are respectively connected to the output ends of AND gate 23 and AND gate 24; the two input ends of OR gate 5 are respectively connected to the output ends of AND gate 22 and AND gate 25; the two input ends of AND gate 26 are respectively connected to the output end of OR gate 5 and the PWM signal; the output end of AND gate 26 outputs signal S4; S6 control logic module includes AND gates 27-33 and OR gate 6; the two input ends of AND gate 27 receive signals HB and HC1 respectively, the two input ends of AND gate 28 receive signals DIR1 and ST respectively; the two input ends of AND gate 29 are respectively connected to the output ends of AND gate 27 and AND gate 28; the two input ends of AND gate 30 receive signals HB1 and HC respectively, the two input ends of AND gate 31 receive signals DIR and ST respectively; the two input ends of AND gate 32 are respectively connected to the output ends of AND gate 30 and AND gate 31; the two input ends of OR gate 6 are respectively connected to the output ends of AND gate 29 and AND gate 32; the two input ends of AND gate 33 are respectively connected to the output end of OR gate 6 and the PWM signal; the output end of AND gate 33 outputs signal S6. ;

[0081] Drive circuit such as Figure 4 As shown, it includes three IR2110 driver chips, each of which is used to drive the upper and lower power tubes of the same bridge arm in the power main circuit; after power-on, the SD pin of each IR2110 driver chip is connected to a low level. Figure 5 shown.

[0082] Overcurrent protection circuit such as Figure 6 As shown, when the overcurrent protection circuit receives the overcurrent signal output by the power main circuit, the overcurrent protection signal output by the overcurrent protection circuit is low level; otherwise, the output overcurrent protection signal is high level; the overcurrent protection signal is input to the commutation control logic circuit, and when the overcurrent protection signal is low level, the commutation control logic signals S2, S4 and S6 are pulled down. During the operation of the brushless DC motor control circuit with overcurrent protection, the overcurrent protection circuit receives the overcurrent signal OV output by the power main circuit, and after the above judgment, the overcurrent protection circuit outputs the overcurrent protection signal ST, and inputs the signal ST to the commutation control logic circuit to control the output of the commutation control logic signals S2, S4 and S6.

[0083] In the above-mentioned brushless DC motor control circuit with overcurrent protection, if an instantaneous overcurrent occurs during the operation of the motor, the output signal ST of the overcurrent protection circuit will be low level, and the signal ST passes through the commutation control logic circuit to pull down the drive signals S4, S6, and S2 at the same time, thereby pulling down the lower bridge arm drive signals G4, G6, and G2 of the power main circuit, blocking the lower bridge arm to ensure the safety of the power main circuit. After the lower bridge arm is blocked, the current of the power main circuit will decrease, and the output signal ST of the overcurrent protection circuit will gradually become high level. ST passes through the commutation control logic circuit to release the drive signals S4, S6, and S2 from the forced low state at the same time, thereby restoring the lower bridge arm drive signals G4, G6, and G2 of the power main circuit to normal. At this point, the power main circuit completes an overcurrent protection and recovery.

[0084] Example 2

[0085] Embodiment 2 of the present invention discloses a brushless DC motor control method with overcurrent protection, the flow chart is as follows: Figure 7 As shown, the following steps are included:

[0086] Step S1: Based on the direction control signal, the PWM signal, the position Hall signal output by the brushless DC motor, the overcurrent protection signal, and the signal after the position Hall signal and the direction control signal are subjected to a negation logic operation, a commutation control logic signal adapted to the H-ON_L-PWM modulation mode is generated;

[0087] Step S2: amplifying the commutation control logic signal to obtain a driving signal;

[0088] Step S3: Based on the driving signal, the power main circuit is driven to perform the H-ON_L-PWM modulation process, outputting the motor input control signal, and using the input control signal to drive the brushless DC motor to work;

[0089] When it is detected that the brushless DC motor is overcurrent, the main power circuit outputs an overcurrent signal and generates the overcurrent protection signal controlled by the overcurrent signal.

[0090] Preferably, when an overcurrent of the brushless DC motor is detected, the commutation control logic signals S2, S4 and S6 are pulled low based on the overcurrent protection signal.

[0091] The specific implementation process of the embodiment of the present invention may refer to the above-mentioned circuit embodiment. For example, a phase-changing control logic signal is generated based on a phase-changing control logic circuit, the drive signal is generated based on a drive circuit, and an overcurrent protection signal is generated based on an overcurrent protection circuit. This embodiment will not be repeated here.

[0092] Since the principle of this embodiment is the same as that of the above circuit embodiment, the method also has the corresponding technical effects of the above circuit embodiment.

[0093] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0094] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A brushless DC motor control circuit with overcurrent protection, characterized in that: include: A commutation control logic circuit is used to receive and process a direction control signal, a PWM signal, a position Hall signal output by a brushless DC motor, an overcurrent protection signal, and a signal after a logical negation operation of the position Hall signal and the direction control signal, and generate a commutation control logic signal adapted to an H-ON_L-PWM modulation mode; A driving circuit, used for amplifying the commutation control logic signal to obtain a driving signal; A power main circuit, used to perform an H-ON_L-PWM modulation process based on the drive signal, output a motor input control signal, and drive the brushless DC motor to work using the input control signal; It is also used to output an overcurrent signal when it is detected that the brushless DC motor has an overcurrent; an overcurrent protection circuit, controlled by the overcurrent signal, generating the overcurrent protection signal; The commutation control logic circuit includes: S1-S6 control logic modules, each of which is composed of an AND gate and an OR gate, and the signals of HA, HB, and HC after the logical negation operation are HA1, HB1, and HC1 respectively, and the signal of DIR after the logical negation operation is DIR1; the signal ST is an overcurrent protection signal; wherein: The S1 control logic module includes AND gates 1-4 and OR gate 1; the two input ends of AND gate 1 receive signals HA and HB1 respectively, and the two input ends of AND gate 2 are connected to the output end of AND gate 1 and signal DIR respectively; the two input ends of AND gate 3 receive signals HA1 and HB respectively, and the two input ends of AND gate 4 are connected to the output end of AND gate 3 and signal DIR1 respectively; the two input ends of OR gate 1 are connected to the output ends of AND gate 2 and AND gate 4 respectively, and the output end of OR gate 1 outputs signal S1; The S3 control logic module includes AND gates 5-8 and an OR gate 2; the two input ends of the AND gate 5 receive signals HB and HC1 respectively, and the two input ends of the AND gate 6 are connected to the output end of the AND gate 5 and the signal DIR respectively; the two input ends of the AND gate 7 receive signals HB1 and HC respectively, and the two input ends of the AND gate 8 are connected to the output end of the AND gate 7 and the signal DIR1 respectively; the two input ends of the OR gate 2 are connected to the output ends of the AND gate 6 and the AND gate 8 respectively, and the output end of the OR gate 2 outputs the signal S3; The S5 control logic module includes AND gates 9-12 and an OR gate 3; the two input ends of the AND gate 9 receive signals HC and HA1 respectively, and the two input ends of the AND gate 10 are respectively connected to the output end of the AND gate 9 and the signal DIR; the two input ends of the AND gate 11 receive signals HC1 and HA respectively, and the two input ends of the AND gate 12 are respectively connected to the output end of the AND gate 11 and the signal DIR1; the two input ends of the OR gate 3 are respectively connected to the output ends of the AND gate 10 and the AND gate 12, and the output end of the OR gate 3 outputs a signal S5; The S2 control logic module includes AND gates 13-19 and an OR gate 4; the two input ends of the AND gate 13 receive signals HC and HA1 respectively, and the two input ends of the AND gate 14 receive signals DIR1 and ST respectively; the two input ends of the AND gate 15 are connected to the output ends of the AND gates 13 and 14 respectively; the two input ends of the AND gate 16 receive signals HC1 and HA respectively, and the two input ends of the AND gate 17 receive signals DIR and ST respectively; the two input ends of the AND gate 18 are connected to the output ends of the AND gate 16 and the AND gate 17 respectively; the two input ends of the OR gate 4 are connected to the output ends of the AND gate 15 and the AND gate 18 respectively, the two input ends of the AND gate 19 are connected to the output end of the OR gate 4 and the PWM signal respectively, and the output end of the AND gate 19 outputs the signal S2; The S4 control logic module includes AND gates 20-26 and an OR gate 5; the two input ends of the AND gate 20 receive signals HA and HB1 respectively, and the two input ends of the AND gate 21 receive signals DIR1 and ST respectively; the two input ends of the AND gate 22 are connected to the output ends of the AND gate 20 and the AND gate 21 respectively; the two input ends of the AND gate 23 receive signals HA1 and HB respectively, and the two input ends of the AND gate 24 receive signals DIR and ST respectively; the two input ends of the AND gate 25 are connected to the output ends of the AND gate 23 and the AND gate 24 respectively; the two input ends of the OR gate 5 are connected to the output ends of the AND gate 22 and the AND gate 25 respectively, the two input ends of the AND gate 26 are connected to the output end of the OR gate 5 and the PWM signal respectively, and the output end of the AND gate 26 outputs the signal S4; The S6 control logic module includes AND gates 27-33 and OR gate 6; the two input ends of AND gate 27 receive signals HB and HC1 respectively, and the two input ends of AND gate 28 receive signals DIR1 and ST respectively; the two input ends of AND gate 29 are connected to the output ends of AND gate 27 and AND gate 28 respectively; the two input ends of AND gate 30 receive signals HB1 and HC respectively, and the two input ends of AND gate 31 receive signals DIR and ST respectively; the two input ends of AND gate 32 are connected to the output ends of AND gate 30 and AND gate 31 respectively; the two input ends of OR gate 6 are connected to the output ends of AND gate 29 and AND gate 32 respectively, the two input ends of AND gate 33 are connected to the output end of OR gate 6 and the PWM signal respectively, and the output end of AND gate 33 outputs signal S6.

2. The brushless DC motor control circuit with overcurrent protection according to claim 1, characterized in that: The corresponding relationship between the position Hall signals HA, HB, HC and the direction control signal DIR in the commutation control logic circuit and the commutation control logic signals S1-S6 is: If HA, HB, HC, and DIR are "1011" or "0100", signal S1 is high level, signals S2, S3, S4, and S5 are low level, and signal S6 is a PWM signal; If HA, HB, HC, and DIR are "1001" or "0110", signal S1 is at a high level, signals S3, S4, S5, and S6 are all at low levels, and signal S2 is a PWM signal; If HA, HB, HC, and DIR are "1101" or "0010", signal S3 is at a high level, signals S1, S4, S5, and S6 are all at low levels, and signal S2 is a PWM signal; If HA, HB, HC, and DIR are "0101" or "1010", signal S3 is at a high level, signals S1, S2, S5, and S6 are all at low levels, and signal S4 is a PWM signal; If HA, HB, HC, and DIR are "0111" or "1000", signal S5 is at a high level, signals S1, S2, S3, and S6 are all at low levels, and signal S4 is a PWM signal; If HA, HB, HC, and DIR are "0011" or "1100", signal S5 is at a high level, signals S1, S2, S3, and S4 are all at low levels, and signal S6 is a PWM signal; When DIR is 1, the motor rotates forward, and when DIR is 0, the motor rotates reversely.

3. The brushless DC motor control circuit with overcurrent protection according to claim 2, characterized in that: The signals S1, S3, and S5 are respectively used to control the opening or closing of the power tubes VT1, VT3, and VT5 in the upper bridge arm of the power main circuit; the signals S2, S4, and S6 are respectively used to control the opening or closing of the power tubes VT4, VT6, and VT2 in the lower bridge arm of the power main circuit; in the power main circuit, VT1 and VT4 are on one bridge arm, VT3 and VT6 are on one bridge arm, and VT5 and VT2 are on one bridge arm.

4. The brushless DC motor control circuit with overcurrent protection according to claim 3, characterized in that: If signal S1 is at a high level, signals S2, S3, S4, and S5 are all at low levels, and signal S6 is a PWM signal, then the input control signal UA of the A-phase brushless DC motor is DC+ / 2; the input control signal UB of the B-phase brushless DC motor is an alternating change between DC+ / 2 and 0; the input control signal UC of the C-phase brushless DC motor is a linear decrease from DC+ / 2 to -DC+ / 2; the alternating change between DC+ / 2 and 0 is: when the PWM signal is at a high level, it is 0, and when the PWM signal is at a low level, it is DC+ / 2; If signal S1 is high, signals S3, S4, S5, and S6 are all low, and signal S2 is a PWM signal, then UA is DC+ / 2; UC is an alternating change between DC+ / 2 and 0; UB is a linear increase from -DC+ / 2 to DC+ / 2; If signal S3 is at a high level, signals S1, S4, S5, and S6 are all at low levels, and signal S2 is a PWM signal, then UB is DC+ / 2, UC is an alternating change between DC+ / 2 and 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2; If signal S3 is at a high level, signals S1, S2, S5, and S6 are all at low levels, and signal S4 is a PWM signal, then UB is DC+ / 2, UA is an alternating change between DC+ / 2 and 0, and UC is a linear increase from -DC+ / 2 to DC+ / 2; If signal S5 is at a high level, signals S1, S2, S3, and S6 are all at low levels, and signal S4 is a PWM signal, then UC is DC+ / 2, UA is an alternating change between DC+ / 2 and 0, and UB is a linear decrease from DC+ / 2 to -DC+ / 2; If signal S5 is at a high level, signals S1, S2, S3, and S4 are all at low levels, and signal S6 is a PWM signal, then UC is DC+ / 2, UB is an alternating change between DC+ / 2 and 0, and UA is a linear increase from -DC+ / 2 to DC+ / 2.

5. The brushless DC motor control circuit with overcurrent protection according to claim 4, characterized in that: When the overcurrent protection circuit receives the overcurrent signal output by the power main circuit, the overcurrent protection signal output by the overcurrent protection circuit is a low level; otherwise, the output overcurrent protection signal is a high level; The overcurrent protection signal is input to the phase switching control logic circuit. When the overcurrent protection signal is at a low level, the phase switching control logic signals S2, S4 and S6 are pulled low.

6. The brushless DC motor control circuit with overcurrent protection according to claim 1, characterized in that: The circuit also includes a logical NOT circuit for performing the NOT logic operation on the position Hall signal and the direction control signal output by the brushless DC motor.

7. A brushless DC motor control method with overcurrent protection, characterized in that: The control method is implemented based on the brushless DC motor control circuit with overcurrent protection according to any one of claims 1 to 6, and the control method comprises the following steps: Based on the direction control signal, the PWM signal, the position Hall signal output by the brushless DC motor, the overcurrent protection signal, and the signal after the position Hall signal and the direction control signal are subjected to a negation logic operation, a commutation control logic signal adapted to the H-ON_L-PWM modulation mode is generated; amplifying the commutation control logic signal to obtain a driving signal; Based on the driving signal, the power main circuit is driven to perform the H-ON_L-PWM modulation process, output the motor input control signal, and use the input control signal to drive the brushless DC motor to work; When it is detected that the brushless DC motor is overcurrent, the main power circuit outputs an overcurrent signal and generates the overcurrent protection signal controlled by the overcurrent signal.

8. The brushless DC motor control method with overcurrent protection according to claim 7, characterized in that: The method further comprises: When it is detected that the brushless DC motor is overcurrent, the commutation control logic signals S2, S4 and S6 are pulled down based on the overcurrent protection signal.

9. The brushless DC motor control method with overcurrent protection according to claim 7 or 8, characterized in that: The driving signal is generated based on a driving circuit, wherein the driving circuit includes three IR2110 driving chips, and each IR2110 driving chip is used to drive the upper and lower power tubes of the same bridge arm in the power main circuit.

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