Elastic wave device and module including the same

Abstract

An elastic wave device includes: a wiring substrate; a device chip electrically connected to the wiring substrate; and a sealing portion sealing the device chip with the wiring substrate. The device chip includes a resonator for exciting elastic surface waves, a first metal layer electrically connected to the resonator, a first insulating layer formed on a portion of the surface of the first metal layer and on the resonator, and a second metal layer, the second metal layer being usable as a bump pad and formed on a region of the surface of the first metal layer not covered by the first insulating layer and on a region of the first insulating layer covering the first metal layer. This provides an elastic wave device capable of suppressing corrosion of the wiring and resonator in the device chip.

Description

Technical Field

[0001] This disclosure relates to an elastic wave device and a module comprising the elastic wave device. Background Technology

[0002] Patent document 1 (Japanese Patent Application Publication No. 2017-157922) illustrates an elastic wave device. The elastic wave device dissipates heat through a heat dissipation path such as a through-hole.

[0003] However, in the elastic wave device exemplified in Patent Document 1, the wiring and resonator of the device chip are exposed inside the sealed portion. Therefore, the wiring and resonator of the device chip are susceptible to corrosion. Summary of the Invention

[0004] In view of the above-mentioned problems, the present disclosure aims to provide an elastic wave device and a module including the elastic wave device that can suppress corrosion of wiring and resonators in a device chip.

[0005] This disclosure discloses an elastic surface wave device, comprising: a wiring substrate; a device chip electrically connected to the wiring substrate; and a sealing portion sealing the device chip with the wiring substrate. The device chip includes a resonator for exciting elastic surface waves, a first metal layer electrically connected to the resonator, a first insulating layer formed on a portion of the surface of the first metal layer and on the resonator, and a second metal layer. The second metal layer can be used as a bump pad and is formed on a region of the surface of the first metal layer not covered by the first insulating layer and on a region of the first insulating layer covering the first metal layer.

[0006] In one embodiment of this disclosure, the elastic wave device further comprises: a second insulating layer formed on a portion of the surfaces of the first insulating layer and the second metal layer.

[0007] In one embodiment of this disclosure, the first metal layer is not directly connected to the second insulating layer.

[0008] In one embodiment of this disclosure, the second metal layer is directly connected to the first metal layer, the first insulating layer, and the second insulating layer.

[0009] In one embodiment of this disclosure, the first insulating layer is directly connected to the first metal layer, the second metal layer, and the second insulating layer.

[0010] In one embodiment of this disclosure, the coefficient of thermal expansion of the first insulating layer is less than that of the second insulating layer.

[0011] In one embodiment of this disclosure, the width of the second metal layer is smaller than the width of the first metal layer.

[0012] In one embodiment of this disclosure, the device chip is formed by bonding a piezoelectric substrate and a support substrate, wherein the support substrate is made of sapphire, silicon, alumina, spinel, crystal, or glass.

[0013] In one embodiment of this disclosure, a second device chip is provided with a bandpass filter formed by a plurality of elastic surface wave resonators.

[0014] In one embodiment of the present disclosure, a second device chip is provided with a bandpass filter formed of a plurality of acoustic thin-film resonators.

[0015] This disclosure discloses an elastic surface wave device, comprising: a wiring substrate; a device chip electrically connected to the wiring substrate; and a sealing portion sealing the device chip with the wiring substrate. The device chip includes a resonator for exciting elastic surface waves, a first metal layer electrically connected to the resonator, a first insulating layer formed on a portion of the surface of the first metal layer and on the resonator, a second metal layer formed on a region of the surface of the first metal layer not covered by the first insulating layer and on a region of the first insulating layer covering the surface of the first metal layer, a third metal layer formed on a portion of the surface of the second metal layer and capable of being used as a bump pad, and a second insulating layer formed on the side surfaces of the first insulating layer, the second metal layer, the third metal layer, and a portion of the surface of the third metal layer.

[0016] In one embodiment of this disclosure, the width of the second metal layer is smaller than the width of the first metal layer, and the width of the third metal layer is smaller than the width of the second metal layer.

[0017] One embodiment of this disclosure includes a module comprising the elastic wave device.

[0018] The beneficial effect of the present invention is that, according to this disclosure, corrosion of wiring and resonators in the device chip can be suppressed. Attached Figure Description

[0019] Figure 1 This is a cross-sectional view of the elastic wave device in the first embodiment.

[0020] Figure 2 This is a top view of the device chip of the elastic wave device in the first embodiment.

[0021] Figure 3 This is a partial cross-sectional view of the device chip in the first embodiment.

[0022] Figure 4 This is a partial cross-sectional view of the device chip in the first embodiment.

[0023] Figure 5 This is a partial top view of the device chip in the first embodiment.

[0024] Figure 6 This is a schematic diagram of the elastic wave component of the device chip in the first embodiment.

[0025] Figure 7 This is a cross-sectional view of the elastic wave device in the second embodiment.

[0026] Figure 8 This is a schematic diagram of the elastic wave component of the second device chip of the elastic wave device in the second embodiment being an acoustic thin film resonator.

[0027] Figure 9 This is a partial cross-sectional view of the elastic wave device in the third embodiment.

[0028] Figure 10 This is a partial cross-sectional view of the elastic wave device in the third embodiment.

[0029] Figure 11 This is a partial top view of the elastic wave device in the third embodiment.

[0030] Figure 12 This is a partial cross-sectional view of the elastic wave device in the fourth embodiment.

[0031] Figure 13 This is a partial cross-sectional view of the elastic wave device in the fourth embodiment.

[0032] Figure 14 This is a partial top view of the elastic wave device in the fourth embodiment.

[0033] Figure 15 This is a cross-sectional view of a module using the elastic wave device in the fifth embodiment. Detailed Implementation

[0034] The specific embodiments of the present invention will be described below with reference to the accompanying drawings. It should be noted that the same or equivalent parts in each figure are labeled with the same reference numerals. The descriptions of the same or equivalent parts will be appropriately simplified or omitted.

[0035] (First Embodiment)

[0036] Figure 1 This is a cross-sectional view of the elastic wave device 1 in the first embodiment.

[0037] Figure 1 The elastic wave device 1 is an example of a duplexer.

[0038] like Figure 1 As shown, the elastic wave device 1 includes a wiring substrate 3, several bumps 15, a device chip 5, and a sealing part 17.

[0039] The wiring substrate 3 may be, for example, a multilayer substrate made of resin. The wiring substrate 3 may also be, for example, a low-temperature co-fired ceramic (LTCC) multilayer substrate formed of multiple dielectric layers.

[0040] The bump 15 is electrically connected to the wiring substrate 3. The bump 15 is, for example, a gold bump. The height of the bump 15 is, for example, between 20 μm and 50 μm. The bump 15 is electrically connected to the main surface of the device chip 5. Figure 1 Wiring on the lower surface.

[0041] The device chip 5 is bonded to the wiring substrate 3 via the bump 15.

[0042] The device chip 5 can be, for example, a substrate formed of piezoelectric single crystal such as lithium tantalate, lithium niobate, or quartz. The device chip 5 can also be a substrate formed of piezoelectric ceramic. Alternatively, the device chip 5 can be a substrate formed by bonding a piezoelectric substrate and a support substrate. The support substrate can be, for example, a substrate formed of sapphire, silicon, alumina, spinel, quartz, or glass.

[0043] The device chip 5 is a substrate equipped with functional components. For example, a receiving filter and a transmitting filter are provided on the main surface of the device chip 5.

[0044] The receiving filter is configured to allow electrical signals in the desired frequency band to pass through. For example, the receiving filter may be a trapezoidal filter composed of multiple series resonators and multiple parallel resonators.

[0045] The transmitting filter is configured to allow electrical signals in the desired frequency band to pass through. For example, the transmitting filter may be a trapezoidal filter composed of multiple series resonators and multiple parallel resonators.

[0046] The sealing portion 17 is formed to cover the device chip 5. The sealing portion 17 seals the device chip 5 with the wiring substrate 3. The sealing portion 17 is formed, for example, by an insulator such as synthetic resin. The sealing portion 17 is formed, for example, by metal. The sealing portion 17 is formed, for example, by an insulating layer and metal.

[0047] When the sealing portion 17 is formed of a synthetic resin, the synthetic resin is epoxy resin, polyimide, or the like. Preferably, the sealing portion 17 uses epoxy resin and is formed by a low-temperature curing process.

[0048] Next, using Figure 2 The structure of the device chip 5 is described.

[0049] Figure 2This is a top view of the device chip 5 of the elastic wave device 1 in the first embodiment.

[0050] like Figure 2 As shown, several elastic wave components 52 and wiring patterns 54 are formed on the main surface of the device chip 5.

[0051] The elastic wave component 52 includes several series resonators S1, S2, S3, S4, S5 and several parallel resonators P1, P2, P3, P4.

[0052] The series resonators S1, S2, S3, S4, and S5, along with the parallel resonators P1, P2, P3, and P4, are configured to function as transmitting filters. Other series resonators and other parallel resonators are configured to function as receiving filters.

[0053] The wiring pattern 54 can be made of suitable metals or alloys such as silver, aluminum, copper, titanium, and palladium. The wiring pattern 54 can also be a laminated metal film formed by stacking multiple metal layers. The thickness of the wiring pattern 54 is, for example, between 1500 nm and 4500 nm.

[0054] The wiring pattern 54 is electrically connected to the elastic wave assembly 52. ​​The wiring pattern 54 includes an antenna bump pad ANT, a transmit bump pad Tx, a receive bump pad Rx, and four ground bump pads GND. The bump pads are connected to the bump 15 during installation. Figure 2 Electrical connection (not shown in the image).

[0055] Next, using Figure 3 The wiring pattern 54 is described.

[0056] Figure 3 This is a partial cross-sectional view of the device chip 5 in the first embodiment.

[0057] like Figure 3 As shown, the wiring pattern 54 has a first metal layer 54a and a first insulating layer 54b. The first metal layer 54a is formed of metal. The first metal layer 54a is the bottom layer. The first insulating layer 54b is formed of resin. The first insulating layer 54b covers the surface of the first metal layer 54a.

[0058] Next, using Figure 4 and Figure 5 Explain the relationship between the bump pads and the elastic wave assembly 52.

[0059] Figure 4 This is a partial cross-sectional view of the device chip 5 in the first embodiment.

[0060] Figure 5 This is a partial top view of the device chip 5 in the first embodiment.

[0061] exist Figure 4 In this configuration, the first metal layer 54a is electrically connected to the elastic wave assembly 52. ​​A first insulating layer 54b is formed on a portion of the surface of the first metal layer 54a and on the elastic wave assembly 52. ​​Specifically, the first insulating layer 54b covers a portion of the surface of the first metal layer 54a in the area where bump pads are formed. The first insulating layer 54b also covers the elastic wave assembly 52.

[0062] In the region where the bump pads are formed, the wiring pattern 54 has a second metal layer 54c. The second metal layer 54c is formed of metal. The second metal layer 54c is formed on the surface of the first metal layer 54a in areas not covered by the first insulating layer 54b, and on the surface of the first insulating layer 54b covering the first metal layer 54a. The width M2 of the second metal layer 54c is smaller than the width M1 of the first metal layer 54a. The second metal layer 54c is electrically connected to the bump 15.

[0063] like Figure 5 As shown, in the region where the bump pads are formed, viewed from a direction perpendicular to the wiring pattern 54, the outer edge of the second metal layer 54c is located within the inner region of the first metal layer 54a. Figure 4 As shown, the width M2 of the second metal layer 54c is smaller than the width M1 of the first metal layer 54a.

[0064] For example, the width M1 of the first metal layer 54a is approximately 130 μm. For example, the width M2 of the second metal layer 54c is approximately 127 μm. In this case, the offset O1 of the outer edge of the second metal layer 54c relative to the outer edge of the first metal layer 54a is approximately 1.5 μm.

[0065] In the region where the bump pads are formed, the offset O2 of the outer edge of the first insulating layer 54b relative to the outer edge of the second metal layer 54c is approximately 2.0 μm.

[0066] The maximum diameter B of the bump 15 is approximately 120 μm. Therefore, the bump 15 can be stably bonded to the second metal layer 54c, which serves as a bump pad.

[0067] Next, using Figure 6 An example illustrating the elastic wave component 52.

[0068] Figure 6 This is a schematic diagram of the elastic wave component 52 of the device chip 5 in the first embodiment.

[0069] like Figure 6As shown, the main surface of the device chip 5 is provided with an IDT (Interdigital Transducer) 52a and a pair of reflectors 52b. The IDT 52a and the reflectors 52b are provided for exciting elastic surface waves.

[0070] For example, the IDT 52a and the reflector 52b are made of an alloy of aluminum and copper. Alternatively, the IDT 52a and the reflector 52b are made of a suitable metal such as titanium, palladium, or silver, or an alloy thereof. For example, the IDT 52a and the reflector 52b can be a stacked metal film formed by stacking multiple metal layers. The thickness of the IDT 52a and the reflector 52b is, for example, between 150 nm and 400 nm.

[0071] The IDT 52a has a pair of comb-shaped electrodes 52c. The comb-shaped electrodes 52c are opposite to each other. Each comb-shaped electrode 52c has a plurality of electrode fingers 52d and a bus bar 52e. The electrode fingers 52d extend longitudinally. The bus bar 52e connects the electrode fingers 52d.

[0072] One of the reflectors 52b is adjacent to one side of the IDT 52a. The other reflector 52b is adjacent to the other side of the IDT 52a.

[0073] According to the first embodiment described above, the first insulating layer 54b is formed on a portion of the surface of the first metal layer 54a and the elastic wave assembly 52. ​​The second metal layer 54c is formed on the area of ​​the surface of the first metal layer 54a not covered by the first insulating layer 54b and on the area of ​​the first insulating layer 54b covering the surface of the first metal layer 54a. Therefore, the second metal layer 54c, which serves as a bump pad, is exposed, thereby suppressing corrosion of the first metal layer 54a, which serves as wiring, and the elastic wave assembly 52. ​​Thus, a wiring structure with low loss, high reliability, and high durability can be achieved.

[0074] Furthermore, the device chip is formed by bonding a piezoelectric substrate and a support substrate, the support substrate being made of sapphire, silicon, alumina, spinel, crystal, or glass. Therefore, corrosion of the first metal layer 54a, which serves as wiring, and the elastic wave component 52 can be reliably suppressed.

[0075] Furthermore, the width M2 of the second metal layer 54c is smaller than the width M1 of the first metal layer 54a. Therefore, the second metal layer 54c can be formed stably, and corrosion of the first metal layer 54a, which serves as wiring, and the elastic wave component 52 can be reliably suppressed.

[0076] It should be noted that the device chip 5 can also be used as a single bandpass filter. In this case, corrosion of the first metal layer 54a, which serves as wiring, and the elastic wave component 52 can also be suppressed.

[0077] (Second Embodiment)

[0078] Figure 7 This is a cross-sectional view of the elastic wave device 1 in the second embodiment. It should be noted that the same or equivalent parts as in the first embodiment are labeled with the same reference numerals. Descriptions of these same or equivalent parts will be omitted.

[0079] like Figure 7 As shown, the elastic wave device 1 includes a first device chip 5a and a second device chip 5b. Both the first device chip 5a and the second device chip 5b function as bandpass filters. For example, the first device chip 5a functions as either a transmitting filter or a receiving filter, and the second device chip 5b functions as either a transmitting filter or a receiving filter.

[0080] The first device chip 5a and the device chip 5 of the first embodiment have the same structure. The second device chip 5b and the device chip 5 of the first embodiment have different or the same structure.

[0081] For example, the first device chip 5a has the same elastic wave component 52 as in the first embodiment. Specifically, the first device chip 5a is provided with a bandpass filter formed by a plurality of elastic surface wave resonators.

[0082] Provided that the second device chip 5b and the device chip 5 of the first embodiment have different structures, for example, the second device chip 5b has the same elastic wave component 52 as the first embodiment. Specifically, the second device chip 5b is provided with a bandpass filter formed by a plurality of elastic surface wave resonators.

[0083] For example, the second device chip 5b has an elastic wave component 52 that differs from that of the first embodiment. Specifically, the second device chip 5b is provided with a bandpass filter formed by a plurality of acoustic thin-film resonators.

[0084] Next, using Figure 8 This illustrates that the elastic wave component 52 of the second device chip 5b is an example of an acoustic thin film resonator.

[0085] Figure 8 This is a schematic diagram of the elastic wave component 52 of the second device chip 5b of the elastic wave device 1 in the second embodiment being an acoustic thin film resonator.

[0086] exist Figure 8In this embodiment, the chip substrate 60 serves as the second device chip 5b. For example, the chip substrate 60 is a semiconductor substrate such as silicon, or an insulating substrate such as sapphire, alumina, spinel, or glass.

[0087] A piezoelectric film 62 is disposed on the chip substrate 60. For example, the piezoelectric film 62 is made of aluminum nitride.

[0088] The lower electrode 64 and the upper electrode 66 sandwich the piezoelectric film 62 therein. For example, the lower electrode 64 and the upper electrode 66 are made of a metal such as aluminum.

[0089] A gap 68 is formed between the lower electrode 64 and the chip substrate 60.

[0090] In the acoustic thin film resonator, the lower electrode 64 and the upper electrode 66 excite elastic waves in the thickness longitudinal vibration mode within the piezoelectric film 62.

[0091] According to the second embodiment described above, the second device chip 5b is provided with a bandpass filter formed by a plurality of elastic surface wave resonators. In this case, corrosion of the first metal layer 54a, which serves as wiring, and the elastic wave component 52 in the first device chip 5a can be suppressed.

[0092] Furthermore, the second device chip 5b is provided with a bandpass filter formed by multiple acoustic thin-film resonators. In this case, corrosion of the first metal layer 54a, which serves as wiring, and the elastic wave component 52 can be suppressed in the first device chip 5a.

[0093] (Third Embodiment)

[0094] Figure 9 This is a partial cross-sectional view of the elastic wave device in the third embodiment.

[0095] It should be noted that the same or equivalent parts as in the first embodiment are marked with the same reference numerals. Descriptions of the same or equivalent parts will be omitted.

[0096] like Figure 9 As shown, the wiring pattern 54 has a second insulating layer 54d. The second insulating layer 54d is formed on the first insulating layer 54b and on the surface of the second metal layer 54c.

[0097] Next, using Figure 10 and Figure 11 Explain the relationship between the bump pads and the elastic wave assembly 52.

[0098] Figure 10 This is a partial cross-sectional view of the elastic wave device in the third embodiment. Figure 11 This is a partial top view of the elastic wave device in the third embodiment.

[0099] like Figure 10 As shown, in the region where the bump pad is formed, the second insulating layer 54d is formed on a portion of the surface of the first insulating layer 54b and the second metal layer 54c. The second insulating layer 54d also covers the first insulating layer 54b in the region of the elastic wave assembly 52. ​​The second metal layer 54c can be used as a bump pad.

[0100] like Figure 11 As shown, in the region where the bump pads are formed, viewed from a direction perpendicular to the wiring pattern 54, the outer edge of the second insulating layer 54d is located within the inner region of the second metal layer 54c. Figure 10 As shown, in the region where the bump pads are formed, the offset O3 of the outer edge of the second insulating layer 54d relative to the outer edge of the second metal layer 54c is approximately 2.0 μm. In this case, the width W of the exposed portion of the second metal layer 54c is approximately 123 μm.

[0101] The maximum diameter B of the bump 15 is approximately 120 μm. Therefore, the bump 15 can stably bond to the second metal layer 54c, which serves as a bump pad.

[0102] In the region where the bump pads are formed, the first metal layer 54a is not directly connected to the second insulating layer 54d. The second metal layer 54c is directly connected to the first metal layer 54a, the first insulating layer 54b, and the second insulating layer 54d. The first insulating layer 54b is directly connected to the first metal layer 54a, the second metal layer 54c, and the second insulating layer 54d.

[0103] According to the third embodiment described above, in the region where the bump pad is formed, the second insulating layer 54d is formed on a portion of the surface of the first insulating layer 54b and the second metal layer 54c. Therefore, corrosion of the first metal layer 54a, the second metal layer 54c, and the elastic wave assembly 52 can be suppressed more reliably.

[0104] Furthermore, the first metal layer 54a is not directly connected to the second insulating layer 54d. Therefore, even if the second insulating layer 54d deteriorates, corrosion of the first metal layer 54a, which serves as the wiring, can be reliably suppressed.

[0105] Furthermore, the second metal layer 54c is directly connected to the first metal layer 54a, the first insulating layer 54b, and the second insulating layer 54d. Therefore, the bonding strength of each layer can be maintained.

[0106] Furthermore, the first insulating layer 54b directly contacts the first metal layer 54a, the second metal layer 54c, and the second insulating layer 54d. Therefore, the bonding strength of the first insulating layer 54b can be maintained.

[0107] Furthermore, the coefficient of thermal expansion of the first insulating layer 54b is smaller than that of the second insulating layer 54d. Therefore, it can suppress the peeling of the second insulating layer 54d caused by the thermal expansion of the first insulating layer 54b.

[0108] (Fourth Embodiment)

[0109] Figure 12 This is a partial cross-sectional view of the elastic wave device in the fourth embodiment. It should be noted that parts that are the same as or equivalent to those in the third embodiment are labeled using the same reference numerals. Descriptions of these same or equivalent parts will be omitted.

[0110] like Figure 12 As shown, the wiring pattern 54 has a third metal layer 54e. The third metal layer 54e is formed on a portion of the surface of the second metal layer 54c.

[0111] The second insulating layer 54d is formed on the side of the first insulating layer 54b, the second metal layer 54c, the side of the third metal layer 54e, and the surface of the third metal layer 54e.

[0112] Next, using Figure 13 and Figure 14 Explain the relationship between the bump pads and the elastic wave assembly 52.

[0113] Figure 13 This is a partial cross-sectional view of the elastic wave device in the fourth embodiment. Figure 14 This is a partial top view of the elastic wave device in the fourth embodiment.

[0114] like Figure 13 As shown, in the region where the bump pad is formed, the second insulating layer 54d is formed on the side of the first insulating layer 54b, the side of the second metal layer 54c, the side of the third metal layer 54e, and a portion of the surface of the third metal layer 54e. The third metal layer 54e can be used as a bump pad.

[0115] like Figure 14 As shown, in the region where the bump pads are formed, viewed from a direction perpendicular to the wiring pattern 54, the outer edge of the third metal layer 54e is located within the inner region of the second metal layer 54c. Figure 13 As shown, the width M3 of the third metal layer 54e is smaller than the width M2 of the second metal layer 54c.

[0116] For example, the width M3 of the third metal layer 54e is approximately 123 μm. In this case, the offset O3 of the outer edge of the third metal layer 54e relative to the outer edge of the second metal layer 54c is approximately 2.0 μm.

[0117] In the region where the bump pads are formed, the offset O4 of the outer edge of the second insulating layer 54d relative to the outer edge of the third metal layer 54e is approximately 2.0 μm. In this case, the width W of the exposed portion of the third metal layer 54e is approximately 119 μm.

[0118] The maximum diameter of the bump 15 is approximately 120 μm. Therefore, in Figure 14 In this context, it is evident that the bump 15 overlaps with the outer edge of the second insulating layer 54d. However, as... Figure 13 As shown, the maximum diameter of the bump 15 is located above the second insulating layer 54d. Therefore, the bump 15 does not contact the second insulating layer 54d. Consequently, the bump 15 can stably bond to the third metal layer 54e, which serves as a bump pad.

[0119] According to the fourth embodiment described above, the second insulating layer 54d is formed on the side surface of the first insulating layer 54b, the side surface of the second metal layer 54c, the side surface of the third metal layer 54e, and a portion of the surface of the third metal layer 54e. Therefore, corrosion of the first metal layer 54a, the second metal layer 54c, the third metal layer 54e (serving as wiring), and the elastic wave assembly 52 can be reliably suppressed.

[0120] Furthermore, the width M2 of the second metal layer 54c is smaller than the width M1 of the first metal layer 54a. The width M3 of the third metal layer 54e is smaller than the width M2 of the second metal layer 54c. Therefore, the second metal layer 54c and the third metal layer 54e can be stably formed, and corrosion of the first metal layer 54a, the second metal layer 54c, the third metal layer 54e as wiring, and the elastic wave component 52 can be reliably suppressed.

[0121] (Fifth Embodiment)

[0122] Figure 15 This is a cross-sectional view of a module using the elastic wave device in the fifth embodiment. It should be noted that parts that are the same as or equivalent to those in the first embodiment are labeled with the same reference numerals. Descriptions of these same or equivalent parts will be omitted.

[0123] exist Figure 12 In the module 100, there are wiring board 130, integrated circuit component IC, elastic wave device 1, inductor 111, and sealing part 117.

[0124] The wiring substrate 130 is the same as the wiring substrate 3 in the first embodiment.

[0125] Although not shown in the figure, the integrated circuit component IC is mounted inside the wiring substrate 130. The integrated circuit component IC includes switching circuitry and a low-noise amplifier.

[0126] The elastic wave device 1 is installed on the main surface of the wiring substrate 130.

[0127] The inductor 111 is mounted on the main surface of the wiring substrate 130. The inductor 111 is mounted for impedance matching. For example, the inductor 111 is an integrated passive device (IPD).

[0128] The sealing part 117 seals multiple electronic components, including the elastic wave device 1.

[0129] According to the fifth embodiment described above, the module 100 includes the elastic wave device 1. Therefore, a module 100 comprising an elastic wave component 1 capable of suppressing corrosion of the first metal layer 54a (which serves as wiring) and the elastic wave component 52 can be implemented.

[0130] While at least one embodiment has been described above, it should be understood that various changes, modifications, or improvements will readily occur to those skilled in the art. These changes, modifications, or improvements are also part of this disclosure and fall within the scope of this invention.

[0131] It should be understood that the embodiments of the methods or apparatus described herein are not limited to the architecture and arrangement of the constituent components described above or illustrated in the accompanying drawings. The methods and apparatus can be installed or performed in other embodiments.

[0132] The embodiments described are for illustrative purposes only and are not intended to be limiting.

[0133] The descriptions and terms used in this disclosure are for illustrative purposes only and are not intended to be limiting. The use of "including," "possessing," "having," "comprise," and variations thereof here means to include the items listed below, their equivalents, and additional items.

[0134] The word “or”, or any word used in a description, may be interpreted as one, more than one, or all of the descriptive words.

[0135] The references to front, back, left, right, top, bottom, upper, lower, and horizontal and vertical are for ease of description and are not intended to limit the position and spatial configuration of any component in this invention. Therefore, the above description and drawings are merely exemplary.

Claims

1. An elastic wave device, comprising: Wiring substrate; A device chip electrically connected to the wiring substrate; The sealing portion of the device chip is sealed to the wiring substrate. Its features are: The device chip includes a resonator that excites elastic surface waves, a first metal layer electrically connected to the resonator, a first insulating layer formed on a portion of the surface of the first metal layer and the resonator, and a second metal layer that can be used as a bump pad and is formed on a region of the surface of the first metal layer not covered by the first insulating layer and on a region of the first insulating layer that covers the first metal layer. It also includes a second insulating layer formed on a portion of the surface of the first insulating layer and the second metal layer. When viewed from a direction perpendicular to the wiring substrate, the edge of the second metal layer is in the inner region of the first metal layer, and the edge of the second insulating layer is located in the inner region of the second metal layer.

2. The elastic wave device according to claim 1, characterized in that: The first metal layer is not directly connected to the second insulating layer.

3. The elastic wave device according to claim 1, characterized in that: The second metal layer is directly connected to the first metal layer, the first insulating layer, and the second insulating layer.

4. The elastic wave device according to claim 1, characterized in that: The first insulating layer is directly connected to the first metal layer, the second metal layer, and the second insulating layer.

5. The elastic wave device according to claim 1, characterized in that: The coefficient of thermal expansion of the first insulating layer is less than that of the second insulating layer.

6. The elastic wave device according to claim 1, characterized in that: The width of the second metal layer is smaller than the width of the first metal layer.

7. The elastic wave device according to claim 1, characterized in that: The device chip is formed by bonding a piezoelectric substrate and a support substrate, wherein the support substrate is made of sapphire, silicon, alumina, spinel, crystal or glass.

8. The elastic wave device according to claim 1, characterized in that: The elastic wave device further includes a second device chip equipped with a bandpass filter formed by multiple elastic surface wave resonators.

9. The elastic wave device according to claim 1, characterized in that: The elastic wave device further includes a second device chip equipped with a bandpass filter formed by multiple acoustic thin-film resonators.

10. An elastic wave device, comprising: Wiring substrate; A device chip electrically connected to the wiring substrate; The sealing portion of the device chip is sealed to the wiring substrate. Its features are: The device chip includes a resonator that excites surface waves, a first metal layer electrically connected to the resonator, a first insulating layer formed on a portion of the surface of the first metal layer and the resonator, a second metal layer formed on a region of the surface of the first metal layer not covered by the first insulating layer and on a region of the first insulating layer covering the surface of the first metal layer, a third metal layer formed on a portion of the surface of the second metal layer and usable as a bump pad, and a second insulating layer formed on the side surfaces of the first insulating layer, the second metal layer, the third metal layer, and a portion of the surface of the third metal layer. When viewed from a direction perpendicular to the wiring substrate, the edge of the second insulating layer is within the region of the third metal layer, the edge of the third metal layer is within the region of the second metal layer, and the edge of the second metal layer is within the region of the first metal layer.

11. The elastic wave device according to claim 10, characterized in that: The width of the second metal layer is smaller than the width of the first metal layer, and the width of the third metal layer is smaller than the width of the second metal layer.

12. A module comprising the elastic wave device according to any one of claims 1 to 11.

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