body switch circuit

Abstract

The invention relates to a bulk switch circuit comprising: a first transistor coupled to a load and having a source coupled to a source voltage and a drain coupled to a drain voltage; a second transistor and a third transistor coupled in series with each other between the source voltage and the drain voltage in parallel with the first transistor, wherein a bulk of the first transistor is coupled with a bulk of the second transistor and the third transistor, wherein a gate of the second transistor is coupled to the source voltage via a first impedance circuit and a gate of the third transistor is coupled to the drain voltage via a second impedance circuit to form a comparator switch controlled by the source voltage and the drain voltage and to dynamically switch the larger of the source voltage and the drain voltage to the load.

Description

Technical Field

[0001] Various example implementations relate to power transistors, and in particular to body-switching transistor circuits. Background Technology

[0002] Body-switching transistor circuits can be used in implementations such as battery chargers and rectifiers. In such implementations, the body of the (metal-oxide-semiconductor, MOS) power transistor can dynamically switch between the source and drain voltages of the power transistor. For example, this dynamic switching may be preferred when the source and drain voltages are variable (floating switch). However, the switching should be fast to overcome the adverse effects of parasitic coupling in the power transistor. Figure 1 This represents a conventional body-switching circuit. When the source voltage VS of power transistor M0 rises above the drain voltage VD, the transconductance of switching transistor M2 decreases, while the transconductance of switching transistor M1 increases, thereby coupling the source voltage to the body of power transistor M0. The transconductance of transistor M1 is defined by the difference between VS and VD, and if this difference is below the threshold voltage of transistor M1, the coupling between the source voltage VS and the body voltage VB decreases. This allows the source voltage VS to... Figure 1 The parasitic diode shown is coupled to the bodies of transistors M0, M1, and M2. A similar leakage exists for transistor M2. This leakage can cause unintended power leakage to the load of the body switching circuit, or even cause the power transistor M0 to latch up. Summary of the Invention

[0003] According to one aspect, an apparatus is provided, comprising: a body-controlled switching circuit including: a first transistor (MP0) coupled to a load and having a source coupled to a source voltage (VS) and a drain coupled to a drain voltage (VD); a second transistor (MPA) and a third transistor (MPB) connected in series with the first transistor in parallel between the source voltage and the drain voltage; wherein the body of the first transistor is coupled to the bodies of the second and third transistors; and wherein the gate of the second transistor is coupled to the source voltage via a first impedance circuit (RU1) and the gate of the third transistor is coupled to the drain voltage via a second impedance circuit (RU2). The circuit comprises: a source voltage and a drain voltage, forming a comparator switch controlled by the source voltage and the drain voltage, and dynamically switching the larger of the source voltage and the drain voltage to the load; a first current generator circuit and a second current generator circuit (IDC1); a first current mirror circuit (MP3, MP4), which is biased by the first current generator circuit and responsive to the source voltage, and configured to trigger a second transistor to couple the source voltage to the load when the source voltage is higher than the drain voltage; and a second current mirror circuit (MP1, MP2), which is biased by the second current generator circuit and responsive to the drain voltage, and configured to trigger a third transistor to couple the drain voltage to the load when the drain voltage is higher than the source voltage.

[0004] The technique of using a current mirror circuit biased by a current generator circuit is faster and more accurate, and reduces leakage through parasitic diode coupling as described in the background art.

[0005] In one embodiment, the device further includes constant current generators (IDC2, IDC3), which serve as loads for the first and second current mirror circuits, respectively, and the constant current generators are configured to generate non-zero hysteresis for the comparator switches. The technical advantage is improved control in the body switches. The hysteresis configuration helps avoid erroneous comparator switching, for example, due to thermal noise.

[0006] In this implementation, the constant current generator is configured to generate a threshold voltage level for coupling the source voltage that is different from the threshold voltage level used for coupling the drain voltage. The technical advantage is improved control in the body switch to optimize a specific voltage domain (source voltage domain or drain voltage domain).

[0007] In one implementation, the first impedance circuit includes a first resistor between the gate and source voltages of the second transistor, and the second impedance circuit includes a second resistor between the gate and drain voltages of the third transistor. The technical advantage of the resistors is that switching can be performed even when the current generator is disabled.

[0008] In this implementation, the first impedance circuit is grounded via a fourth transistor (MN2) and the second impedance circuit is grounded via a fifth transistor (MN3), wherein the second current mirror circuit is coupled to the gate of the fourth transistor and the first current mirror circuit is coupled to the gate of the fifth transistor. The technical effect is improved control during switching.

[0009] In this embodiment, the first, second, and third transistors are positive metal-oxide-semiconductor (PMOS) transistors, and the device includes at least one additional PMOS transistor and at least one negative metal-oxide-semiconductor (NMOS) transistor, wherein the body of all PMOS transistors is coupled to the same body voltage, and wherein the body of all NMOS transistors is grounded. The technical effect is improved body switching performance.

[0010] In this embodiment, both the first and second current mirror circuits include diode-coupled transistors (MP1, MP3) and current source transistors (MP2, MP4). The current source transistor (MP4) of the first current mirror circuit is coupled to the gate of a sixth transistor (MN4), which drives a constant current source (IDC3) serving as the load of the current source transistor (MP2) of the second current mirror circuit. Furthermore, the current source transistor (MP2) of the second current mirror circuit is coupled to the gate of a seventh transistor (MN1), which drives the constant current source (IDC3) serving as the load of the current source transistor (MP4) of the first current mirror circuit. This arrangement further improves the performance of the body switch.

[0011] In one implementation, a first current mirror circuit is configured to increase the coupling of the source voltage to the load in response to the source voltage rising above the drain voltage, while a second current mirror circuit is configured to increase the decoupling of the drain voltage to the load. This dual functionality enables rapid switching.

[0012] In one embodiment, at least one of the first and second current mirror circuits comprises a cascode amplifier with multiple current mirror circuits. The cascode amplifier improves the accuracy of body switching.

[0013] According to one aspect, a rectifier circuit is provided, which includes the means of any of the above embodiments.

[0014] According to one aspect, a charger device is provided, which includes the means of any of the above embodiments. The charger device may be a battery charger.

[0015] The embodiments are defined in the dependent claims. The scope of protection sought by the various embodiments is given in the independent claims.

[0016] The embodiments and features described in this specification that do not fall within the scope of the independent claims (if any) are to be interpreted as examples useful for understanding various embodiments of the invention. Attached Figure Description

[0017] In the following description, exemplary embodiments will be described in more detail with reference to the accompanying drawings, in which:

[0018] Figure 1 This illustrates a conventional body switch circuit;

[0019] Figure 2 A body switch circuit according to an embodiment is shown;

[0020] Figure 3 and Figure 4 This shows that when the source voltage varies with respect to the drain voltage at a threshold level... Figure 2 The operation of the body switch circuit;

[0021] Figure 5 The hysteresis effect according to the implementation method is shown;

[0022] Figure 6 A body switch circuit according to yet another embodiment is shown. Detailed Implementation

[0023] The following embodiments are examples. Although the specification may refer to "a," "an," or "some" embodiments in several places, this does not necessarily mean that each such reference refers to the same(s) embodiments(s), or that a feature applies only to a single embodiment. Individual features of different embodiments may also be combined to provide other embodiments. Furthermore, the words "comprising" and "including" should be understood not to limit the described embodiments to consisting only of those features already mentioned, and such embodiments may also include features / structures not specifically mentioned.

[0024] According to an embodiment, an apparatus is provided, comprising a body-controlled switching circuit including: a first transistor coupled to a load and having a source coupled to a source voltage VS and a drain coupled to a drain voltage VD; a second transistor and a third transistor connected in series with the first transistor in parallel between the source voltage and the drain voltage, wherein the body of the first transistor is coupled to the bodies of the second and third transistors, wherein the gate of the second transistor is coupled to the source voltage via a first impedance circuit and the gate of the third transistor is coupled to the drain voltage via a second impedance circuit, to form a comparator switch controlled by the source voltage and the drain voltage and dynamically switching the larger of the source voltage and the drain voltage to the load. The body-controlled switching circuit further includes a first current generator circuit and a second current generator circuit. The body-controlled switching circuit also includes a first current mirror circuit biased by the first current generator circuit and responsive to the source voltage, and configured to trigger the second transistor to couple the source voltage to the load when the source voltage is higher than the drain voltage. The body control switch circuit also includes a second current mirror circuit, which is biased by a second current generator circuit and responsive to the drain voltage, and is configured to trigger a third transistor to couple the drain voltage to the load when the drain voltage is higher than the source voltage.

[0025] Reference Figure 1 The first, second, and third transistors can correspond to transistors M0, M1, and M2, respectively. As an additional component to accelerate the response to changes in source voltage VS or drain voltage, a current mirror circuit biased by a current generator circuit is provided. The bias enables control of the switch, defining a threshold voltage for VS or VD when the switch is triggered. As described in more detail below, the current mirror arrangement improves the response time to changes.

[0026] Figure 2 An embodiment of a circuit including the above-described device is shown. Figure 2 In the diagram, the first transistor, the second transistor, and the third transistor are represented by MP0, MPA, and MPB, respectively. For example... Figure 2As shown, power transistor MP0 is coupled in parallel with switching transistors MPA and MPB, which are arranged in series, between VS and VD. Specifically, the sources of transistor MPA and MPB are coupled together, the drain of transistor MPA is coupled to the source voltage VS, and the drain of transistor MPB is coupled to the drain voltage VD. The source of transistor MP0 is coupled to the source voltage VS, and the drain of transistor MP0 is coupled to the drain voltage VD. The bodies of the transistors are coupled together, and the body voltage is represented by VB. The gate of transistor MPA is coupled to the drain voltage VD via a second impedance circuit RU2, while the gate of transistor MPB is coupled to the source voltage VS via a first impedance circuit RU1. In this embodiment, transistors MP0, MPA, and MPB are positive metal-oxide-semiconductor (PMOS) transistors.

[0027] The first current mirror circuit is represented by a diode-connected transistor MP3 and a transistor MP4 coupled to and responding to the source voltage VS. The second current mirror circuit is represented by a diode-connected transistor MP1 and a transistor MP2 coupled to and responding to the drain voltage VD. The first current generator circuit is represented by a current source IDC1 coupled to the gates of transistors MP3 and MP4. The second current generator circuit is represented by a current source IDC1 coupled to the gates of transistors MP1 and MP2. Figure 2 As shown, current source IDC1 defines the bias voltages of the first and second current mirror circuits by contributing to the gate voltages of transistors MP1 through MP4 respectively. In this embodiment, current source IDC1 maintains the gate voltages of current mirror transistors MP1 through MP4 at a constant level.

[0028] Although both current mirror circuits are coupled to both VS and VD, the coupling of the first current mirror circuit MP3, MP4 to the gate of MPA causes it to select MPA in response to a rise in VS. Similarly, the coupling of the second current mirror circuit MP1, MP2 to the gate of MPB causes it to select MPB in response to a rise in VD.

[0029] Furthermore, current mirrors IDC2 and IDC3 can be coupled to the drain of the current mirror circuit to draw current from the current mirror (IDC2) and introduce hysteresis into the selection of MPA / MPB (IDC3). See below. Figure 5 Describe the lag in more detail.

[0030] The first current mirror circuit can be arranged to drive a first set of additional transistors MN3 and MN4. Transistor MN3 is coupled between the second impedance circuit RU2 and ground, thereby driving the second impedance circuit and controlling transistor MPA. Transistor MN4 operates as a switch, selectively switching... Figure 2The current source IDC3 on the right is coupled to ground, thus affecting hysteresis, as described below. Similarly, the second current mirror circuit can be arranged to drive a second set of additional transistors MN1 and MN2. Transistor MN2 is coupled between the first impedance circuit RU1 and ground, thereby driving the first impedance circuit RU1 and controlling transistor MPB. Transistor MN1 operates as a switch, selectively switching... Figure 2 The current source IDC3 on the left is coupled to ground, which affects the hysteresis, as described below.

[0031] Then refer to Figure 3 as well as Figure 4 To describe using timing diagrams Figure 2 The operation of the bias comparator circuit. Figure 3 It shows the relationship with Figure 2 The same circuit diagram, but with additional markings for the voltages of some signal lines, and furthermore, arrows indicating the voltage changes in the circuit when the source voltage VS rises above the drain voltage VD. VHS and VHD represent the drain voltages of transistors MP4 and MP2, respectively. VPA and VPB represent the gate voltages of transistors MPA and MPB, respectively. When VPA enters the LOW state, VPA closes the switch MPA, thereby coupling the source voltage to the body. Similarly, when VPB enters the LOW state, VPB closes the switch MPB, thereby coupling the drain voltage to the body. VBPD and VBPS represent the gate (bias) voltages of the first and second current mirror circuits, respectively. (Refer to...) Figure 3 and Figure 4 Let's assume the source voltage VS rises above the drain voltage. In this case, the circuit's function is to couple the source voltage to the load, which is then body-coupled to transistors MP0, MPA, and MPB. Figure 4 The top diagram shows the source voltage VS starting to rise and the drain voltage VD turning off. Before VS exceeds VD, because the gate-source voltage of transistor MP4 increases, current flows through transistor MP4 ( Figure 4 The current in I_MP4 increases. This is because the gate voltage VBPD remains constant, due to... Figure 3 The current source IDC1 on the right is driving the MP4. Because the source voltage of MP4 increases and the gate voltage is fixed, the transconductance of MP4 increases, and therefore the current I_MP4 increases. The load on MP4 is the constant current source IDC2, which is driven when the gate-source voltage of MP4 is high enough to drive both current sources IDC2 and IDC3 together, i.e., when the source voltage is sufficiently higher than the drain voltage (in...). Figure 4 (As shown by IDC2+IDC3), the constant current source IDC2 again raises the voltage VHS to the high level of the threshold. Figure 2 and Figure 3As shown and as described above, VHS drives transistors MN3 and MN4. When VHS goes high due to a sufficiently high source voltage VS, MN3 couples VPA to ground, thereby pulling VPA to a LOW state. As mentioned above, a low VPA will cause transistor MPA to couple its source voltage to the load.

[0032] Therefore, the second current mirror circuit effectively reduces the impedance between the body voltage VB and the source voltage VS, thereby coupling the source voltage to the body voltage and the load. There is another mechanism in the circuit that affects the rapid coupling of the source voltage to the load, and this mechanism is transmitted via the first current mirror circuit. Since transistor MP1 is also coupled to the source voltage and has a constant current source as its load, the transconductance and gate-source voltage of MP1 increase in a similar manner to those in MP4, which again reduces the gate-source voltage at transistor MP2. As a result, as Figure 4 As shown, the current source IDC2 at the load of transistor MP2 pulls VHD to the LOW state. This essentially occurs simultaneously with triggering VHS to the HIGH state. When voltage VHD is in the LOW state, transistors MN1 and MN2 are off, causing voltage VPB to increase towards the source voltage, thereby disconnecting switch MPB and defining a high impedance between the drain voltage and the body, effectively decoupling the drain voltage from the body. This dual effect provides fast coupling capability for comparator circuits MPA and MPB.

[0033] Then, the operation follows when the source voltage VS drops below the drain voltage VD. Since the source voltage VS is coupled to the bodies of transistors MP0, MPA, and MPB, the source voltage VS is also initially defined and equal to the body voltage VB. For example... Figure 4 As shown, the decrease in source voltage VS initially increases the transconductance of MP2, thereby increasing the current I_MP2 flowing through MP2. Current I_MP2 increases until it is high enough to drive both current sources IDC2 and IDC3 coupled to the load of transistor MP2, i.e., when the source voltage is sufficiently lower than the drain voltage. During this phase, VHS enters the LOW state and VHD enters the HIGH state. When VHD enters the HIGH state due to a sufficiently high drain voltage VD, MN2 couples VPB to ground, thereby pulling VPB to the LOW state. As mentioned above, a low VPB will cause transistor MPB to couple the source voltage to the load.

[0034] Therefore, the first current mirror circuit effectively reduces the impedance between the body voltage VB and the drain voltage VD, thereby coupling the drain voltage to both the body voltage and the load. Similar to the case where the source voltage VS increases, the same dual mechanism in the circuit affects the rapid coupling of the drain voltage to the load. Since transistor MP3 is also coupled to the drain voltage and has a constant current source as its load, the transconductance and gate-source voltage of MP3 increase in a similar manner to MP2, which again reduces the gate-source voltage at transistor MP4. As a result, the current source IDC2 at the load of transistor MP4 pulls VHS to a LOW state. This essentially occurs simultaneously with triggering VHD to a HIGH state. When voltage VHS is in a LOW state, transistors MN3 and MN4 are off, causing voltage VPA to increase towards the drain voltage, thereby disconnecting switch MPA and defining a high impedance between the source voltage and the body, thus effectively decoupling the source voltage from the body. Similarly, this dual effect provides rapid coupling capability for comparator circuits MPA and MPB.

[0035] Current sources IDC1 to IDC3 can be constant current generators configured to generate a constant current. In embodiments, each current source having the same reference numeral IDC1, IDC2, or IDC3 can be identical. Consequently, current source IDC1, as well as current sources IDC2 and IDC3, which serve as loads for transistors MP1 and MP3, can be identical to each other. (As described above...) Figure 3 and Figure 4 As described, current sources IDC2 and IDC3, which serve as loads for the current mirror circuit, are configured to generate non-zero hysteresis for the comparator switches. For example... Figure 4As shown, the source voltage VS needs to rise above the drain voltage VD by a first threshold amount to trigger state transitions in VHS and VHD and coupling from the source voltage to the body. Similarly, the source voltage needs to fall below the drain voltage VD by a second threshold amount to trigger state transitions in VHS and VHD and coupling from the drain voltage to the body. This is called hysteresis. As mentioned above, the first and second thresholds are actually defined by the configuration of current generators IDC2 and IDC3. When current generators IDC2 and IDC3 are identical, the first and second thresholds can have equal (absolute) values. In an implementation, constant current sources IDC2 and IDC3 are independently configured to generate a threshold voltage level for selecting the source voltage that is different from the threshold voltage level used to select the drain voltage. In this case, at least one of the current sources IDC2 and IDC3 at the load of transistor MP4 can generate a constant current different from at least one of the current sources IDC2 and IDC3 at the load of transistor MP2. In other words, IDC2 at the load of transistor MP4 can generate a different constant current than IDC2 at the load of transistor MP2, and / or IDC3 at the load of transistor MP4 can generate a different constant current than IDC3 at the load of transistor MP2.

[0036] In the implementation, the hysteresis voltage that defines the threshold voltage level and thus the first and second thresholds is defined as a function of the constant current IDC_3 generated by the current source IDC3, as follows:

[0037]

[0038] Where μC′ OX These are complementary MOS (CMOS) process parameters describing the mobility of transistors MP2 and MP4, L. MP2，4 It is the channel length of transistor MP2 and transistor MP4, and W MP2，4 This refers to the channel widths of transistors MP2 and MP4. Therefore, the hysteresis is defined by the current generated by current source IDC3 and the transconductance of transistors MP2 and MP4. Figure 5 The hysteresis effect is shown when current sources IDC2 and IDC3 are the same.

[0039] Reference Figure 5The hysteresis voltage can be concentrated near zero voltage, where the source voltage and threshold voltage are equal. Consider threshold level +1 / 2HYST as the threshold when the source voltage is about to be coupled to the body, and threshold level -1 / 2HYST as the threshold when the drain voltage is about to be coupled to the body. When the source voltage increases, causing it to increase the transconductance of transistor MP4 sufficiently to overcome the current generated at the load of transistor MP4 by current sources IDC2 and IDC3 together, VHS enters the HIGH state, causing the source voltage to couple to the body. When the source voltage VS decreases, the transconductance of MP4 decreases, and when it is low enough to generate a smaller current at the load of MP4 than current source IDC2, this helps to switch the drain voltage to the body. Transistor MP2 operates on the drain voltage in the same way. The current generated by current source(s) IDC1 can be defined as follows to achieve balanced hysteresis:

[0040]

[0041] According to any of the above embodiments, the first transistor, the second transistor, and the third transistor are positive metal-oxide-semiconductor (PMOS) transistors, and the device includes at least one additional PMOS transistor and at least one negative metal-oxide-semiconductor (NMOS) transistor, wherein the bodies of all PMOS transistors are coupled to the same body voltage, and wherein the bodies of all NMOS transistors are coupled to ground.

[0042] Current sources IDC1, IDC2, and IDC3 are active components that can be enabled or disabled. When the current sources are enabled, the comparator circuit operates as described above. However, the comparator circuit continues to operate even when the current sources are disabled. In this case, the current sources can be considered as high impedance. Transistors MN2 and MN3 are also in a high impedance state. As a result, voltage VPB is primarily coupled to the source voltage via the first impedance circuit (resistor RU1), while voltage VPA is primarily coupled to the drain voltage via the second impedance circuit (resistor RU2). Therefore, the comparator's function is essentially similar to... Figure 1 The circuitry has the following technical advantage: the body switch can still be performed, for example, during the startup phase of the comparator circuit when the current source is not yet fully activated. The advantage is that the body still follows either the source or drain voltage, which is always coupled to the body through the comparator circuitry.

[0043] In one embodiment, at least one of the first and second current mirror circuits includes a cascode amplifier with multiple current mirror circuits. In another embodiment, both the first and second current mirror circuits include a cascode amplifier with multiple current mirror circuits. The cascode amplifier improves the circuit's response time to changes in source and drain voltages, thereby improving the accuracy of the comparator and coupling. For example, if an extremely fast response to either the source or drain voltage is not required, the cascode amplifier is not necessary for either current mirror circuit. Figure 6 An implementation is shown in the case of a cascode amplifier where both current mirrors include current mirrors. For example... Figure 6 As shown, Figure 2 Each transistor MP1 to MP4 in the current mirror is part of a current mirror cascode amplifier. Transistors MP1 and MP2 are cascode-coupled with transistors MP1A and MP2A, respectively, while transistors MP3 and MP4 are cascode-coupled with transistors MP3A and MP4A, respectively. In this embodiment, the cascode transistors have the same type as PMOS transistors. Therefore, the drains of transistors MP1 to MP4 are coupled to the sources of transistors MP1A to MP4A, respectively. However, the gates of transistors MP1A and MP2A are coupled to VS1, which can be coupled to the power supply voltage domain of the source voltage VS, while the gates of transistors MP3A and MP4A are coupled to VS2, which can be coupled to the power supply voltage domain of the drain voltage VD. In some embodiments, the source voltage VS can be coupled directly or via a circuit such as an impedance circuit to the gates of transistors MP1A and MP2A. Similarly, the drain voltage VD can be coupled directly or via a circuit such as an impedance circuit to the gates of transistors MP3A and MP4A. The actual implementation of the circuit that provides bias for transistors MP1A through MP4A can be designed according to the desired implementation method, remembering to give the cascode amplifier sufficient operating margin. The operation of the circuit is basically similar to the combination of the above. Figure 3 and Figure 4 The described operation.

[0044] In some embodiments, the apparatus is or is included in a rectifier circuit or a charger device. The apparatus according to the embodiments described herein can be used to rectify alternating current or other mobile voltages to charge batteries, etc.

[0045] The embodiments described herein are applicable to the systems defined above, but also to other systems. Specifications for the protocols, systems, and components used are evolving rapidly. Such evolution may necessitate additional modifications to the described embodiments. Therefore, all words and expressions should be interpreted broadly, and they are intended to be illustrative rather than limiting. It will be apparent to those skilled in the art that the concepts of the invention can be implemented in various ways as technology advances. Embodiments are not limited to the examples described above, but may vary within the scope of the claims.

Claims

1. An apparatus including a circuit, comprising: A body-controlled switching circuit includes: a first transistor (MP0) coupled to a load and having a source coupled to a source voltage (VS) and a drain coupled to a drain voltage (VD); a second transistor (MPA) and a third transistor (MPB) connected in parallel with the first transistor (MP0) and in series with each other between the source voltage and the drain voltage, wherein the body of the first transistor is coupled to the bodies of the second transistor and the third transistor, wherein the gate of the second transistor is coupled to the source voltage via a first impedance circuit (RU1) and the gate of the third transistor is coupled to the drain voltage via a second impedance circuit (RU2), to form a comparator switch controlled by the source voltage and the drain voltage and dynamically switch the larger of the source voltage and the drain voltage to the load; First current generator circuit and second current generator circuit (IDC1); The first current mirror circuit (MP3, MP4), biased by the first current generator circuit and responsive to the source voltage, is configured to trigger the second transistor to couple the source voltage to the load when the source voltage is higher than the drain voltage. The second current mirror circuit (MP1, MP2), biased by the second current generator circuit and responsive to the drain voltage, is configured to: trigger the third transistor to couple the drain voltage to the load when the drain voltage is higher than the source voltage; and A constant current generator (IDC2, IDC3) serves as a load for the first current mirror circuit and the second current mirror circuit, and the constant current generator is configured to generate a non-zero hysteresis for the comparator switch.

2. The apparatus according to claim 1, wherein, The constant current generator is configured to generate a threshold voltage level for coupling the source voltage that is different from the threshold voltage level used for coupling the drain voltage.

3. The apparatus according to any of the preceding claims, wherein, The first impedance circuit includes a first resistor between the gate of the second transistor and the source voltage, and the second impedance circuit includes a second resistor between the gate of the third transistor and the drain voltage.

4. The apparatus according to claim 3, wherein, The first impedance circuit is grounded via a fourth transistor (MN2) and the second impedance circuit is grounded via a fifth transistor (MN3), wherein the second current mirror circuit is coupled to the gate of the fourth transistor and the first current mirror circuit is coupled to the gate of the fifth transistor.

5. The apparatus according to any one of claims 1 to 2, wherein, The first transistor, the second transistor, and the third transistor are positive metal-oxide-semiconductor (PMOS) transistors, and the device includes at least one additional PMOS transistor and at least one negative metal-oxide-semiconductor (NMOS) transistor, wherein the bodies of all PMOS transistors are coupled to the same body voltage, and wherein the bodies of all NMOS transistors are coupled to ground.

6. The apparatus according to claim 5, wherein, Both the first current mirror circuit and the second current mirror circuit include diode-coupled transistors (MP1, MP3) and current source transistors (MP2, MP4). The current source transistor (MP4) of the first current mirror circuit is coupled to the gate of a sixth transistor (MN4), which drives a constant current source (IDC3) that serves as the load of the current source transistor (MP2) of the second current mirror circuit. The current source transistor (MP2) of the second current mirror circuit is coupled to the gate of a seventh transistor (MN1), which drives a constant current source (IDC3) that serves as the load of the current source transistor (MP4) of the first current mirror circuit.

7. The apparatus according to any one of claims 1 to 2, wherein, The first current mirror circuit is configured to increase the coupling of the source voltage to the load in response to the source voltage rising above the drain voltage, and the second current mirror circuit is configured to increase the decoupling of the drain voltage to the load, wherein the second current mirror circuit is configured to increase the coupling of the drain voltage to the load in response to the drain voltage rising above the source voltage, and the first current mirror circuit is configured to increase the decoupling of the source voltage to the load.

8. The apparatus according to any one of claims 1 to 2, wherein, At least one of the first current mirror circuit and the second current mirror circuit includes a common-source cascode amplifier comprising multiple current mirror circuits.

9. A rectifier circuit comprising the means of any one of claims 1 to 2.

10. A charger device comprising the means according to any one of claims 1 to 2.

Images