Methods for encoding or decoding video parameter sets or sequence parameter sets

Abstract

This disclosure provides a computer-implemented video encoding method. The method includes: determining whether an encoded video sequence (CVS) contains an equal number of file, layer, and level (PTL) syntax structures and an output layer set (OLS); and encoding a bitstream in response to the CVS containing an equal number of PTL syntax structures and OLS, without signaling a first PTL syntax element, the first PTL syntax element assigning an index of a PTL syntax structure corresponding to an OLS in a video parameter set (VPS) to a list of PTL syntax structures in the VPS.

Description

[0001] Cross-references to related applications

[0002] This disclosure claims priority to U.S. Provisional Application No. 62 / 994,995, filed March 26, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to video processing, and more specifically, to a video processing method for signaling a video parameter set (VPS) and a sequence parameter set (SPS). Background Technology

[0004] Video is a set of still images (or "frames") that capture visual information. To reduce storage memory and transmission bandwidth, video can be compressed before storage or transmission and then decompressed before display. The compression process is usually called encoding, and the decompression process is usually called decoding. There are various video coding formats that use standardized video coding techniques, the most common being prediction, transform, quantization, entropy coding, and in-loop filtering. Standardization organizations have developed video coding standards, such as the High Efficiency Video Coding (HEVC / H.265) standard, the Universal Video Coding (VVC / H.266) standard, and the AVS standard, specifying particular video coding formats. As more and more advanced video coding techniques are adopted in video standards, the coding efficiency of new video coding standards is becoming increasingly higher. Summary of the Invention

[0005] Embodiments of this disclosure provide a computer-implemented video encoding method. In some embodiments, the method includes: determining whether an encoded video sequence (CVS) contains an equal number of file, layer, and level (PTL) syntax structures and output layer sets (OLS); and encoding a bitstream in response to the CVS containing an equal number of PTL syntax structures and OLS, without signaling a first PTL syntax element, the first PTL syntax element assigning an index of a PTL syntax structure corresponding to an OLS in a VPS to a list of PTL syntax structures in the VPS.

[0006] In some embodiments, the method includes: determining whether an encoded video sequence (CVS) has an equal number of decoded image buffer (DPB) parameter syntax structures and output layer sets (OLS); and encoding the bitstream in response to the CVS having an equal number of DPB parameter syntax structures and OLS, without signaling a first DPB syntax element that assigns an index of the DPB parameter syntax structure applied to the corresponding OLS to a list of DPB parameter syntax structures in the VPS.

[0007] In some embodiments, the method includes: determining whether at least one of a file, layer, and level (PTL) syntax structure, a decoded picture buffer (DPB) parameter syntax structure, or a hypothetical reference decoder (HRD) parameter syntax structure exists in a sequence parameter set (SPS) of a bitstream; determining whether a first value is greater than 1, the first value specifying the maximum number of temporal sublayers present in a coded layer video sequence (CLVS) of a reference SPS; and signaling a flag configured to control the presence of syntax elements in the DPB parameter syntax structure in the SPS when at least one of the PTL syntax structure, the DPB parameter syntax structure, or the HRD parameter syntax structure exists in the SPS and the first value is greater than 1.

[0008] In some embodiments, the method includes: determining a value of a first sequence parameter set (SPS) syntax element, the first SPS syntax element specifying an identifier of a video parameter set (VPS) referenced by the SPS when the value of the first SPS syntax element is greater than zero; in response to the value of the first SPS syntax element being greater than zero, allocating a range of a second SPS syntax element based on a corresponding VPS syntax element, the second SPS syntax element specifying a maximum number of temporal sublayers present in each coded layer video sequence (CLVS) referencing the SPS; and in response to the value of the first SPS syntax element being equal to zero, allocating the range of the second SPS syntax element as a closed interval from zero to a fixed value, the second SPS syntax element specifying the maximum number of temporal sublayers present in each CLVS referencing the SPS.

[0009] In some embodiments, the method includes: encoding one or more file, layer, and level (PTL) syntax elements that specify PTL-related information; and using variable-length signaling to notify the one or more PTL syntax elements in a video parameter set (VPS) or sequence parameter set (SPS) of a bitstream.

[0010] In some embodiments, the method includes: encoding a variable-length Video Parameter Set (VPS) syntax element; and signaling the VPS syntax element in a VPS that the VPS syntax element is associated with the number of Output Layer Sets (OLS) contained in a coded video sequence (CVS) of a reference VPS.

[0011] Embodiments of this disclosure provide a computer-implemented video decoding method. In some embodiments, the method includes: receiving a bitstream comprising an encoded video sequence (CVS); determining whether the CVS has the same number of file, layer, and level (PTL) syntax structures and output layer sets (OLS); and, in response to the number of PTL syntax structures being equal to the number of OLS, skipping the decoding of a first PTL syntax element, the first PTL syntax element being indexed to a list of PTL syntax structures in the VPS when decoding a VPS corresponding to an OLS.

[0012] In some embodiments, the method includes: receiving a bitstream including a encoded video sequence (CVS); determining whether the CVS has an equal number of decoded image buffer (DPB) parameter syntax structures and output layer sets (OLS); and, in response to the CVS having an equal number of DPB parameter syntax structures and OLS, skipping the decoding of a first DPB syntax element, the first DPB syntax element specifying the index of the DPB parameter syntax structure applied to the corresponding OLS to a list of DPB parameter syntax structures in the VPS.

[0013] In some embodiments, the method includes: receiving a bitstream including a Video Parameter Set (VPS) and a Sequence Parameter Set (SPS); in response to at least one of a File, Layer, and Type (PTL) syntax structure, a Decoded Picture Buffer (DPB) parameter syntax structure, or a Hypothetical Reference Decoder (HRD) parameter syntax structure present in the SPS, determining whether a first value is greater than 1, the first value specifying the maximum number of temporal sub-layers present in each coding layer video sequence (CLVS) referencing the SPS; and in response to the first value being greater than 1, decoding a flag configured to control the presence of syntax elements in the DPB parameter syntax structure in the SPS.

[0014] In some embodiments, the method includes: determining a value of a first sequence parameter set (SPS) syntax element, the first SPS syntax element specifying an identifier of a video parameter set (VPS) referenced by an SPS when the value of the first SPS syntax element is greater than zero; and decoding a second SPS syntax element specifying a maximum number of temporal sublayers present in each coding layer video sequence (CLVS) of the referenced SPS, wherein the range of the second SPS syntax element is based on a corresponding VPS syntax element of the VPS referenced by the SPS when the value of the first SPS syntax element is greater than zero, or the range of the second SPS syntax element is based on a fixed value when the value of the first SPS syntax element is equal to zero.

[0015] In some embodiments, the method includes: receiving a bitstream including a video parameter set (VPS) or a sequence parameter set (SPS); and decoding one or more file, layer, and level (PTL) syntax elements in the VPS or SPS, the one or more PTL syntax elements specifying PTL-related information.

[0016] In some embodiments, the method includes:

[0017] Receives a bitstream including a Video Parameter Set (VPS); and

[0018] VPS syntax elements in a VPS are decoded using a variable length, the VPS syntax elements being associated with the number of output layer sets (OLS) contained in a coded video sequence (CVS) referencing the VPS.

[0019] Embodiments of this disclosure provide an apparatus. In some embodiments, the apparatus includes: a memory configured to store instructions; and a processor coupled to the memory and configured to execute the instructions to perform a computer-implemented method for encoding video. In some embodiments, the apparatus includes: a memory configured to store instructions; and a processor coupled to the memory and configured to execute the instructions to perform a computer-implemented method for decoding video.

[0020] Embodiments of this disclosure provide a non-transitory computer-readable storage medium for storing a set of instructions that can be executed by one or more processors of a device to cause the device to perform a method for encoding video.

[0021] Embodiments of this disclosure provide a non-transitory computer-readable storage medium for storing a set of instructions that can be executed by one or more processors of a device to cause the device to perform a method for decoding video. Attached Figure Description

[0022] Embodiments and aspects of this disclosure are illustrated in the following detailed description and accompanying drawings. The various features shown in the figures are not drawn to scale.

[0023] Figure 1 This is a schematic diagram of the structure of an exemplary video sequence consistent with some embodiments of this disclosure.

[0024] Figure 2A This is a schematic diagram illustrating an exemplary encoding process of a hybrid video codec system consistent with some embodiments of this disclosure.

[0025] Figure 2B This is a schematic diagram illustrating another exemplary encoding process of a hybrid video codec system consistent with some embodiments of this disclosure.

[0026] Figure 3A This is a schematic diagram illustrating an exemplary decoding process of a hybrid video codec system consistent with some embodiments of this disclosure.

[0027] Figure 3B This is a schematic diagram illustrating another exemplary decoding process of a hybrid video codec system consistent with some embodiments of this disclosure.

[0028] Figure 4 This is a block diagram of an exemplary apparatus for encoding or decoding video, consistent with some embodiments of this disclosure.

[0029] Figure 5 This is a schematic diagram of an exemplary bitstream consistent with some embodiments of this disclosure.

[0030] Figure 6A An exemplary encoded syntax table is shown that is consistent with some embodiments of the present disclosure in terms of PTL syntax structure.

[0031] Figure 6B An exemplary encoded syntax table is shown that is consistent with some embodiments of the present disclosure regarding the DPB parameter syntax structure.

[0032] Figure 7A An exemplary encoded syntax table is shown that is consistent with some embodiments of the HRD parameter syntax structure of this disclosure.

[0033] Figure 7B Another exemplary encoded syntax table is shown that is consistent with some embodiments of the present disclosure regarding the HRD parameter syntax structure.

[0034] Figure 8 An exemplary encoded syntax table is shown as a portion of the VPS Raw Byte Sequence Payload (RBSP) syntax structure consistent with some embodiments of this disclosure.

[0035] Figure 9 An exemplary encoded syntax table is shown as a portion of an SPS RBSP syntax structure consistent with some embodiments of this disclosure.

[0036] Figure 10A A flowchart of an exemplary video encoding method according to some embodiments of the present disclosure is shown.

[0037] Figure 10B Some embodiments consistent with this disclosure are shown. Figure 10A The flowchart shows an exemplary video decoding method corresponding to the video encoding method.

[0038] Figure 10C A portion of an exemplary VPS syntax structure consistent with some embodiments of this disclosure is shown.

[0039] Figure 10D A portion of an exemplary VPS syntax structure consistent with some embodiments of this disclosure is shown.

[0040] Figure 11A A flowchart of an exemplary video encoding method according to some embodiments of the present disclosure is shown.

[0041] Figure 11B Some embodiments consistent with this disclosure are shown. Figure 11A The flowchart shows an exemplary video decoding method corresponding to the video encoding method.

[0042] Figure 11C A portion of an exemplary VPS syntax structure consistent with some embodiments of this disclosure is shown.

[0043] Figure 11D A portion of an exemplary VPS syntax structure consistent with some embodiments of this disclosure is shown.

[0044] Figure 12A A flowchart of an exemplary video encoding method consistent with some embodiments of this disclosure is shown.

[0045] Figure 12B Some embodiments consistent with this disclosure are shown. Figure 12A The flowchart shows an exemplary video decoding method corresponding to the video encoding method.

[0046] Figure 12C A portion of an exemplary SPS syntax structure consistent with some embodiments of this disclosure is shown. Detailed Implementation

[0047] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, wherein, unless otherwise stated, the same numerals in different drawings denote the same or similar elements. The embodiments set forth in the following description of the exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with aspects of this disclosure as described in the appended claims. Specific aspects of this disclosure are described below in more detail. In the event of any conflict with terms and / or definitions incorporated by reference, the terms and definitions provided herein shall prevail.

[0048] The Joint Video Experts Group (JVET) of the ITU-T Video Coding Experts Group (ITU-T VCEG) and the ISO / IEC Moving Picture Experts Group (ISO / IEC MPEG) is currently developing the Universal Video Coding (VVC / H.266) standard. The VVC standard aims to double the compression efficiency of its predecessor, the High Efficiency Video Coding (HEVC / H.265) standard. In other words, VVC aims to achieve the same subjective quality as HEVC / H.265 using half the bandwidth.

[0049] To achieve the same subjective quality as HEVC / H.265 using half the bandwidth, JVET has been developing techniques other than HEVC using the Joint Exploratory Model (JEM) reference software. With the incorporation of coding techniques into JEM, JEM achieves higher coding performance than HEVC.

[0050] The VVC standard is a recent development and continues to include more coding techniques that provide better compression performance. VVC is based on a hybrid video coding system that has been used in modern video compression standards such as HEVC, H.264 / AVC, MPEG2, and H.263.

[0051] Video is a set of still images (or “frames”) arranged in chronological order to store visual information. These images can be captured and stored in chronological order using video capture devices (e.g., cameras), and displayed in a time-series using video playback devices (e.g., televisions, computers, smartphones, tablets, video players, or any end-user terminal with a display capability). Furthermore, in some applications, video capture devices can transmit captured video in real time to video playback devices (e.g., computers with monitors), such as for surveillance, conferencing, or live broadcasting.

[0052] To reduce the storage space and transmission bandwidth required for such applications, video can be compressed before storage and transmission, and decompressed before display. Compression and decompression can be implemented by software executed by a processor (e.g., a processor in a general-purpose computer) or dedicated hardware. The module used for compression is typically called an "encoder," and the module used for decompression is typically called a "decoder." Encoders and decoders can be collectively referred to as a "codec." Encoders and decoders can be implemented as any of a variety of suitable hardware, software, or combinations thereof. For example, hardware implementations of encoders and decoders can include circuits such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, or any combination thereof. Software implementations of encoders and decoders can include program code embedded in a computer-readable medium, computer-executable instructions, firmware, or any suitable computer-implemented algorithm or process. Video compression and decompression can be implemented using various algorithms or standards, such as MPEG-1, MPEG-2, MPEG-4, the H.26x series, etc. In some applications, a codec can decompress video from a first encoding standard and recompress the decompressed video using a second encoding standard; in this case, the codec can be referred to as a "transcoder."

[0053] Video encoding processes identify and retain useful information that can be used to reconstruct the image, while ignoring unimportant reconstruction information. If ignoring unimportant information prevents complete reconstruction, such an encoding process can be called "lossy." Otherwise, it can be called "lossless." Most encoding processes are lossy, a trade-off to reduce required storage space and transmission bandwidth.

[0054] Useful information about an encoded image (referred to as the "current image") includes changes relative to a reference image (e.g., a previously encoded and reconstructed image). Such changes can include variations in pixel position, brightness, or color, with positional changes being the most important. The positional changes of a set of pixels representing an object can reflect the object's movement between the reference and current images.

[0055] An image encoded without referencing another image (i.e., it is its own reference image) is called an "I-image". An image encoded using a previous image as a reference image is called a "P-image", and an image encoded using both a previous image and a future image as reference images is called a "B-image" (the reference is "bidirectional").

[0056] Figure 1The structure of an example video sequence 100 according to some embodiments of the present disclosure is shown. The video sequence 100 may be live video or video that has been captured and archived. The video 100 may be real-life video, computer-generated video (e.g., computer game video), or a combination of both (e.g., real video with augmented reality effects). The video sequence 100 may be input from a video capture device (e.g., a camera), a video archive containing previously captured video (e.g., a video file stored on a storage device), or a video feed interface (e.g., a video broadcast transceiver) receiving video from a video content provider.

[0057] like Figure 1 As shown, video sequence 100 may include a series of images arranged temporally along a timeline, including images 102, 104, 106, and 108. Images 102-106 are consecutive, with more images between images 106 and 108. Figure 1 In this diagram, image 102 is an I-image, and its reference image is image 102 itself. Image 104 is a P-image, and its reference image is image 102, as indicated by the arrow. Image 106 is a B-image, and its reference images are images 104 and 108, as indicated by the arrow. In some embodiments, the reference image of an image (e.g., image 104) may not immediately precede or follow the image. For example, the reference image of image 104 may be an image preceding image 102. It should be noted that the reference images of images 102-106 are merely examples, and this disclosure does not limit the scope to such cases. Figure 1 An example of the reference image shown.

[0058] Typically, due to the computational complexity of encoding and decoding tasks, video codecs do not encode or decode the entire image at once. Instead, they can segment the image into basic segments and encode or decode each segment sequentially. In this disclosure, such basic segments are referred to as basic processing units (“BPUs”). For example, Figure 1Structure 110 illustrates an example structure of an image (e.g., any of images 102-108) from video sequence 100. In structure 110, the image is divided into 4×4 basic processing units, whose boundaries are shown as dashed lines. In some embodiments, the basic processing unit may be referred to as a “macroblock” in some video coding standards (e.g., MPEG family, H.261, H.263, or H.264 / AVC), or as a “coding tree unit” (“CTU”) in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing unit may have a variable size in the image, such as 128×128, 64×64, 32×32, 16×16, 4×8, 16×32, or pixels of any shape and size. The size and shape of the basic processing units for the image can be selected based on a balance between coding efficiency and the level of detail to be maintained within the basic processing unit. The CTU is the largest block unit and can contain up to 128 × 128 luma samples (plus corresponding chroma samples depending on the chroma format). The CTU can be further divided into coding units (CUs) using quadtrees, binary trees, ternary trees, or combinations thereof.

[0059] A basic processing unit can be a logical unit that may include a set of different types of video data stored in computer memory (e.g., in a video frame buffer). For example, a basic processing unit for a color image may include a luminance component (Y) representing achromatic luminance information, one or more chrominance components (e.g., Cb and Cr) representing color information, and associated syntax elements, where the luminance and chrominance components may have the same size as the basic processing unit. In some video coding standards (e.g., H.265 / HEVC or H.266 / VVC), the luminance and chrominance components may be referred to as “code tree blocks” (“CTBs”). Any operation performed on a basic processing unit may be performed repeatedly on each of its luminance and chrominance components.

[0060] Video encoding involves multiple operational stages, examples of which are as follows: Figure 2A-2B and Figures 3A-3BAs shown. For each stage, the size of the basic processing unit may still be too large for the processing, and therefore can be further divided into segments referred to herein as "basic processing subunits". In some embodiments, the basic processing subunit may be referred to as a "block" in some video coding standards (e.g., MPEG family, H.261, H.263, or H.264 / AVC), or as a "coding unit" ("CU") in some other video coding standards (e.g., H.265 / HEVC or H.266 / VVC). The basic processing subunit may have the same size as the basic processing unit or a smaller size. Similar to the basic processing unit, the basic processing subunit is also a logical unit that may include a set of different types of video data (e.g., Y, Cb, Cr, and associated syntax elements) stored in computer memory (e.g., in a video frame buffer). Any operation performed on the basic processing subunit may be repeated for each of its luminance and chrominance components. It should be noted that this division can be performed to further levels as needed for processing. It should also be noted that different schemes can be used to divide the basic processing units for different stages.

[0061] For example, in the pattern decision-making stage (examples of which are in...) Figure 2B As shown, the encoder can decide which prediction mode (e.g., intra-frame prediction or inter-frame prediction) to use for a basic processing unit, which may be too large to make such a decision. The encoder can divide the basic processing unit into multiple basic processing subunits (e.g., CUs in H.265 / HEVC or H.266 / VVC) and determine the prediction type for each individual basic processing subunit.

[0062] For another example, in the prediction phase (the example is in...) Figure 2A-2B As shown in the diagram, the encoder can perform prediction operations at the level of a basic processing subunit (e.g., a CU). However, in some cases, the basic processing subunit may still be too large to handle. The encoder can further divide the basic processing subunit into smaller segments (e.g., referred to as "prediction blocks" or "PBs" in H.265 / HEVC or H.266 / VVC) at which prediction operations can be performed.

[0063] For another example, in the transformation phase (the example of which is in...) Figure 2A-2BAs shown in the diagram, the encoder can perform transformation operations on residual basic processing subunits (e.g., CUs). However, in some cases, the basic processing subunits may still be too large to process. The encoder can further divide the basic processing subunits into smaller segments (e.g., referred to as "transform blocks" or "TBs" in H.265 / HEVC or H.266 / VVC), at which level transformation operations can be performed. It is important to note that the partitioning scheme of the same basic processing subunit can differ between the prediction and transformation phases. For example, in H.265 / HEVC or H.266 / VVC, the prediction blocks and transform blocks of the same CU can have different sizes and numbers.

[0064] exist Figure 1 In structure 110, the basic processing unit 112 is further divided into 3×3 basic processing sub-units, the boundaries of which are shown by dashed lines. Different basic processing units of the same image can be divided into basic processing sub-units in different schemes.

[0065] In some implementations, to provide parallel processing capabilities and fault tolerance for video encoding and decoding, an image can be divided into regions for processing, such that the encoding or decoding process for a given region of the image can be independent of information from any other region of the image. In other words, each region of the image can be processed independently. By doing so, the codec can process different regions of the image in parallel, thereby improving encoding efficiency. Furthermore, when data in one region is corrupted during processing or lost during network transmission, the codec can correctly encode or decode other regions of the same image without relying on the corrupted or lost data, thus providing fault tolerance. In some video coding standards, images can be divided into different types of regions. For example, H.265 / HEVC and H.266 / VVC provide two types of regions: “slices” and “tiles.” It should also be noted that different images in the video sequence 100 may have different partitioning schemes for dividing the image into regions.

[0066] For example, in Figure 1 In the diagram, structure 110 is divided into three regions 114, 116, and 118, whose boundaries are shown as solid lines within structure 110. Region 114 comprises four basic processing units. Regions 116 and 118 each comprise six basic processing units. It should be noted that... Figure 1 The basic processing unit, basic processing subunit, and structural region of 110 are merely examples, and this disclosure does not limit its embodiments.

[0067] Figure 2A A schematic diagram of an exemplary encoding process 200A according to an embodiment of the present disclosure is shown. For example, the encoding process 200A may be performed by an encoder. Figure 2AAs shown, the encoder can encode the video sequence 202 into a video bitstream 228 according to process 200A. Similar to... Figure 1 Video sequence 100 and video sequence 202 may include a set of images arranged in chronological order (referred to as "original images"). Similar to... Figure 1 In structure 110, each raw image of video sequence 202 can be divided into basic processing units, basic processing subunits, or regions by an encoder for processing. In some embodiments, the encoder can perform process 200A at the level of basic processing units for each raw image of video sequence 202. For example, the encoder can perform process 200A iteratively, wherein the encoder can encode basic processing units in one iteration of process 200A. In some embodiments, the encoder can perform process 200A in parallel for regions (e.g., regions 114-118) of each raw image of video sequence 202.

[0068] refer to Figure 2A The encoder feeds the basic processing unit (referred to as the "raw BPU") of the original image of video sequence 202 to prediction stage 204 to generate prediction data 206 and prediction BPU 208. The encoder can subtract the predicted BPU 208 from the raw BPU to generate residual BPU 210. The encoder can feed residual BPU 210 to transform stage 212 and quantization stage 214 to generate quantization transform coefficients 216. The encoder can feed prediction data 206 and quantization transform coefficients 216 to binary encoding stage 226 to generate video bitstream 228. Components 202, 204, 206, 208, 210, 212, 214, 216, 226, and 228 can be referred to as the "forward path". During process 200A, after quantization stage 214, the encoder can feed quantization transform coefficients 216 to inverse quantization stage 218 and inverse transform stage 220 to generate reconstructed residual BPU 222. The encoder can add the reconstructed residual BPU 222 to the predicted BPU 208 to generate a prediction reference 224, which is used in the prediction stage 204 of the next iteration of process 200A. Components 218, 220, 222, and 224 of process 200A can be referred to as the "reconstruction path". The reconstruction path can be used to ensure that both the encoder and decoder use the same reference data for prediction.

[0069] The encoder can iteratively execute process 200A to encode each raw BPU (in the forward path) of the original image and generate a prediction reference 224 for encoding the next raw BPU (in the reconstruction path) of the original image. After encoding all raw BPUs of the original image, the encoder can continue to encode the next image in the video sequence 202.

[0070] Referring to process 200A, the encoder may receive a video sequence 202 generated by a video acquisition device (e.g., a camera). As used herein, the term "receive" can refer to any action that receives, inputs, acquires, retrieves, obtains, reads, accesses, or is used for inputting data in any manner.

[0071] In prediction phase 204, during the current iteration, the encoder can receive the original BPU and prediction reference 224, and perform prediction operations to generate prediction data 206 and prediction BPU 208. Prediction reference 224 can be generated from the reconstruction path of previous iterations of process 200A. The purpose of prediction phase 204 is to reduce information redundancy by extracting prediction data 206 from prediction data 206 and prediction reference 224 that can be used to reconstruct the original BPU into prediction BPU 208.

[0072] Ideally, the predicted BPU 208 should be identical to the original BPU. However, due to non-ideal prediction and reconstruction operations, the predicted BPU 208 is typically slightly different from the original BPU. To record these differences, the encoder can subtract the predicted BPU 208 from the original BPU to generate the residual BPU 210. For example, the encoder can subtract the value of the corresponding pixel in the predicted BPU 208 (e.g., grayscale or RGB value) from the pixel value of the original BPU. Each pixel in the residual BPU 210 can have a residual value as the result of this subtraction between the corresponding pixel in the original BPU and the predicted BPU 208. Compared to the original BPU, the predicted data 206 and the residual BPU 210 can have fewer bits, but they can be used to reconstruct the original BPU without a significant quality degradation. Thus, the original BPU is compressed.

[0073] To further compress the residual BPU 210, in the transform stage 212, the encoder can reduce its spatial redundancy by decomposing the residual BPU 210 into a set of two-dimensional “base patterns”. Each base pattern is associated with “transform coefficients”. The base patterns can have the same size (e.g., the size of the residual BPU 210), and each base pattern can represent the frequency (e.g., the frequency of brightness variation) component of the residual BPU 210. None of the base patterns can be reproduced from any combination (e.g., a linear combination) of any other base patterns. In other words, the decomposition decomposes the variation of the residual BPU 210 into the frequency domain. This decomposition is analogous to the discrete Fourier transform of a function, where the base patterns are analogous to the base functions of the discrete Fourier transform (e.g., trigonometric functions), and the transform coefficients are analogous to the coefficients associated with the base functions.

[0074] Different transform algorithms can use different base patterns. Various transform algorithms, such as discrete cosine transform, discrete sine transform, etc., can be used in transform stage 212. The transform at transform stage 212 is reversible. That is, the encoder can recover the residual BPU 210 through the inverse operation of the transform (called the "inverse transform"). For example, to recover the pixels of the residual BPU 210, the inverse transform can be to multiply the values ​​of the corresponding pixels of the base pattern by the corresponding correlation coefficients and sum the products to produce a weighted sum. For video coding standards, both the encoder and decoder can use the same transform algorithm (and therefore have the same base pattern). Therefore, the encoder can only record the transform coefficients, from which the decoder can reconstruct the residual BPU 210 without receiving the base pattern from the encoder. Compared to the residual BPU 210, the transform coefficients can have fewer bits, but they can be used to reconstruct the residual BPU 210 without significant quality degradation. Therefore, the residual BPU 210 is further compressed.

[0075] The encoder can further compress the transform coefficients during the quantization stage 214. During the transform process, different fundamental patterns can represent different frequencies of change (e.g., brightness change frequencies). Because the human eye is generally better at recognizing low-frequency changes, the encoder can ignore information about high-frequency changes without causing significant quality degradation in decoding. For example, in the quantization stage 214, the encoder can generate quantized transform coefficients 216 by dividing each transform coefficient by an integer value (called the “quantization parameter”) and rounding the quotient to its nearest integer. After such an operation, some transform coefficients of the high-frequency fundamental patterns can be converted to zero, and the transform coefficients of the low-frequency fundamental patterns can be converted to smaller integers. The encoder can ignore the zero-valued quantized transform coefficients 216, thus further compressing the transform coefficients. This quantization process is also reversible, where the quantized transform coefficients 216 can be reconstructed into transform coefficients in the inverse operation of quantization (called “inverse quantization”).

[0076] Because the encoder ignores the remainder of the division during rounding, quantization stage 214 can be lossy. Typically, quantization stage 214 contributes the most to information loss in process 200A. The greater the information loss, the fewer bits are required for the quantization transform coefficients 216. To obtain different levels of information loss, the encoder can use different quantization parameter values ​​or any other parameter of the quantization process.

[0077] In the binary encoding stage 226, the encoder can encode the prediction data 206 and the quantization transform coefficients 216 using binary encoding techniques, such as entropy coding, variable-length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or any other lossless or lossy compression algorithm. In some embodiments, in addition to the prediction data 206 and the quantization transform coefficients 216, the encoder can encode other information in the binary encoding stage 226, such as the prediction mode used in the prediction stage 204, the parameters of the prediction operation, the transform type at the transform stage 212, the parameters of the quantization process (e.g., quantization parameters), encoder control parameters (e.g., bit rate control parameters), etc. The encoder can use the output data of the binary encoding stage 226 to generate a video bitstream 228. In some embodiments, the video bitstream 228 can be further packaged for network transmission.

[0078] Following the reconstruction path of process 200A, in the inverse quantization stage 218, the encoder can perform inverse quantization on the quantized transform coefficients 216 to generate reconstructed transform coefficients. In the inverse transform stage 220, the encoder can generate a reconstruction residual BPU 222 based on the reconstructed transform coefficients. The encoder can add the reconstruction residual BPU 222 to the prediction BPU 208 to generate a prediction reference 224 that will be used in the next iteration of process 200A.

[0079] It should be noted that other variations of process 200A can be used to encode video sequence 202. In some embodiments, the stages of process 200A may be performed by the encoder in different orders. In some embodiments, one or more stages of process 200A may be combined into a single stage. In some embodiments, a single stage of process 200A may be divided into multiple stages. For example, transform stage 212 and quantization stage 214 may be combined into a single stage. In some embodiments, process 200A may include additional stages. In some embodiments, process 200A may be omitted. Figure 2A One or more stages in the process.

[0080] Figure 2B A schematic diagram of another example encoding process 200B according to an embodiment of the present disclosure is shown. Process 200B can be modified from process 200A. For example, process 200B can be used by an encoder conforming to a hybrid video coding standard (e.g., H.26x series). Compared to process 200A, the forward path of process 200B further includes a mode decision stage 230, and divides the prediction stage 204 into a spatial prediction stage 2042 and a temporal prediction stage 2044. The reconstruction path of process 200B also additionally includes a loop filtering stage 232 and a buffer 234.

[0081] Generally, prediction techniques can be categorized into two types: spatial prediction and temporal prediction. Spatial prediction (e.g., intra-frame image prediction or "intra-prediction") uses pixels from one or more already encoded neighboring BPUs in the same image to predict the current BPU. That is, the prediction reference 224 in spatial prediction can include neighboring BPUs. Spatial prediction can reduce the inherent spatial redundancy of images. Temporal prediction (e.g., inter-image prediction or "inter-frame prediction") uses regions from one or more already encoded images to predict the current BPU. That is, the prediction reference 224 in temporal prediction can include encoded images. Temporal prediction can reduce the inherent temporal redundancy of images.

[0082] In reference process 200B, during the forward path, the encoder performs prediction operations in spatial prediction phase 2042 and temporal prediction phase 2044. For example, in spatial prediction phase 2042, the encoder may perform intra-frame prediction. For the original BPU of the encoded image, prediction reference 224 may include one or more adjacent BPUs that have been encoded (in the forward path) and reconstructed (in the reconstruction path) in the same image. The encoder can generate the predicted BPU 208 by interpolating adjacent BPUs. Interpolation techniques may include, for example, linear interpolation or interpolation, polynomial interpolation or interpolation, etc. In some embodiments, the encoder may perform interpolation at the pixel level, for example, by interpolating to predict the value of the corresponding pixel for each pixel of BPU 208. The adjacent BPUs used for interpolation may be located in various directions relative to the original BPU, such as in the vertical direction (e.g., at the top of the original BPU), the horizontal direction (e.g., to the left of the original BPU), the diagonal direction (e.g., at the lower left, lower right, upper left, or upper right of the original BPU), or any direction defined in the video coding standard used. For intra-frame prediction, prediction data 206 may include, for example, the location (e.g., coordinates) of the neighboring BPUs used, the size of the neighboring BPUs used, the interpolation parameters, the orientation of the neighboring BPUs used relative to the original BPU, etc.

[0083] In another example, during the temporal prediction phase 2044, the encoder can perform inter-frame prediction. For the original BPU of the current image, the prediction reference 224 can include one or more images (referred to as "reference images") that have been encoded (in the forward path) and reconstructed (in the reconstruction path). In some embodiments, the reference images can be encoded and reconstructed on a BPU-by-BPU basis. For example, the encoder can add the reconstructed residual BPU 222 to the prediction BPU 208 to generate a reconstructed BPU. When all reconstructed BPUs for the same image have been generated, the encoder can generate a reconstructed image as the reference image. The encoder can perform a "motion estimation" operation to search for matching regions within the range of the reference image (referred to as a "search window"). The position of the search window in the reference image can be determined based on the position of the original BPU in the current image. For example, the search window can be centered at a location in the reference image that has the same coordinates as the original BPU in the current image and can extend outward by a predetermined distance. When the encoder identifies a region in the search window that resembles the original BPU (e.g., by using a PEL recursive algorithm, a block matching algorithm, etc.), the encoder can determine such a region as a matching region. The matching region can have a different size than the original BPU (e.g., less than, equal to, greater than, or with a different shape). This is because the reference image and the current image are temporally separated on the timeline (e.g., as...). Figure 1 As shown in the image, the matching region can be considered to have "moved" to the original BPU's location over time. The encoder can record the direction and distance of this movement as a "motion vector." When using multiple reference images (e.g., such as...), Figure 1 In image 106, the encoder can search for matching regions and determine the associated motion vector for each reference image. In some embodiments, the encoder can assign weights to the pixel values ​​of the matching regions of each matching reference image.

[0084] Motion estimation can be used to identify various types of motion, such as translation, rotation, scaling, etc. For inter-frame prediction, prediction data 206 may include, for example, the location (e.g., coordinates) of the matching region, the motion vector associated with the matching region, the number of reference images, the weights associated with the reference images, etc.

[0085] To generate the predicted BPU 208, the encoder can perform a "motion compensation" operation. Motion compensation can be used to reconstruct the predicted BPU 208 based on the predicted data 206 (e.g., motion vectors) and the predicted reference 224. For example, the encoder can move a matching region of the reference image according to the motion vectors, where the encoder can predict the original BPU of the current image. When using multiple reference images (e.g., such as...), Figure 1In image 106), the encoder can move the matching region of the reference image based on the individual motion vectors and average pixel values ​​of the matching region. In some embodiments, if the encoder has already assigned weights to the pixel values ​​of the matching regions of the respective matching reference images, the encoder can add the weighted sums of the pixel values ​​of the moved matching regions.

[0086] In some embodiments, inter-frame prediction can be unidirectional or bidirectional. Unidirectional inter-frame prediction can use one or more reference images in the same temporal direction relative to the current image. For example, Figure 1 Image 104 in the image is a one-way inter-frame prediction image, where the reference image (i.e., image 102) precedes image 104. Two-way inter-frame prediction can use one or more reference images in two temporal directions relative to the current image. For example, Figure 1 Image 106 in the image is a bidirectional inter-frame prediction image, in which the reference image (i.e., images 104 and 08) is relative to image 104 in two temporal directions.

[0087] Referring again to the forward path of process 200B, after spatial prediction 2042 and temporal prediction stages 2044, in the mode decision stage 230, the encoder can select a prediction mode (e.g., one of intra-frame prediction or inter-frame prediction) for the current iteration of process 200B. For example, the encoder can perform a rate distortion optimization technique, whereby the encoder selects a prediction mode based on the bit rate of the candidate prediction modes and the distortion of the reconstructed reference image under the candidate prediction modes to minimize the value of the cost function. Based on the selected prediction mode, the encoder can generate the corresponding prediction BPU 208 and prediction data 206.

[0088] In the reconstruction path of process 200B, if intra-frame prediction mode has been selected in the forward path, the encoder can directly feed prediction reference 224 (e.g., the current BPU that has been encoded and reconstructed in the current image) to spatial prediction stage 2042 for later use (e.g., for interpolating the next BPU of the current image) after generating prediction reference 224. If inter-frame prediction mode has been selected in the forward path, the encoder can feed prediction reference 224 (e.g., the current image where all BPUs have been encoded and reconstructed) to loop filter stage 232 after generating prediction reference 224. In this stage, the encoder can apply loop filters to prediction reference 224 to reduce or eliminate distortions introduced by inter-frame prediction (e.g., block artifacts). The encoder can apply various loop filter techniques at loop filter stage 232, such as deblocking, adaptive sampling compensation, adaptive loop filtering, etc. The loop-filtered reference image can be stored in buffer 234 (or "decoded image buffer") for later use (e.g., as an inter-frame prediction reference image for future images of video sequence 202). The encoder can store one or more reference images in buffer 234 for use at temporal prediction stage 2044. In some embodiments, the encoder can encode parameters of the loop filter (e.g., loop filter strength) as well as quantization transform coefficients 216, prediction data 206, and other information at binary encoding stage 226.

[0089] Figure 3A A schematic diagram of an exemplary decoding process 300A according to an embodiment of the present disclosure is shown. Process 300A may be corresponding to Figure 2A The compression process 200A in the video stream is followed by the decompression process. In some embodiments, process 300A can be similar to the reconstruction path of process 200A. The decoder can decode the video bitstream 228 into video stream 304 according to process 300A. Video stream 304 can be very similar to video sequence 202. However, due to information loss during compression and decompression (e.g., Figure 2A-2B In the quantization stage 214), the video stream 304 is typically different from the video sequence 202. Similar to... Figure 2A-2B In processes 200A and 200B, the decoder can perform process 300A at the basic processing unit (BPU) level for each image encoded in the video bitstream 228. For example, the decoder can perform process 300A iteratively, where the decoder can decode the basic processing unit in one iteration of process 300A. In some embodiments, the decoder can perform process 300A in parallel for a region (e.g., region 114-118) of each image encoded in the video bitstream 228.

[0090] like Figure 3AAs shown, the decoder can feed a portion of the video bitstream 228 associated with a basic processing unit (referred to as the "encoded BPU") of the encoded image to a binary decoding stage 302, where the decoder can decode this portion into prediction data 206 and quantization transform coefficients 216. The decoder can feed the quantization transform coefficients 216 to an inverse quantization stage 218 and an inverse transform stage 220 to generate a reconstruction residual BPU 222. The decoder can feed the prediction data 206 to a prediction stage 204 to generate a prediction BPU 208. The decoder can add the reconstruction residual BPU 222 to the prediction BPU 208 to generate a prediction reference 224. In some embodiments, the prediction reference 224 can be stored in a buffer (e.g., a decoded image buffer in computer memory). The decoder can feed the prediction reference 224 to the prediction stage 204 for performing a prediction operation in the next iteration of process 300A.

[0091] The decoder can iteratively execute process 300A to decode each encoded BPU of the encoded image and generate a prediction reference 224 for the next encoded BPU of the encoded image. After decoding all encoded BPUs of the encoded image, the decoder can output the image to video stream 304 for display and continue decoding the next encoded image in video bit stream 228.

[0092] In the binary decoding stage 302, the decoder can perform the inverse operation of the binary encoding technique used by the encoder (e.g., entropy coding, variable-length coding, arithmetic coding, Huffman coding, context-adaptive binary arithmetic coding, or any other lossless compression algorithm). In some embodiments, in addition to the prediction data 206 and the quantized transform coefficients 216, the decoder can decode other information in the binary decoding stage 302, such as the prediction mode, parameters of the prediction operation, transform type, parameters of the quantization process (e.g., quantization parameters), encoder control parameters (e.g., bit rate control parameters), etc. In some embodiments, if the video bitstream 228 is transmitted over a network in packets, the decoder can unpack it before feeding the video bitstream 228 to the binary decoding stage 302.

[0093] Figure 3B A schematic diagram of another example decoding process 300B according to an embodiment of the present disclosure is shown. Process 300B can be modified from process 300A. For example, process 300B can be used by a decoder conforming to a hybrid video coding standard (e.g., H.26x series). Compared to process 300A, process 300B additionally divides the prediction stage 204 into a spatial prediction stage 2042 and a temporal prediction stage 2044, and additionally includes a loop filtering stage 232 and a buffer 234.

[0094] In process 300B, for the encoding basic processing unit (referred to as the "current BPU") of the decoded encoded image (referred to as the "current image"), the prediction data 206 decoded by the decoder from the binary decoding stage 302 can include various types of data depending on the prediction mode used by the encoder to encode the current BPU. For example, if the encoder uses intra-frame prediction to encode the current BPU, the prediction data 206 can include prediction mode indicators (e.g., flag values) that indicate intra-frame prediction, parameters of the intra-frame prediction operation, etc. Parameters of the intra-frame prediction operation can include, for example, the positions (e.g., coordinates) of one or more neighboring BPUs used as references, the sizes of neighboring BPUs, interpolation parameters, the orientation of neighboring BPUs relative to the original BPU, etc. For another example, if the current BPU is encoded by inter-frame prediction used by the encoder, the prediction data 206 can include prediction mode indicators (e.g., flag values) that indicate inter-frame prediction, parameters of the inter-frame prediction operation, etc. The parameters of the inter-frame prediction operation may include, for example, the number of reference images associated with the current BPU, the weights associated with the reference images respectively, the positions (e.g., coordinates) of one or more matching regions in the corresponding reference images, and one or more motion vectors associated with the matching regions respectively.

[0095] Based on the prediction mode indicator, the decoder can decide whether to perform spatial prediction (e.g., intra-frame prediction) in the spatial prediction phase 2042 or temporal prediction (e.g., inter-frame prediction) in the temporal prediction phase 2044. The details of performing this spatial or temporal prediction are... Figure 2B As described herein, it will not be repeated below. After performing such spatial or temporal prediction, the decoder can generate a predicted BPU 208, which can be added to the predicted BPU 208 and the reconstructed residual BPU 222 to generate a prediction reference 224, as shown below. Figure 3A As described in [the text].

[0096] In process 300B, the decoder can feed prediction reference 224 to either spatial prediction stage 2042 or temporal prediction stage 2044 for performing prediction operations in the next iteration of process 300B. For example, if intra-frame prediction is used to decode the current BPU in spatial prediction stage 2042, the decoder can feed prediction reference 224 directly to spatial prediction stage 2042 for later use (e.g., for interpolating the next BPU of the current image) after generating prediction reference 224 (e.g., the decoded current BPU). If inter-frame prediction is used to decode the current BPU in temporal prediction stage 2044, the encoder can feed prediction reference 224 to loop filter stage 232 to reduce or eliminate distortion (e.g., block artifacts) after generating prediction reference 224 (e.g., a reference image where all BPUs are decoded). The decoder can, as follows: Figure 2BThe loop filter is applied to prediction reference 224 in the manner shown. The loop-filtered reference image can be stored in buffer 234 (e.g., a decoded image buffer in computer memory) for later use (e.g., as an inter-prediction reference image for future encoded images of video bitstream 228). The decoder can store one or more reference images in buffer 234 for use at temporal prediction stage 2044. In some embodiments, the prediction data can further include parameters of the loop filter (e.g., loop filter strength) when the prediction mode indicator of prediction data 206 indicates that inter-frame prediction is used to encode the current BPU. The reconstructed image from buffer 234 can also be sent to a display, such as a TV, PC, smartphone, or tablet, for viewing by an end user.

[0097] Figure 4 This is a block diagram of an example apparatus 400 for encoding or decoding video according to embodiments of the present disclosure. Figure 4 As shown, device 400 may include processor 402. When processor 402 executes the instructions described herein, device 400 may become a dedicated machine for video encoding or decoding. Processor 402 may be any type of circuit capable of manipulating or processing information. For example, processor 402 may include any number of central processing units (or “CPU”), graphics processing units (or “GPU”), neural processing units (“NPU”), microcontroller units (“MCU”), optical processors, programmable logic controllers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), general-purpose array logic (GALs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), application-specific integrated circuits (ASICs), and any combination thereof. In some embodiments, processor 402 may also be a group of processors grouped into individual logic components. For example, such as Figure 4 As shown, processor 402 may include multiple processors, including processor 402a, processor 402b and processor 402n.

[0098] The device 400 may also include a memory 404 configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, such as Figure 4As shown, the stored data may include program instructions (e.g., for implementing stages in processes 200A, 200B, 300A, or 300B) and data for processing (e.g., video sequence 202, video bitstream 228, or video stream 304). Processor 402 can access the program instructions and data for processing (e.g., via bus 410) and execute the program instructions to perform operations or manipulations on the data for processing. Memory 404 may include a high-speed random access memory device or a non-volatile memory device. In some embodiments, memory 404 may include any combination of any number of random access memories (RAM), read-only memories (ROM), optical discs, magnetic disks, hard disks, solid-state drives, flash drives, secure digital cards (SD cards), memory sticks, compact flash memory (CF cards), etc. Memory 404 may also be a group of memories grouped into single logical components. Figure 4 (Not shown in the image).

[0099] Bus 410 may be a communication device for transmitting data between components within device 400, such as an internal bus (e.g., CPU-memory bus), an external bus (e.g., a Universal Serial Bus port, a Peripheral Component Interconnect Fast Port), or the like.

[0100] For ease of explanation and to avoid ambiguity, the processor 402 and other data processing circuitry are collectively referred to as "data processing circuitry" in this disclosure. The data processing circuitry may be implemented entirely in hardware, or as a combination of software, hardware, or firmware. Furthermore, the data processing circuitry may be a single, separate module, or may be wholly or partially integrated into any other component of the device 400.

[0101] The device 400 may also include a network interface 406 to provide wired or wireless communication with a network (e.g., the Internet, intranet, local area network, mobile communication network, etc.). In some embodiments, the network interface 406 may include any combination of any number of network interface controllers (NICs), radio frequency (RF) modules, transceivers, transceivers, modems, routers, gateways, wired network adapters, wireless network adapters, Bluetooth adapters, infrared adapters, near field communication (“NFC”) adapters, cellular network chips, etc.

[0102] In some embodiments, optionally, the device 400 may further include a peripheral interface 408 to provide connectivity to one or more peripheral devices. Figure 4 As shown, peripheral devices may include, but are not limited to, cursor control devices (e.g., mouse, touchpad, or touchscreen), keyboards, displays (e.g., cathode ray tube displays, liquid crystal displays, or light-emitting diode displays), video input devices (e.g., cameras or input interfaces coupled to video files), etc.

[0103] It should be noted that the video codec (e.g., the codec for executing processes 200A, 200B, 300A, or 300B) can be implemented as any combination of any software or hardware modules in device 400. For example, some or all stages of processes 200A, 200B, 300A, or 300B can be implemented as one or more software modules of device 400, such as program instances that can be loaded into memory 404. As another example, some or all stages of processes 200A, 200B, 300A, or 300B can be implemented as one or more hardware modules of device 400, such as dedicated data processing circuitry (e.g., FPGA, ASIC, NPU, etc.).

[0104] Figure 5 This is a schematic diagram of an example bit stream 500 encoded by an encoder according to some embodiments of the present disclosure. In some embodiments, the structure of the bit stream 500 can be applied to... Figure 2A-2B and Figures 3A-3B The video bitstream shown is 228. Figure 5 In this context, bitstream 500 includes a Video Parameter Set (VPS) 510, a Sequence Parameter Set (SPS) 520, a Picture Parameter Set (PPS) 530, a picture header 540, and stripes 550-570, which are separated by synchronization markers M1-M7. Each stripe 550-570 includes a corresponding header block (e.g., header 552) and a data block (e.g., data 554), and each data block includes one or more CTUs (e.g., CTU1-CTUn in data 554).

[0105] According to some embodiments, bitstream 500 is a sequence of bits in the form of Network Abstraction Layer (NAL) units or a byte stream, forming one or more coded video sequences (CVS). A CVS includes one or more coded layer video sequences (CLVS). In some embodiments, a CLVS is a sequence of picture units (PUs), and each PU contains a coded picture. Specifically, a PU includes zero or one picture header NAL unit (e.g., picture header 540) containing a picture header syntax structure as a payload, a coded picture including one or more video coding layer (VCL) NAL units, and optionally, one or more other non-VCL NAL units. A VCL NAL unit is a collective term for a subset of coded stripe NAL units (e.g., stripes 550-570) and NAL units having reserved values ​​of NAL unit types classified as VCL NAL units in some embodiments. A coded stripe NAL unit contains a stripe header and stripe data blocks (e.g., header 552 and data 554).

[0106] In other words, in some embodiments of this disclosure, a layer can be a set of Video Coding Layer (VCL) NAL units with a specific value for the NAL layer ID and associated non-VCL NAL units. Inter-layer prediction can be applied between different layers within these layers to achieve high compression performance.

[0107] In some embodiments, an Output Layer Set (OLS) can be specified to support decoding some, but not all, of the layers. An OLS is a set of layers that includes a specified set of layers, where one or more layers in that set are designated as output layers. Therefore, an OLS can contain one or more output layers, as well as other layers required to decode those output layers for inter-layer prediction.

[0108] In some embodiments, "profile," "tier," and "level" (collectively referred to as "PTL") are used to specify constraints on the bitstream, and thus on the capabilities required to decode the bitstream. Profiles, tiers, and levels can also be used to indicate interoperability points between various decoder implementations. A "profile" is a subset of the bitstream syntax and specifies a subset of algorithmic features and constraints that can be supported by a decoder conforming to that profile. Within the range imposed by the syntax of a given profile, performance variations may be required for both the encoder and decoder, depending on the values ​​adopted by the syntax elements in the bitstream, such as the specified size of the decoded image. In some applications, implementing a decoder capable of handling all hypothetical scenarios using the syntax within a specific profile may be neither practical nor economical.

[0109] In addition, "layers" and "levels" are specified in each file. A layer level is a set of specified constraints imposed on the values ​​of syntax elements in the bitstream. These constraints may be simple restrictions on the values. Alternatively, they may take the form of constraints on arithmetic combinations of values ​​(e.g., image width multiplied by image height multiplied by the number of images decoded per second). In some embodiments, the same set of layer and level definitions is used across all files. Some implementations may support different layers and different levels within each layer for each supported file. For a given profile, the level of a layer typically corresponds to the specific decoder's processing load and memory capacity. Levels specified for lower layers may be subject to more constraints than levels specified for higher layers.

[0110] Figure 6AAn exemplary encoded syntax table, in bold and highlighted, of a PTL syntax structure 600A that is signaled in a VPS or SPS, consistent with some embodiments of this disclosure, is shown. In some embodiments, PTL-related information for each operation point, identified by parameters TargetOlsIdx and Htid, can be indicated by parameters 610A and 620A (e.g., general_profile_idc and general_tier_flag) in the PTL syntax structure 600A and by parameter 630A (e.g., sublayer_level_idc[Htid]) found in or derived from the PTL syntax structure, which is signaled in a Video Parameter Set (VPS) or Sequence Parameter Set (SPS). TargetOlsIdx is a variable used to identify the OLS index of the target OLS to be decoded, and Htid is a variable used to identify the highest temporal sublayer to be decoded.

[0111] As described in the preceding paragraphs, the Decoded Image Buffer (DPB) contains image storage buffers for storing decoded images. Each image storage buffer may contain decoded images marked "for reference" or reserved for future output. In some embodiments, starting from the lowest layer in the OLS, procedures are applied sequentially and individually to each layer in ascending order of the nuh_layer_id values ​​in the OLS, where nuh_layer_id is a parameter specifying the identifier of the layer to which the VCL NAL unit belongs or the identifier of the layer to which a non-VCL NAL unit applies. In some embodiments, the value of nuh_layer_id should be the same for the encoded image or the VCL NAL unit of the PU. These procedures include the process of outputting and removing images from the DPB before decoding the current image, the process of marking and storing the current decoded image, and the process of applying collisions.

[0112] Figure 6B An exemplary encoded syntax table, highlighted in bold, is shown that is consistent with some embodiments of this disclosure, representing the DPB parameter syntax structure 600B that is signaled in a VPS or SPS. For example... Figure 6B As shown, DPB parameters 610B, 620B, and 630B (which are required to apply the above procedures and check the consistency of the bit stream) can be found in or derived from the DPB parameter syntax structure 600B, which is signaled in the VPS or SPS. These parameters may include...

[0113] max_dec_pic_buffering_minus1[Htid], max_num_reorder_pics[Htid] and

[0114] MaxLatencyPictures[Htid]).

[0115] In some embodiments, parameter 610B (e.g., max_dec_pic_buffering_minus1[i]) plus 1 specifies the maximum required size of the DPB in units of image storage buffers for an index i with Htid equal to 0. The value of parameter 610B can be in the closed range of 0 to MaxDpbSize-1. MaxDpbSize is a parameter that specifies the maximum size of the decoded image buffer in units of image storage buffers. When index i is greater than 0, max_dec_pic_buffering_minus1[i] should be greater than or equal to max_dec_pic_buffering_minus1[i − 1]. When max_dec_pic_buffering_minus1[i] does not exist for an index i in the closed range of 0 to SubLayersMinus1-1, parameter 610B is inferred to be equal to max_dec_pic_buffering_minus1[maxSubLayersMinus1].

[0116] Parameter 620B (e.g., max_num_reorder_pics[i]) specifies the maximum number of images allowed for an OLS with Htid equal to index i, which can precede any image in the OLS in decoding order and follow any image in output order. The value of parameter 620B can be in the closed interval from 0 to max_dec_pic_buffering_minus1[i]. When index i is greater than 0, parameter 620B can be greater than or equal to max_num_reorder_pics[i − 1]. For index i in the closed interval from 0 to maxSubLayersMinus1 minus 1, when parameter 620B is not present, parameter 620B is inferred to be equal to max_num_reorder_pics[maxSubLayersMinus1] since subLayerInfoFlag is equal to 0.

[0117] The parameter 630B is used to calculate the value of MaxLatencyPictures[i], which specifies the maximum number of pictures in the OLS for which Htid equals index i, which can precede any picture in the OLS in output order and follow any picture in decoding order. When parameter 630B is equal to zero, no corresponding limit is indicated. When parameter 630B is not equal to 0, the value of MaxLatencyPictures[i] can be determined according to the following formula:

[0118] MaxLatencyPictures[i] = max_num_reorder_pics[i]+ max_latency_increase_plus1[i] − 1

[0119] (Formula 1)

[0120] The value of parameter 630B can be between 0 and 2. 32 Within the closed interval of −2. When index i is within the closed interval of maxSubLayersMinus1 minus 1, and parameter 630B does not exist, since subLayerInfoFlag is equal to 0, parameter 630B is inferred to be equal to max_latency_increase_plus1[maxSubLayersMinus1].

[0121] The hypothetical reference decoder (HRD) is a hypothetical decoder model that specifies the constraints on the variability of the encoding process, which may produce NAL unit streams or byte streams, and can be used to check the consistency of the bit stream and decoder. Both types of bit streams or subsets of bit streams are subject to VVC HRD consistency checks. The first type, called Type I bit stream, is a NAL unit stream containing multiple VCL NAL units, and the nal_unit_type of the multiple NAL unit stream is equal to the padding data NAL units (FD_NUT) of all access units (AUs) in the bit stream. The second type, called Type II bit stream, contains, in addition to the VCL NAL units and padding data NAL units of all AUs in the bit stream, at least one of the following: (1) other non-VCL NAL units besides padding data NAL units, or (2) all leading_zero_8bits syntax elements, zero_byte syntax elements, start_code_prefix_one_3bytes syntax elements, and trailing_zero_8bits syntax elements that form a byte stream from the NAL unit stream. In some embodiments, leading_zero_8bits is a byte equal to 0x00, zero_byte is a single byte equal to 0x00, start_code_prefix_one_3bytes is a fixed sequence of 3 bytes equal to 0x000001, referred to as the start code prefix, and trailing_zero_8bits is a byte equal to 0x00. In some embodiments, the leading_zero_8bits syntax element exists in the first byte stream NAL unit of the bitstream. Any byte equal to 0x00 that follows the NAL unit syntax structure and precedes the four-byte sequence 0x00000001 (will be interpreted as a zero_byte syntax element, followed by a start_code_prefix_one_3bytes syntax element) will be considered a trailing_zero_8bits syntax element, which is part of the previous byte stream NAL unit.

[0122] 7A and Figure 7B Exemplary encoded syntax tables, highlighted in bold, for HRD parameter syntax structures 700A and 700B, consistent with some embodiments of this disclosure. 700A and 700B can be signaled in a VPS or SPS. Figure 7A and Figure 7B As shown, two sets of HRD parameters can be used (NAL HRD parameters and VCL HRD parameters). HRD parameters can be obtained through... Figure 7A The general HRD parameter syntax structure 700A and Figure 7BThe OLS HRD parameter syntax structure 700B uses signals to indicate that the OLS HRD parameter can be part of the VPS or the SPS.

[0123] As mentioned above, OLS and PTL syntax structures (e.g., Figure 6A The PTL syntax structure 600A and the DPB parameter syntax structure (e.g., Figure 6B The DPB parameter syntax structure (600B) and the HRD parameter syntax structure (e.g., Figure 7A and Figure 7B Syntax structures 700A and 700B in the OLS can be signaled in the VPS or SPS. For each of these syntax structures, the VPS or SPS signals a set of syntax structures and the index of the syntax structures applied to each OLS.

[0124] Figure 8 An exemplary encoded syntax table, highlighted in bold, of a portion of the VPS Raw Byte Sequence Payload (RBSP) syntax structure 800, consistent with some embodiments of this disclosure, is shown. Figure 8 As shown, VPS parameter 810 (vps_max_layers_minus1) plus 1 specifies the maximum allowed number of layers in the reference VPS within each CVS. VPS parameter 812 (vps_max_sublayers_minus1) plus 1 specifies the maximum number of temporal sublayers that can exist in the layers of the reference VPS within each CVS. In some embodiments, the value of VPS parameter 812 is within a closed range from 0 to a predefined static value (e.g., 6). VPS parameter 814 (each_layer_is_an_ols_flag) equal to 1 indicates that each OLS contains one layer, and each layer of the reference VPS in the CVS is itself an OLS, where the single contained layer is the only output layer. VPS parameter 814 equal to 0 indicates that an OLS can contain more than one layer. If VPS parameter 810 equals 0, then the value of VPS parameter 814 is inferred to be equal to 1. In some embodiments, if a corresponding flag specifies that one or more layers specified by the VPS can use inter-layer prediction (e.g., vps_all_independent_layers_flag equals 0), then the value of VPS parameter 814 is inferred to be equal to 0.

[0125] In some embodiments, the value of VPS parameter 816 (ols_mode_idc) can be within a closed range of 0 to 2, and the value 3 of VPS parameter 816 can be reserved for future use. In some embodiments, VPS parameter 816 equal to 0 indicates that the total number of OLS specified by VPS (TotalNumOlss) is equal to the value of VPS parameter 810 plus 1, the i-th OLS includes layers with layer indices from 0 to index i, and for each OLS, only the highest layer in the OLS is output. VPS parameter 816 equal to 1 indicates that the total number of OLS specified by VPS is equal to the value of VPS parameter 810 plus 1, the i-th OLS includes layers with layer indices from 0 to index i, and for each OLS, all layers in the OLS are output. VPS parameter 816 equal to 2 indicates that the total number of OLS specified by VPS is explicitly signaled using VPS parameter 818, and for each OLS, the output layer is explicitly signaled, while other layers are layers that are direct or indirect reference layers to the output layer of the OLS.

[0126] In some embodiments, when the corresponding flag specifies that all layers specified by the VPS are encoded independently without using inter-layer prediction (e.g., vps_all_independent_layers_flag equals 1) and VPS parameter 814 equals 0, the value of VPS parameter 816 is inferred to be equal to 2.

[0127] When VPS parameter 816 equals 2, VPS parameter 818 (num_output_layer_sets_minus1) is signaled to indicate that the total number of OLS is reduced by 1. In other words, adding 1 to VPS parameter 818 specifies the total number of OLS (e.g., the variable TotalNumOlss) specified by VPS when VPS parameter 816 equals 2. The variable TotalNumOlss can be derived and calculated from the following code:

[0128] if( vps_max_layers_minus1= =0 )

[0129] TotalNumOlss = 1

[0130] else if( each_layer_is_an_ols_flag| |ols_mode_idc == 0 | | ols_mode_idc == 1 )

[0131] TotalNumOlss = vps_max_layers_minus1 + 1

[0132] else if (ols_mode_idc == 2)

[0133] TotalNumOlss = num_output_layer_sets_minus1 + 1

[0134] Furthermore, when VPS parameter 816 equals 2, VPS parameter 820 (ols_output_layer_flag[i][j]) equals 1, indicating that the j-th layer (i.e., the layer whose nuh_layer_id equals vps_layer_id[j]) is the output layer of the i-th OLS, and VPS parameter 820 equals 0, indicating that the j-th layer is not the output layer of the i-th OLS. In other words, each OLS can define a flag for each layer in the CVS to indicate whether the layer is the output layer of a certain OLS by signaling the relevant flag (e.g., VPS parameter 820).

[0135] The VPS parameter 822 (vps_num_ptls_minus1) incremented by 1 specifies the number of PTL syntax structures in the VPS. The value of VPS parameter 822 can be less than the total number of OLS (i.e., TotalNumOlss).

[0136] The VPS parameter 824 (pt_present_flag[i]) equal to 1 indicates that the file, layer, and general constraint information exists in the i-th PTL syntax structure in the VPS. The VPS parameter 824 equal to 0 indicates that the file, layer, and general constraint information does not exist in the i-th PTL syntax structure in the VPS. In some embodiments, the value of pt_present_flag[0] is inferred to be equal to 1. When the VPS parameter 824 equals 0, the file, layer, and general constraint information of the i-th PTL syntax structure in the VPS is inferred to be the same as the file, layer, and general constraint information of the (i-1)-th PTL syntax structure in the VPS.

[0137] VPS parameter 826 (ptl_max_temporal_id[i]) specifies the highest sublayer temporal identifier (TemporalId) in the i-th PTL syntax structure within the VPS, used to indicate that level information exists therein. The value of VPS parameter 826 can be within a closed range from 0 to VPS parameter 812. When VPS parameter 812 equals 0, the value of VPS parameter 826 is inferred to be 0. When VPS parameter 812 is greater than 0 and the corresponding flag (e.g., vps_all_layers_same_num_sublayers_flag) equals 1, the value of VPS parameter 826 is inferred to be equal to VPS parameter 812.

[0138] In some embodiments, VPS parameter 828 (vps_ptl_alignment_zero_bit) can be equal to 0. In some embodiments, VPS parameter 830 (ols_ptl_idx[i]) specifies the index of the PTL syntax structure applied to the i-th OLS to the list of PTL syntax structures in the VPS. When present, the value of VPS parameter 830 can be in the closed range of 0 to VPS parameter 822. When VPS parameter 828 is equal to 0, the value of VPS parameter 830 is inferred to be equal to 0.

[0139] When NumLayersInOls[i] (a variable specifying the number of layers in the i-th OLS) equals 1, the PTL syntax structure applicable to the i-th OLS also exists in the SPS referenced by the layer in the i-th OLS. In some embodiments, the requirement for bitstream consistency is that when the number of layers in the i-th OLS equals 1, the PTL syntax structure signaled in the VPS and in the SPS for the i-th OLS can be the same.

[0140] VPS parameter 832 (vps_num_dpb_params) specifies the number of DPB parameter syntax structures in the VPS. In some embodiments, the value of VPS parameter 832 can be in a closed range from 0 to 16. When it does not exist, the value of VPS parameter 832 is inferred to be equal to 0.

[0141] VPS parameter 834 (vps_sublayer_dpb_params_present_flag) controls the syntax elements in the DPB parameter syntax structure of the VPS (e.g., max_dec_pic_buffering_minus1[], max_num_reorder_pics[], and...).

[0142] The existence of `max_latency_increase_plus1[]`. When it does not exist, the VPS parameter 834 is inferred to be equal to 0.

[0143] VPS parameter 836 (dpb_max_temporal_id[i]) specifies the TemporalId representing the highest sublayer in the i-th DPB parameter syntax structure within the VPS where the DPB parameter may reside. The value of VPS parameter 836 can be within a closed interval from 0 to VPS parameter 812. When VPS parameter 812 equals 0, the value of VPS parameter 836 is inferred to be 0. When VPS parameter 812 is greater than 0 and the corresponding flag (e.g., vps_all_layers_same_num_sublayers_flag) equals 1, the value of VPS parameter 836 is inferred to be equal to VPS parameter 812.

[0144] The VPS parameters 838 (ols_dpb_pic_width[i]) and 840 (ols_dpb_pic_height[i]) specify the width and height of the image storage buffer for the i-th OLS, respectively, in units of luminance samples.

[0145] VPS parameter 842 (ols_dpb_params_idx[i]) specifies the index of the DPB parameter syntax structure applied to the i-th OLS when NumLayersInOls[i] is greater than 1, pointing to the list of DPB parameter syntax structures in the VPS. When present, the value of VPS parameter 842 can be within a closed range from 0 to the value of VPS parameter 832 minus 1. When VPS parameter 842 is not present, its value is inferred to be equal to 0. In some embodiments, when NumLayersInOls[i] is equal to 1, the DPB parameter syntax structure applied to the i-th OLS exists in the SPS referenced by the layer in the i-th OLS.

[0146] The VPS parameter 844 (vps_general_hrd_params_present_flag) being equal to 1 specifies that a general HRD parameter syntax structure exists in the VPS RBSP syntax structure (e.g., Figure 7A The syntax structure 700A and other HRD parameters are defined in the VPS RBSP syntax structure. A VPS parameter 844 equal to 0 indicates that the generic HRD parameter syntax structure and other HRD parameters do not exist in the VPS RBSP syntax structure. When they do not exist, the value of VPS parameter 844 is inferred to be 0. When NumLayersInOls[i] equals 1, the generic HRD parameter syntax structure applied to the i-th OLS exists in the SPS referenced by the i-th OLS layer.

[0147] The VPS parameter 846 (vps_sublayer_cpb_params_present_flag) being equal to 1 specifies the syntax structure of the i-th OLS HRD parameter in the VPS (e.g., Figure 7B The syntax structure 700B contains the HRD parameter for sublayer representation, where TemporalId takes a value within a closed range from 0 to VPS parameter 850. VPS parameter 846 being equal to 0 specifies the i-th OLS HRD parameter in the VPS. The syntax structure contains the HRD parameter for sublayer representation, where TemporalId is only equal to the value of VPS parameter 850. When VPS parameter 812 is equal to 0, the value of VPS parameter 846 is inferred to be equal to 0.

[0148] When VPS parameter 846 equals 0, the HRD parameter for a sublayer representation with a TemporalId in the closed interval range of 0 to VPS parameter 850 minus 1 is inferred to be the same as the HRD parameter for a sublayer representation with a TemporalId equal to VPS parameter 850. In some embodiments, the HRD parameter includes parameters starting from the fixed_pic_rate_general_flag[i] syntax element and continuing until... Figure 7B The OLS HRD parameter syntax structure in 700B is the sublayer_hrd_parameters(i) syntax structure under the conditional statement "if(general_vcl_hrd_params_present_flag)".

[0149] The VPS parameter 848 (num_ols_hrd_params _minus1) plus 1 specifies the number of OLS HRD parameter syntax structures present in the general HRD parameter syntax structure when the VPS parameter 844 equals 1. The value of the VPS parameter 848 can be within a closed range from 0 to TotalNumOlss minus 1.

[0150] The VPS parameter 850 (hrd_max_tid[i]) specifies the TemporalId representing the highest sublayer of the HRD parameter contained in the i-th OLS HRD parameter syntax structure. The value of VPS parameter 850 can be within a closed range from 0 to VPS parameter 812. When VPS parameter 812 equals 0, the value of VPS parameter 850 is inferred to be 0. When VPS parameter 812 is greater than 0 and the corresponding flag (e.g., vps_all_layers_same_num_sublayers_flag) equals 1, the value of VPS parameter 850 is inferred to be equal to VPS parameter 812.

[0151] VPS parameter 852 (ols_hrd_idx[i]) specifies the index of the OLS HRD parameter syntax structure applied to the i-th OLS when NumLayersInOls[i] is greater than 1, pointing to the list of OLS HRD parameter syntax structures in the VPS. The value of VPS parameter 852 can be in the closed range of 0 to VPS parameter 848. When NumLayersInOls[i] equals 1, the OLS HRD parameter syntax structure applied to the i-th OLS exists in the SPS referenced by the layer in the i-th OLS. In some embodiments, if the value of VPS parameter 848 plus 1 equals TotalNumOlss, the value of VPS parameter 852 is inferred to be equal to index i. In some embodiments, when NumLayersInOls[i] is greater than 1 and VPS parameter 848 equals 0, the value of VPS parameter 852 is inferred to be equal to 0.

[0152] If the SPS layer is an independent layer, the PTL parameter syntax structure, DPB parameter syntax structure, and HRD parameter syntax structure can also be signaled in the Sequence Parameter Set (SPS).

[0153] Figure 9 An exemplary encoded syntax table, highlighted in bold, showing a portion of the SPS RBSP syntax structure 900 signaled in SPS, consistent with some embodiments of this disclosure. (See also:) Figure 9 As shown, SPS parameter 910 (sps_seq_parameter_set_id) provides an identifier for the SPS for reference by other syntax elements. Regardless of the nuh_layer_id value, SPS NAL units share the same value space for SPS parameter 910. Let spsLayerId be the nuh_layer_id value of a specific SPS NAL unit, and vclLayerId be the nuh_layer_id value of a specific VCL NAL unit. A specific VCLNAL unit cannot reference the specific SPS NAL unit unless spsLayerId is less than or equal to vclLayerId and a layer with nuh_layer_id equal to spsLayerId is included in at least one OLS that includes layers with nuh_layer_id equal to vclLayerId.

[0154] The SPS parameter 912 (sps_video_parameter_set_id) specifies the value of vps_video_parameter_set_id for the VPS referenced by the SPS when SPS parameter 912 is greater than 0. In some embodiments, when SPS parameter 912 equals 0, the corresponding SPS does not reference the VPS, and the VPS is not referenced when decoding each CLVS that references the SPS. Furthermore, the corresponding VPS parameter 810 is inferred to be equal to 0, the CVS contains only one layer (i.e., the VCL NAL units in the CVS have the same nuh_layer_id value), the value of GeneralLayerIdx[nuh_layer_id] is inferred to be equal to 0, and the value of vps_independent_layer_flag[GeneralLayerIdx[nuh_layer_id]] is inferred to be equal to 1. When vps_independent_layer_flag[GeneralLayerIdx[nuh_layer_id]] equals 1, the SPS (referenced by the CLVS with a specific nuh_layer_id value nuhLayerId) can have a nuh_layer_id equal to nuhLayerId. In some embodiments, the value of SPS parameter 912 can be the same in the SPS referenced by the CLVS in the CVS.

[0155] The SPS parameter 914 (sps_max_sublayers_minus1) plus 1 specifies the maximum number of temporal sublayers that can exist in each CLVS of the reference SPS. The value of SPS parameter 914 can be within a closed range from 0 to the corresponding VPS parameter 812.

[0156] In some embodiments, the SPS parameter 916 (sps_reserved_zero_4bits) can be equal to 0 in the bitstream. Other values ​​for the SPS parameter 916 can be reserved for future use.

[0157] The SPS parameter 918 (sps_ptl_dpb_hrd_params_present_flag) equal to 1 indicates that PTL syntax structures and DPB parameter syntax structures exist in SPS, and that general HRD parameter syntax structures and OLS HRD parameter syntax structures may also exist in SPS. The SPS parameter 918 equal to 0 indicates that these four syntax structures do not exist in SPS. The value of the SPS parameter 918 can be equal to vps_independent_layer_flag[GeneralLayerIdx[nuh_layer_id]].

[0158] The SPS parameter 920 (sps_sublayer_dpb_params_flag) controls the presence of syntax elements (e.g., max_dec_pic_buffering_minus1[i], max_num_reorder_pics[i], and max_latency_increase_plus1[i]) in the DPB parameter syntax structure within SPS. When these elements are not present, the value of SPS parameter 920 can be inferred to be 0.

[0159] The SPS parameter 922 (sps_general_hrd_params_present_flag) equal to 1 specifies that SPS includes the general HRD parameter syntax structure and the OLS HRD parameter syntax structure. The SPS parameter 922 equal to 0 specifies that SPS does not include the general HRD parameter syntax structure or the OLS HRD parameter syntax structure.

[0160] An SPS parameter 924 (sps_sublayer_cpb_params_present_flag) equal to 1 specifies that the OLSHRD parameter syntax structure in SPS includes HRD parameters for the sublayer representation, where TemporalId takes values ​​in a closed interval from 0 to SPS parameter 914. An SPS parameter 924 equal to 0 specifies that the OLS HRD parameter syntax structure in SPS includes HRD parameters for the sublayer representation, where TemporalId is equal to only SPS parameter 914. When SPS parameter 914 is equal to 0, the value of SPS parameter 924 is inferred to be equal to 0. When SPS parameter 924 is equal to 0, the value of the HRD parameter for a sublayer representation with a TemporalId taking values ​​in a closed interval from 0 to SPS parameter 914 minus 1 is inferred to be the same as the HRD parameter for a sublayer representation with a TemporalId equal to SPS parameter 914. In some embodiments, these HRD parameters include those starting from the fixed_pic_rate_general_flag[i] syntax element up to... Figure 7B The sublayer_hrd_parameters(i) syntax structure under the conditional statement "if( general_vcl_hrd_params_present_flag)" in the OLS HRD parameter syntax structure 700B ends.

[0161] There are several issues with the PTL, DPB, and HRD parameter signal notifications and OLS signal notifications in the aforementioned VPS or SPS.

[0162] For example, such as Figure 8As shown, for the DPB and HRD parameters notified by signals, the number of syntax structures (VPS parameter 832 for the DPB parameter and VPS parameter 848 for the HRD parameter) and the index of the syntax structure applied to the i-th OLS (VPS parameter 842 for the DPB parameter and VPS parameter 852 for the HRD parameter) are signaled in the VPS using the “ue(v)” encoding method, which is a variable-length encoding method where smaller values ​​are encoded with fewer bits and larger values ​​are encoded with more bits. On the other hand, for the PTL parameters notified by signals, the number of syntax structures, VPS parameter 822, and the index of the syntax structure applied to the i-th OLS, VPS parameter 830 are encoded using “u(8)”. This is an encoding method that uses a fixed length of 8 bits for values ​​in the range of 0 to 255.

[0163] Therefore, the number of syntax structures and the encoding methods for syntax structure indices among DPB, HRD, and PTL parameters may differ. Furthermore, in practical applications, the number of PTL syntax structures is typically relatively small. Using 8 bits for these syntax elements (e.g., VPS parameters 822 and 830) would unnecessarily increase the overhead of signal notification.

[0164] Furthermore, to specify which PTL, DPB, and HRD syntax structures are applied to each OLS, the index of each OLS is signaled in the VPS (e.g., VPS parameters 830, 842, or 852). However, if the number of OLS equals the number of syntax structures, an efficient encoder can perform a one-to-one mapping from syntax structures to OLS, avoiding bit waste due to unused syntax structures. Therefore, the encoder can signal syntax structures in the order they are applied, without signaling the indexes. On the decoder side, the i-th syntax structure applied to the i-th OLS can be inferred. By skipping signaling to the indexes, the number of bits can be reduced, thus improving encoding efficiency. In some embodiments, this mechanism is used for HRD parameters. In some embodiments, this mechanism can also be used for PTL and DPB parameters, preventing increased signaling overhead or inconsistencies in signaling design.

[0165] Furthermore, in SPS, when SPS parameter 914 is greater than 0, the signaled SPS parameter 920 controls the existence of syntax elements, including parameters 610B, 620B, and 630B in the DPB parameter syntax structure 600B within SPS. When SPS parameter 918 equals 0, no signal is given to the DPB parameter syntax structure. In other words, when SPS parameter 914 is greater than 0 and SPS parameter 918 equals 0, the signaling of SPS parameter 920 is redundant.

[0166] In addition, Figure 8 In syntax structure 800, the VPS parameter 818, which specifies the total number of OLS, is a fixed-length encoding using 8 bits. Therefore, the maximum value of VPS parameter 818 is 255. OLS are defined by VPS parameter 820 for each layer in the CVS, and the total number of OLS is less than or equal to the number of combinations of VPS parameters 820. When the maximum number of layers in the CVS (i.e., the value of VPS parameter 810 + 1) is less than 8, using 8-bit fixed-length encoding for VPS parameter 818 may not be necessary.

[0167] Figure 10A A flowchart of an exemplary video encoding method 1000A consistent with some embodiments of this disclosure is shown. In some embodiments, the video encoding method 1000A may be performed by an encoder (e.g., an encoder that executes...). Figure 2A Process 200A or Figure 2B The process (using the encoder in process 200B) is executed to generate... Figure 5 The bitstream 500 shown is an example. For instance, an encoder can be implemented for processing video sequences (e.g., ...). Figure 2A or Figure 2B A device for encoding or transcoding the video sequence 202 in the video (e.g., Figure 4 One or more software or hardware components of the device 400 in the middle are used to generate a bitstream of a video sequence (e.g., Figure 2A or Figure 2B The video bitstream 228 in the video stream. For example, the processor (e.g., Figure 4 The processor 402 in the middle can execute video encoding method 1000A.

[0168] Referring to video encoding method 1000A, in step 1010a, the encoder uses a variable-length pair of one or more PTL syntax elements (e.g., PTL-related information) to specify PTL-related information. Figure 8 The VPS parameter 822 or VPS parameter 830 in the bit stream is encoded. At step 1020a, the encoder encodes the bit stream (…). Figure 5 VPS with a bitstream of 500 (e.g., Figure 5 VPS 510) or SPS (e.g., Figure 5 In SPS 520, variable length signals are used to notify one or more PTL syntax elements.

[0169] Figure 10B Some embodiments consistent with this disclosure are shown. Figure 10A A flowchart of an exemplary video decoding method 1000B corresponding to the video encoding method 1000A is shown below. In some embodiments, the video decoding method 1000B may be performed by a decoder (e.g., executing...). Figure 3A The decoding process in 300A or Figure 3B The decoding process in the 300B decoder is executed to decode. Figure 5 The bitstream is 500. For example, a decoder can be implemented for bitstreams (e.g., Figure 3A or Figure 3B A device for decoding the video bitstream 228 in the video (e.g., Figure 4 One or more software or hardware components of the device 400 in the middle to reconstruct the video stream of the bitstream (e.g., Figure 3A or Figure 3B The video stream in the video stream (304). For example, the processor (e.g., Figure 4 The processor 402 in the middle can execute video decoding method 1000B. (See reference...) Figure 10B In video decoding method 1000B, in step 1010b, the decoder receives a bitstream including the VPS or SPS to be decoded (e.g., Figure 5 (bit stream 500 in the VPS or SPS). At step 1020b, the decoder uses a variable length to decode one or more PTL syntax elements that specify PTL-related information in the VPS or SPS.

[0170] Figure 10C and Figure 10D Exemplary VPS syntax structures 1000C and 1000D, consistent with some embodiments of this disclosure, are shown respectively. Each of VPS syntax structures 1000C and 1000D can be used in methods 1000A and 1000B. Based on Figure 8 The syntax structure 800 is modified to change the VPS syntax structure 1000C and 1000D.

[0171] like Figure 10C As shown, in some embodiments, the PTL syntax elements to be encoded or decoded with variable length may include a first PTL syntax element (e.g., VPS parameter 830) specifying the index of the PTL syntax structure or a second PTL syntax element (e.g., VPS parameter 822) specifying the number of PTL syntax structures in the VPS or SPS. The first and second PTL syntax elements can be encoded or decoded using Exponential-Golomb code. For example, the number of PTL syntax structures (e.g., VPS parameter 822) and the index of the PTL syntax structures (e.g., VPS parameter 830) can be encoded using the “ue(v)” encoding method of 0th-order Exponential-Golomb code. For design consistency, the PTL parameters can be signaled in the same manner as the DPB and HDR parameters, where the DPB and HDR parameters are signaled using the “ue(v)” encoding method. Figure 10CAs shown, descriptors 822d and 830d indicate that the encoding method used for VPS parameters 822 and 830 is changed from u(8) to ue(v). Figure 10C The semantics (left column of the table) in the syntax structure of 1000C have not changed, therefore it is consistent with... Figure 8 The syntax structure is the same as 800.

[0172] like Figure 10D As shown in the syntax structure 1000D, in some other embodiments, when encoding a first PTL syntax element (e.g., VPS parameter 830), the length of the first PTL syntax element can be set to the smallest integer greater than or equal to the base-2 logarithm of the number of PTL syntax structures in the VPS or SPS. In some other embodiments, when encoding a second PTL syntax element (e.g., VPS parameter 822), the length of the second PTL syntax element can be a fixed length, such as u(8).

[0173] For example, the index of a PTL syntax structure (e.g., VPS parameter 830) can be encoded using a variable-length encoding method of "u(v)". The number of bits depends on the values ​​of other syntax elements, such as the value associated with the number of PTL syntax structures (e.g., VPS parameter 822), which is still encoded using u(8). Therefore, after parsing the value of VPS parameter 822, the length of VPS parameter 830 is calculated as Ceil(log2(vps_num_ptls_minus1 + 1)), where log2(x) is the base-2 logarithm of x, and Ceil(x) is the smallest integer greater than or equal to x, and then VPS parameter 830 is parsed using Ceil(log2(vps_num_ptls_minus1 + 1)) bits. In particular, for VPS parameter 830, the encoding method can be changed from u(8) to u(v). Similar to Figure 8 In the illustrated embodiment, when present, the value of VPS parameter 830 can be within a closed interval ranging from 0 to VPS parameter 822. When VPS parameter 828 equals 0, the value of VPS parameter 830 is inferred to be equal to 0.

[0174] In some embodiments, when the number of PTL or DPB syntax structures equals the number of OLS, it can be inferred that signaling indexes are unnecessary (e.g., VPS parameters 830 and 842). By omitting signaling indexes, the cost of signaling can be reduced.

[0175] Figure 11A A flowchart of an exemplary video coding method 1100A consistent with some embodiments of this disclosure is shown. Figure 11B Some embodiments consistent with this disclosure are shown. Figure 11AThe flowchart shows the exemplary video decoding method 1100B corresponding to the video encoding method 1100A in the example. Similar to... Figure 10A and Figure 10B Methods 1000A and 1000B, video encoding method 1100A and video decoding method 1100B can be executed by an encoder and decoder of one or more software or hardware components (e.g., a processor executing an instruction set) implemented as a device.

[0176] refer to Figure 11A In the video encoding method 1100A shown, in step 111 0a, the encoder determines whether the number of PTL syntax structures (vps_num_ptls_minus1+1) and the number of OLS (TotalNumOlss) in the VPS are the same. In other words, the encoder determines whether the encoded video sequence (CVS) contains an equal number of PTL syntax structures and OLS.

[0177] In response to the CVS containing an equal number of PTL syntax structures and OLS (step 1110a-Yes), the encoder bypasses steps 1120a and 1130a and encodes the bit stream without signaling the first PTL syntax element (e.g., ols_ptl_idx[i]), which assigns the index of the PTL syntax structure applied to the i-th OLS to the list of PTL syntax structures in the VPS.

[0178] In response to the number of PTL syntax structures differing from the number of OLS (step 1110a - No), in step 1120a, the encoder determines whether the number of PTL syntax structures is equal to 1 (e.g., by determining whether the parameter vps_num_ptls_minus1 is greater than zero). In response to the number of PTL syntax structures being less than or equal to 1 (step 1120a - No), the encoder bypasses step 1130a and encodes the bitstream without signaling the first PTL syntax element in the VPS.

[0179] In response to the number of PTL syntax structures being greater than 1 and different from the number of OLS (step 1110a - No, step 1120a - Yes), the encoder performs step 1130a and signals the first PTL syntax element in the VPS (or SPS). In some embodiments, the first PTL syntax element is signaled with a fixed length.

[0180] In some other embodiments, step 1120a is performed before step 1110a. Step 1130a is performed in response to the number of PTL syntax structures being greater than 1 and different from the number of OLS (step 1120a - Yes, step 1110a - No); otherwise, step 1130a is skipped. For example, in response to the number of PTL syntax structures being equal to 1 (step 1120a - No), the encoder may bypass steps 1110a and 1130a.

[0181] Similar to the encoding of PTL syntax elements, the encoding of DPB syntax element indices (e.g., VPS parameter 842) can be inferred without signal notification when certain conditions are met.

[0182] In step 1140a, the encoder determines whether the number of DPB parameter syntax structures (vps_num_dpb_params) and the number of OLS (TotalNumOlss) in the VPS are the same. In other words, the encoder determines whether the encoded video sequence (CVS) contains an equal number of DPB parameter syntax structures and OLS.

[0183] In response to the number of DPB parameter syntax structures being the same as the number of OLS (step 1140a - Yes), the encoder bypasses steps 1150a and 1160a and encodes the bit stream without signaling the first DPB syntax element (e.g., ols_dpb_params_idx[i]), which specifies the index of the DPB parameter syntax structure applied to the i-th OLS to the list of DPB parameter syntax structures in the VPS.

[0184] In response to the number of DPB parameter syntax structures differing from the number of OLS (step 1140a - No), in step 1150a, the encoder determines whether the number of DPB parameter syntax structures is equal to 1 (e.g., by determining whether the parameter vps_num_dpb_params is greater than 1). In response to the number of DPB parameter syntax structures being less than or equal to 1 (step 1150a - No), the encoder bypasses step 1160a and encodes the bitstream without signaling the first DPB syntax element.

[0185] In response to the number of DPB parameter syntax structures being greater than 1 and different from the number of OLS (step 1140a - No, step 1150a - Yes), the encoder performs step 1160a and signals the first DPB syntax element in the VPS. In some embodiments, ue(v) is used to signal the first DPB syntax element with a variable length.

[0186] In some embodiments, step 1150a is performed before step 1140a. Step 1160a is performed in response to the number of DPB syntax structures being greater than 1 and different from the number of OLS structures (step 1150a - Yes, step 1140a - No); otherwise, step 1160a is skipped. For example, in response to the number of DPB syntax structures being equal to 1 (step 1150a - No), the encoder may bypass steps 1140a and 1160a.

[0187] refer to Figure 11B The video decoding method 1100B shown, on the decoder side, in step 1110b, the decoder receives a bitstream including an encoded video sequence (CVS) (e.g., Figure 5 In the video bitstream 500. In step 1120b, the decoder determines whether the number of PTL syntax structures (vps_num_ptls_minus1+1) and the number of OLS (TotalNumOlss) in the VPS are the same. In some embodiments, the decoder decodes one or more VPS syntax elements associated with OLS to obtain information about the number of OLS (TotalNumOlss).

[0188] In response to the number of PTL syntax structures being the same as the number of OLS (step 1120b - Yes), in step 1125b, the decoder infers a first PTL syntax element (e.g., ols_ptl_idx[i]) that assigns an index to the list of PTL syntax structures in the VPS equal to the ordinal number (e.g., index i) of the PTL syntax structure applied to the i-th OLS. In response to the number of PTL syntax structures being different from the number of OLS (step 1120b - No), in step 1130b, the decoder determines whether the number of PTL syntax structures is equal to 1 (e.g., by determining whether the parameter vps_num_ptl_minus1 is greater than zero). In response to the number of PTL syntax structures being less than or equal to 1 (step 1130b - No), in step 1135b, the decoder infers that the first PTL syntax element is zero.

[0189] In response to the PTL syntax structure having a number greater than 1 and different from the number of OLS (step 1120b - No, step 1130b - Yes), the decoder performs step 1140b and decodes the first PTL syntax element encoded in the VPS or SPS. In some embodiments, the first PTL syntax element is signaled in the VPS or SPS with a fixed length.

[0190] In some embodiments, step 1130b is performed before step 1120b. If the number of PTL syntax structures is greater than 1 and is different from the number of OLS (step 1130b - yes, step 1120b - no), step 1140a is performed; otherwise, step 1140a is skipped.

[0191] Similarly, in step 1150b, the decoder determines whether the number of DPB parameter syntax structures (vps_num_dpb_params) and the number of OLS (TotalNumOlss) in the VPS are the same.

[0192] In response to the fact that the number of DPB parameter syntax structures is the same as the number of OLS (step 1150b - Yes), in step 1155b, the decoder infers a first DPB syntax element (e.g., ols_dpb_params_idx[i]) that specifies the index of the list of DPB parameter syntax structures in the VPS that applies to the DPB parameter syntax structures of the i-th OLS is equal to the ordinal number of the i-th OLS (e.g., index i).

[0193] In response to the number of DPB parameter syntax structures differing from the number of OLS (step 1150b - No), in step 1160b, the decoder determines whether the number of DPB parameter syntax structures is equal to 1 (e.g., by determining whether the parameter vps_num_dpb_params is greater than 1). In response to the number of DPB parameter syntax structures being less than or equal to 1 (step 1160b - No), in step 1165b, the decoder infers that the first DPB syntax element is zero.

[0194] In response to the number of DPB parameter syntax structures being greater than 1 and different from the number of OLS (step 1150b - No, step 1160b - Yes), the decoder performs step 1170b and decodes the first DPB syntax element in the VPS. In some embodiments, ue(v) is used to signal the first DPB syntax element with a variable length.

[0195] In some embodiments, step 1160b is performed before step 1150b. Step 1170b is performed in response to the number of DPB parameter syntax structures being greater than 1 and different from the number of OLS (step 1160b - yes, step 1150b - no); otherwise, step 1170b is skipped.

[0196] Figure 11C A portion of an exemplary VPS syntax structure 1100C associated with possible implementations of the proposed methods 1100A and 1100B, consistent with some embodiments of this disclosure, is shown. Figure 11C The VPS syntax structure in 1100C is based on Figure 8 The syntax structure has been modified 800 times.

[0197] and Figure 8 Compared to the illustrated embodiment, as shown in the conditional statement 1110c of the VPS syntax structure 1100C, when the value of VPS parameter 822 plus 1 (vps_num_ptls_minus1) is not equal to the total number of OLS specified by VPS (TotalNumOlss) and is not equal to 0, VPS parameter 830 is signaled. If the value of VPS parameter 822 plus 1 is equal to TotalNumOlss, then the value of VPS parameter 830 is inferred to be equal to index i. When VPS parameter 822 is equal to 0, the value of VPS parameter 830 is inferred to be equal to 0.

[0198] Similarly, as shown in conditional statement 1120c of VPS syntax structure 1100C, when the value of VPS parameter 832 is not equal to TotalNumOlss and is not equal to 0, VPS parameter 842 is signaled (ols_dpb_params_idx[i]). When VPS parameter 842 is not signaled, if the value of VPS parameter 832 is equal to TotalNumOlss, the value of VPS parameter 842 is inferred to be index i. When VPS parameter 832 is equal to 0, the value of VPS parameter 842 is inferred to be equal to 0.

[0199] As described above, during encoding or decoding, the encoder or decoder may need to determine the number of OLS (TotalNumOls) in the VPS. In some embodiments, the decoder and encoder can derive the number of OLS based on the OLS pattern indicated by a VPS syntax element (e.g., VPS parameter 816) and the maximum number of layers in the CVS indicated by another VPS syntax element (e.g., VPS parameter 810). In some embodiments, the encoder can encode the VPS syntax element with a fixed length (e.g., VPS parameter 818), where the fixed length is associated with the number of OLS specified by the VPS, and the decoder can decode the VPS syntax element with the fixed length to determine the number of OLS specified by the VPS. In some embodiments, the encoder can encode the VPS syntax element with a variable length (e.g., VPS parameter 818), where the variable length is associated with the number of OLS contained in the CVS of the reference VPS. And the decoder can use the VPS syntax element decoded with the variable length to determine the number of OLS contained in the CVS of the reference VPS. When the maximum allowed number is less than a predefined length value, the length of the VPS syntax element can be equal to the maximum allowed number of layer combinations in the CVS of the reference VPS.

[0200] Figure 11DThe embodiments shown are consistent with those of this disclosure. Figure 8 This is a portion of an exemplary VPS syntax structure 1100D, modified from the syntax structure 800 and associated with possible implementations that encode or decode VPS syntax elements using variable lengths. In some cases, the total number of OLS is limited by the number of combinations of VPS parameters 820 (ols_output_layer_flag) across all layers in the CVS, and TotalNumOlss satisfies the following inequality:

[0201] TotalNumOlss ≤

[0202] VPS parameter 818 plus 1 specifies the total number of OLS specified by the VPS when VPS parameter 816 equals 2. Therefore, VPS parameter 818 can be represented by (vps_max_layers_minus1 + 1) bits (e.g., the value of VPS parameter 810 plus 1).

[0203] In some embodiments, such as Figure 11D As shown, the descriptor 818d, highlighted in italics, indicates that the encoding method for VPS parameter 818 can be variable-length encoding, where the length of VPS parameter 818 is a predefined value (e.g., 8), or a value of VPS parameter 810 plus 1 (i.e., the maximum number of layers allowed in the CVS of the reference VPS), whichever is smaller. For example, in some embodiments, the length of VPS parameter 818 can be determined based on the following min function:

[0204] Min(8, vps_max_layers_minus1 + 1 )

[0205] Refer again Figure 9 As mentioned above, the value of SPS parameter 914 can be within a closed range from 0 to the corresponding VPS parameter 812. In some embodiments, when SPS parameter 912 equals 0, SPS does not reference VPS, therefore there is no corresponding VPS parameter 812, and thus the range of SPS parameter 914 is undefined. When SPS parameter 912 (sps_video_parameter_set_id) equals 0, this issue can be resolved by modifying the syntax to assign a range of values ​​for SPS parameter 914 independent of VPS parameter 812.

[0206] Figure 12A A flowchart of an exemplary video coding method 1200A consistent with some embodiments of this disclosure is shown. Figure 12B Some embodiments consistent with this disclosure are shown. Figure 12AThe flowchart shows an exemplary video decoding method 1200B corresponding to the video encoding method 1200A in the example. Similar to... Figure 10A and Figure 10B Methods 1000A and 1000B, video encoding method 1200A and video decoding method 1200B can be executed by an encoder and decoder of one or more software or hardware components (e.g., a processor executing an instruction set) implemented as a device.

[0207] refer to Figure 12A In the video coding method 1200A shown, in step 1210a, the encoder encodes a first SPS syntax element (e.g., SPS parameter 914 sps_max_sublayers_minus1), which is associated with the maximum number of temporal sublayers that may exist in each CLVS of the reference SPS. At step 1220a, the encoder determines whether a PTL syntax structure, a DPB parameter syntax structure, and / or an HRD parameter syntax structure exist in the SPS. For example, the encoder may make this determination and then set the SPS parameter 918 based on this determination.

[0208] The value of (sps_ptl_dpb_hrd_params_present_flag). If determined to be true (step 1220a - Yes), the encoder performs step 1230a and determines whether the maximum number of temporal sublayers present in each coding layer video sequence (CLVS) of the reference SPS is greater than 1 by determining whether the SPS parameter 914 is greater than zero.

[0209] When both conditions are met (step 1220a - Yes, step 1230a - Yes), in step 1240a, the encoder signals a flag (e.g., SPS parameter 920, sps_sublayer_dpb_params_flag) that is configured to control the presence of syntax elements in the DPB parameter syntax structure in the SPS. The encoder then performs step 1250a to signal one or more syntax elements in the DPB parameter syntax structure.

[0210] When the maximum number of sublayers in the domain is equal to or less than 1 (step 1220a - yes, step 1230a - no), the encoder bypasses step 1240a and executes step 1250a to signal one or more syntax elements in the DPB parameter syntax structure by setting a flag (e.g., SPS parameter 920, sps_sublayer_dpb_params_flag) to 0 without signaling the flag.

[0211] If the PTL syntax structure, DPB parameter syntax structure, and HRD parameter syntax structure are not present in the SPS (steps 1220a-no), the encoder bypasses steps 1230a-1250a and encodes the SPS without sending flags (e.g., SPS parameter 920, sps_sublayer_dpb_params_flag) and DPB syntax elements.

[0212] In some embodiments, for encoding the SPS parameter 914 in video coding method 1200A, when the SPS references the VPS, the range of the SPS parameter 914 (sps_max_sublayers_minus1) can be set to the same range as the VPS parameter 812 (vps_max_sublayers_minus1). When the SPS does not reference the VPS and therefore the corresponding VPS parameter 812 (vps_max_sublayers_minus1) does not exist, the range of the SPS parameter 914 can still be defined by setting a predefined value. For example, the value of the VPS parameter 812 can be in the range of 0 to a predefined static value (e.g., 6). Therefore, the value of the SPS parameter 914 can be in the closed interval range of 0 to MaxSubLayer minus 1, where the value of the MaxSubLayer sublayer parameter can be derived and calculated from the code using ternary operators, as follows:

[0213] MaxSubLayer = (sps_video_parameter_set_id == 0 ? 6 : vps_max_sublayers_minus1) + 1

[0214] Alternatively, the encoder can first determine the value of SPS parameter 912, which specifies the identifier of the VPS referenced by the SPS when the value of SPS parameter 912 is greater than zero, and indicates that the SPS does not reference a VPS when the value of SPS parameter 912 is equal to zero. Then, in response to the value of SPS parameter 912 being greater than zero, the encoder allocates a range of SPS parameter 914 based on the corresponding VPS parameter 812, which specifies the maximum number of temporal sublayers present in each CLVS of the referenced SPS. That is, the value of SPS parameter 914 (e.g., sps_max_sublayers_minus1) is in the range of 0 to VPS parameter 812 (e.g., vps_max_sublayers_minus1), including end values. On the other hand, in response to the value of SPS parameter 912 being equal to zero, the encoder allocates the range of SPS parameter 914 as a closed interval range from zero to a fixed value (e.g., 6). In other words, the value of the SPS parameter 914 (e.g., sps_max_sublayers_minus1) is in the range of 0 to 6, including the end values.

[0215] Therefore, when SPS parameter 914 equals 0, an inferred value can be given to SPS parameter 914. Thus, the maximum value of SPS parameter 914 is available when SPS does not reference any VPS. In some embodiments, the semantics can be changed such that when SPS parameter 912 equals 0, the value of VPS parameter 812 (vps_max_sublayers_minus1) is inferred to be equal to a predefined static value (e.g., 6).

[0216] refer to Figure 12B In the video decoding method 1200B shown, on the decoder side, in step 1210b, the decoder receives a bitstream including the SPS to be decoded (e.g., Figure 5 The video bitstream 500 in step 1220b is used. In step 1220b, the decoder decodes the first SPS syntax element (e.g., SPS parameter 914 sps_max_sublayers_minus1). In some embodiments, on the decoder side, when decoding the SPS, the decoder may first determine the value of SPS parameter 912 and then decode SPS parameter 914. The range of SPS parameter 914 is based on the corresponding VPS parameter 912 of the VPS referenced by the SPS when the value of SPS parameter 912 is greater than zero, or based on a fixed value when the value of SPS parameter 912 is equal to zero.

[0217] In step 1230b, the decoder determines whether a PTL syntax structure, a DPB parameter syntax structure, and / or an HRD parameter syntax structure exists in the SPS. For example, the decoder may make this determination based on whether the SPS parameter 918 (sps_ptl_dpb_hrd_params_present_flag) is equal to 1. If the determination is true (step 1230b - Yes), the decoder executes step 1240b and determines whether the maximum number of temporal sublayers present in each coding layer video sequence (CLVS) of the reference SPS is greater than 1 by determining whether the SPS parameter 914 is greater than zero.

[0218] When both conditions are met (step 1230b - Yes, step 1240b - Yes), in step 1250b, the decoder decoding flag (e.g., SPS parameter 920, sps_sublayer_dpb_params_flag) is SPS, which is signaled in the SPS and configured to control the presence of syntax elements in the DPB parameter syntax structure. The decoder then performs step 1260b to decode one or more syntax elements in the DPB parameter syntax structure based on the value of the flag (e.g., SPS parameter 920, sps_sublayer_dpb_params_flag).

[0219] When the maximum number of sublayers in the time domain is equal to or less than 1 (step 1230b - Yes, step 1240b - No), the decoder bypasses step 1250b and infers that the flag (e.g., SPS parameter 920, sps_sublayer_dpb_params_flag) is equal to zero, and then performs step 1260b to decode one or more syntax elements in the DPB parameter syntax structure based on the value of the flag (e.g., SPS parameter 920, sps_sublayer_dpb_params_flag).

[0220] If the PTL syntax structure, DPB parameter syntax structure, and HRD parameter syntax structure do not exist in the SPS (step 1230b - No), the decoder bypasses steps 1240b-1260b and decodes the SPS without decoding the flags and DPB syntax elements.

[0221] Figure 12C A portion of an exemplary SPS syntax structure 1200C, consistent with some embodiments of this disclosure, is shown as associated with possible implementations of the proposed methods 1200A and 1200B. It can be based on... Figure 9 The syntax structure of 900 is modified. Figure 12CThe SPS syntax structure 1200C is described above. In some embodiments, the signal notification of SPS parameter 920 can be conditional on SPS parameters 918 and 914. Therefore, as... Figure 12C As shown, the syntax element SPS parameter 920 can be signaled (or decoded) if SPS parameter 918 equals 1 and SPS parameter 914 is greater than 0. Otherwise, SPS parameter 920 is not signaled (or decoded).

[0222] In summary, as proposed in the various embodiments of this disclosure, by using variable-length encoded or decoded PTL syntax elements, the encoding methods for the number of syntax structures and syntax structure indices among DPB, HRD, and PTL parameters can be consistent and efficient, and can reduce the signaling overhead incurred by using fixed lengths for these syntax elements. Furthermore, by appropriately inferring the value of a syntax element when it is not signaled, signaling of the index can be skipped in some cases, reducing the number of output bits and thus improving encoding efficiency. This method can be used for HRD parameters as well as PTL and DPB parameters to reduce signaling overhead and ensure consistency in signaling design.

[0223] The embodiments may be further described using the following terms:

[0224] 1. A computer-implemented video encoding method, comprising:

[0225] Determine whether the encoded video sequence (CVS) contains an equal number of files, layers, and levels (PTL), syntax structure, and output layer set (OLS); and

[0226] In response to the CVS containing an equal number of PTL syntax structures and OLS, the bitstream is encoded without signaling the first PTL syntax element, which assigns the index of the PTL syntax structure corresponding to the OLS in the VPS to the list of PTL syntax structures in the VPS.

[0227] 2. The method described in Clause 1 further includes:

[0228] Determine whether the number of PTL syntax structures is equal to 1; and

[0229] In response to the PTL syntax structure having a quantity of 1, the bitstream is encoded without signaling the first PTL syntax element in the VPS.

[0230] 3. The method described in Clause 1 further includes:

[0231] In response to the PTL syntax structure having a number greater than 1 and different from the number of OLS, the first PTL syntax element is notified in the VPS with a signal of fixed length.

[0232] 4. A computer-implemented video encoding method, comprising:

[0233] Determine whether the encoded video sequence (CVS) has an equal number of decoded image buffers (DPB), parameter syntax structure, and output layer set (OLS); and

[0234] In response to the CVS having an equal number of DPB parameter syntax structures and OLS, the bitstream is encoded without signaling the first DPB syntax element, which assigns the index of the DPB parameter syntax structure to be applied to the corresponding OLS to the list of DPB parameter syntax structures in the VPS.

[0235] 5. The method described in Clause 4 further includes:

[0236] Determine whether the number of the DPB parameter syntax structures is less than or equal to 1; and

[0237] In response to the number of DPB parameter syntax structures being equal to 1, the bitstream is encoded without signaling the first DPB syntax element in the VPS.

[0238] 6. The method described in Clause 4 further includes:

[0239] In response to the fact that the number of DPB parameter syntax structures is greater than 1 and is different from the number of OLS, the first DPB syntax element is signaled in the VPS with a variable length.

[0240] 7. A computer-implemented video encoding method, comprising:

[0241] Determine whether at least one of the following exists in the Sequence Parameter Set (SPS) of the bitstream: File, Level, and Grade (PTL) syntax structure, Decoded Image Buffer (DPB) parameter syntax structure, or Hypothetical Reference Decoder (HRD) parameter syntax structure;

[0242] Determine whether a first value is greater than 1, where the first value specifies the maximum number of temporal sublayers present in the coded layer video sequence (CLVS) of the reference SPS; and

[0243] When at least one of the PTL syntax structure, the DPB parameter syntax structure, or the HRD parameter syntax structure exists in the SPS and the first value is greater than 1, a signal is used to notify the presence of a flag configured to control the presence of a syntax element in the DPB parameter syntax structure in the SPS.

[0244] 8. The method described in Clause 7 further includes:

[0245] When the first value is equal to or less than 1, one or more syntax elements are signaled in the DPB parameter syntax structure, but the flag is not signaled in the SPS.

[0246] 9. A computer-implemented video encoding method, comprising:

[0247] Determine the value of a first sequence parameter set (SPS) syntax element, wherein the first SPS syntax element specifies an identifier of a video parameter set (VPS) referenced by the SPS when the value of the first SPS syntax element is greater than zero;

[0248] In response to a value greater than zero for the first SPS syntax element, a range of second SPS syntax elements is allocated based on the corresponding VPS syntax element. The second SPS syntax element specifies the maximum number of temporal sublayers present in each coded layer video sequence (CLVS) referencing the SPS; and

[0249] In response to the first SPS syntax element having a value of zero, the range of the second SPS syntax element is assigned to a closed interval from zero to a fixed value, the second SPS syntax element specifying the maximum number of temporal sublayers present in each CLVS of the reference SPS.

[0250] 10. A computer-implemented video encoding method, comprising:

[0251] Encode one or more file, level, and grade (PTL) syntax elements that are related to a specified PTL; and

[0252] Use variable-length signaling to notify one or more PTL syntax elements in the bitstream's Video Parameter Set (VPS) or Sequence Parameter Set (SPS).

[0253] 11. The method according to Clause 10, wherein encoding the one or more PTL syntax elements comprises:

[0254] The first PTL syntax element is encoded using a variable length, and the first PTL syntax element specifies the index of the PTL syntax structure.

[0255] 12. The method according to Clause 11, wherein the VPS or the SPS comprises N PTL syntax structures, where N is an integer, and encoding the one or more PTL syntax elements further comprises:

[0256] Set the length of the first PTL syntax element to the smallest integer greater than or equal to the logarithm of N to the base 2.

[0257] 13. The method according to Clause 11, wherein encoding the one or more PTL syntax elements comprises:

[0258] The first PTL syntax element is encoded using exponential Golomb codes.

[0259] 14. The method according to Clause 10, wherein the VPS or the SPS comprises N PTL syntax structures, where N is an integer, and encoding the one or more PTL syntax elements comprises:

[0260] The second PTL syntax element, which specifies the N, is encoded using a variable length.

[0261] 15. A computer-implemented video encoding method, comprising:

[0262] Encoding is performed using variable-length Video Parameter Set (VPS) syntax elements; and

[0263] In a VPS, the VPS syntax element is signaled to be associated with the number of output layer sets (OLS) contained in the coded video sequence (CVS) of the reference VPS.

[0264] 16. The method described in Clause 15 further includes:

[0265] When the maximum allowed number of layers in the encoded video sequence (CVS) of the reference VPS is less than a predefined length value, the length of the VPS syntax element is set to be equal to the maximum allowed number.

[0266] 17. A computer-implemented video decoding method, comprising:

[0267] Receive bitstreams including encoded video sequences (CVS);

[0268] Determine whether the CVS has the same number of File, Level, and Grade (PTL) syntax structures and Output Level Sets (OLS); and

[0269] In response to the number of PTL syntax structures being equal to the number of OLS, the decoding of the first PTL syntax element is skipped. The index of the first PTL syntax element, which is applied to the PTL syntax structure of the corresponding OLS when decoding the VPS, is specified in the list of PTL syntax structures in the VPS.

[0270] 18. The method described under Clause 17 further includes:

[0271] In response to the fact that the number of PTL syntax structures equals the number of OLS, the first PTL syntax element is determined to be equal to the index of the OLS to which the PTL syntax structure specified by the first PTL syntax element applies.

[0272] 19. The method described under Clause 17 further includes:

[0273] Determine whether the number of PTL syntax structures is equal to 1; and

[0274] In response to the PTL syntax structure having a quantity of 1, the decoding of the first PTL syntax element is skipped when decoding the VPS.

[0275] 20. The method described pursuant to Clause 19 further includes:

[0276] In response to the fact that the number of PTL syntax structures is equal to 1, the first PTL syntax element is determined to be zero.

[0277] 21. The method described in Clause 17 further includes:

[0278] In response to the fact that the number of PTL syntax structures is greater than 1 and is different from the number of OLS, the first PTL syntax element is decoded in the VPS with a fixed length.

[0279] 22. A computer-implemented video decoding method, comprising:

[0280] Receive bitstreams including encoded video sequences (CVS);

[0281] Determine whether the CVS has an equal number of decoded image buffers (DPB), parameter syntax structures, and output layer sets (OLS); and

[0282] In response to the CVS having an equal number of DPB parameter syntax structures and OLS, the decoding of the first DPB syntax element is skipped, and the index of the DPB parameter syntax structure applied to the corresponding OLS is assigned to the list of DPB parameter syntax structures in the VPS.

[0283] 23. The method described pursuant to Clause 22 further includes:

[0284] Determine whether the number of the DPB parameter syntax structures is less than or equal to 1; and

[0285] In response to the number of DPB parameter syntax structures being less than or equal to 1, the decoding of the first DPB syntax element is skipped when decoding the VPS.

[0286] 24. The method described pursuant to Clause 23 further includes:

[0287] In response to the fact that the number of DPB parameter syntax structures is less than or equal to 1, the first DPB syntax element is determined to be zero; and

[0288] In response to the fact that the number of DPB syntax structures equals the number of OLS, the first DPB syntax element is determined to be equal to the index of the OLS to which the DPB parameter syntax structure specified by the first DPB syntax element is applied.

[0289] 25. The method described under Clause 23 further includes:

[0290] In response to the fact that the number of DPB parameter syntax structures is greater than 1 and is different from the number of OLS, the first DPB syntax element is decoded in the VPS using a variable length.

[0291] 26. A computer-implemented video decoding method, comprising:

[0292] Receive bitstreams including Video Parameter Set (VPS) and Sequence Parameter Set (SPS);

[0293] In response to at least one of the File, Layer, and Type (PTL) syntax structure, Decoded Picture Buffer (DPB) parameter syntax structure, or Hypothetical Reference Decoder (HRD) parameter syntax structure present in the SPS, a first value is determined to be greater than 1, the first value specifying the maximum number of temporal sub-layers present in each coding layer video sequence (CLVS) referencing the SPS; and

[0294] In response to the first value being greater than 1, the flag configured to control the presence of syntax elements in the DPB parameter syntax structure in the SPS is decoded.

[0295] 27. The method described pursuant to Clause 26 further includes:

[0296] In response to the first value being equal to or less than 1, it is inferred that the flag is equal to zero, and one or more syntax elements in the DPB parameter syntax structure are decoded in the SPS without decoding the flag.

[0297] 28. A computer-implemented video decoding method, comprising:

[0298] Determine the value of a first Sequence Parameter Set (SPS) syntax element, wherein the first SPS syntax element specifies an identifier of a Video Parameter Set (VPS) referenced by an SPS when the value of the first SPS syntax element is greater than zero; and

[0299] The second SPS syntax element is decoded, which specifies the maximum number of temporal sub-layers present in each coding layer video sequence (CLVS) of the reference SPS. When the value of the first SPS syntax element is greater than zero, the range of the second SPS syntax element is based on the corresponding VPS syntax element of the VPS referenced by the SPS, or when the value of the first SPS syntax element is equal to zero, the range of the second SPS syntax element is based on a fixed value.

[0300] 29. A computer-implemented video decoding method, comprising:

[0301] Receive bitstreams including Video Parameter Set (VPS) or Sequence Parameter Set (SPS); and

[0302] Decode one or more file, tier, and level (PTL) syntax elements in the VPS or SPS, wherein the one or more PTL syntax elements specify PTL-related information.

[0303] 30. The method according to Clause 29, wherein decoding the one or more PTL syntax elements comprises:

[0304] The first PTL syntax element, which specifies the index of the PTL syntax structure, is decoded using a variable length.

[0305] 31. The method according to Clause 30, wherein the VPS or the SPS comprises N PTL syntax structures, N is an integer, and the length of the first PTL syntax element is the smallest integer greater than or equal to the logarithm of N to the base 2.

[0306] 32. The method according to Clause 30, wherein the first PTL syntax element is encoded using exponential Golomb codes.

[0307] 33. The method according to Clause 29, wherein the VPS or the SPS comprises N PTL syntax structures, where N is an integer, and decoding the one or more PTL syntax elements comprises:

[0308] The second PTL syntax element, which specifies N, is decoded using a variable length.

[0309] 34. A computer-implemented video decoding method, comprising:

[0310] Receives a bitstream including a Video Parameter Set (VPS); and

[0311] VPS syntax elements in a VPS are decoded using a variable length, the VPS syntax elements being associated with the number of output layer sets (OLS) contained in a coded video sequence (CVS) referencing the VPS.

[0312] 35. The method according to Clause 34, wherein when the maximum allowed number of layers in the encoded video sequence (CVS) of the VPS referenced is less than a predefined length value, the length of the VPS syntax element is equal to the maximum allowed number.

[0313] 36. An apparatus comprising:

[0314] A memory configured to store instructions; and

[0315] A processor, coupled to the memory and configured to execute the instructions to cause the device to perform:

[0316] Determine whether the encoded video sequence (CVS) contains an equal number of files, layers, and levels (PTL), syntax structure, and output layer set (OLS); and

[0317] In response to the CVS containing an equal number of PTL syntax structures and OLS, the bitstream is encoded without signaling the first PTL syntax element, which assigns the index of the PTL syntax structure corresponding to the OLS in the VPS to the list of PTL syntax structures in the VPS.

[0318] 37. The apparatus according to claim 36, wherein the processor is configured to execute the instructions to:

[0319] Determine whether the number of PTL syntax structures is equal to 1; and

[0320] In response to the PTL syntax structure having a quantity of 1, the bitstream is encoded without signaling the first PTL syntax element in the VPS.

[0321] 38. The apparatus according to clause 36, wherein the processor is configured to execute the instructions to:

[0322] In response to the PTL syntax structure having a number greater than 1 and different from the number of OLS, the first PTL syntax element is notified in the VPS with a signal of fixed length.

[0323] 39. An apparatus comprising:

[0324] A memory configured to store instructions; and

[0325] A processor, coupled to the memory and configured to execute the instructions to cause the device to:

[0326] Determine whether the encoded video sequence (CVS) has an equal number of decoded image buffers (DPB), parameter syntax structure, and output layer set (OLS); and

[0327] In response to the CVS having an equal number of DPB parameter syntax structures and OLS, the bitstream is encoded without signaling the first DPB syntax element, which assigns the index of the DPB parameter syntax structure to be applied to the corresponding OLS to the list of DPB parameter syntax structures in the VPS.

[0328] 40. The apparatus according to claim 39, wherein the processor is configured to execute the instructions to:

[0329] Determine whether the number of the DPB parameter syntax structures is less than or equal to 1; and

[0330] In response to the number of DPB parameter syntax structures being equal to 1, the bitstream is encoded without signaling the first DPB syntax element in the VPS.

[0331] 41. The apparatus according to clause 39, wherein the processor is configured to execute the instructions to:

[0332] In response to the fact that the number of DPB parameter syntax structures is greater than 1 and is different from the number of OLS, the first DPB syntax element is signaled in the VPS with a variable length.

[0333] 42. An apparatus comprising:

[0334] A memory configured to store instructions; and

[0335] A processor, coupled to the memory and configured to execute the instructions to cause the device to:

[0336] Determine whether at least one of the following exists in the Sequence Parameter Set (SPS) of the bitstream: File, Level, and Grade (PTL) syntax structure, Decoded Image Buffer (DPB) parameter syntax structure, or Hypothetical Reference Decoder (HRD) parameter syntax structure;

[0337] Determine whether a first value is greater than 1, where the first value specifies the maximum number of temporal sublayers present in the coded layer video sequence (CLVS) of the reference SPS; and

[0338] When at least one of the PTL syntax structure, the DPB parameter syntax structure, or the HRD parameter syntax structure exists in the SPS and the first value is greater than 1, a signal is used to notify the presence of a flag configured to control the presence of a syntax element in the DPB parameter syntax structure in the SPS.

[0339] 43. The apparatus according to clause 42, wherein the processor is configured to execute the instructions to:

[0340] When the first value is equal to or less than 1, one or more syntax elements are signaled in the DPB parameter syntax structure, but the flag is not signaled in the SPS.

[0341] 44. An apparatus comprising:

[0342] A memory configured to store instructions; and

[0343] A processor, coupled to the memory and configured to execute the instructions to cause the device to:

[0344] Determine the value of a first sequence parameter set (SPS) syntax element, wherein the first SPS syntax element specifies an identifier of a video parameter set (VPS) referenced by the SPS when the value of the first SPS syntax element is greater than zero;

[0345] In response to a value greater than zero for the first SPS syntax element, a range of second SPS syntax elements is allocated based on the corresponding VPS syntax element. The second SPS syntax element specifies the maximum number of temporal sublayers present in each coded layer video sequence (CLVS) referencing the SPS; and

[0346] In response to the first SPS syntax element having a value of zero, the range of the second SPS syntax element is assigned to a closed interval from zero to a fixed value, the second SPS syntax element specifying the maximum number of temporal sublayers present in each CLVS of the reference SPS.

[0347] 45. An apparatus comprising:

[0348] A memory configured to store instructions; and

[0349] A processor, coupled to the memory and configured to execute the instructions to cause the device to:

[0350] Encode one or more file, level, and grade (PTL) syntax elements that are related to a specified PTL; and

[0351] Use variable-length signaling to notify one or more PTL syntax elements in the bitstream's Video Parameter Set (VPS) or Sequence Parameter Set (SPS).

[0352] 46. ​​The apparatus according to clause 45, wherein the processor is configured to execute the instructions to encode the one or more PTL syntax elements in such a way as:

[0353] The first PTL syntax element is encoded using a variable length, and the first PTL syntax element specifies the index of the PTL syntax structure.

[0354] 47. The apparatus according to Clause 46, wherein the VPS or the SPS comprises N PTL syntax structures, where N is an integer, and the processor is configured to execute the instructions to encode the one or more PTL syntax elements in such a way as:

[0355] Set the length of the first PTL syntax element to the smallest integer greater than or equal to the logarithm of N to the base 2.

[0356] 48. The apparatus according to clause 46, wherein the processor is configured to execute the instructions to encode the one or more PTL syntax elements in such a way as:

[0357] The first PTL syntax element is encoded using exponential Golomb codes.

[0358] 49. The apparatus according to Clause 45, wherein the VPS or the SPS comprises N PTL syntax structures, where N is an integer, and the processor is configured to execute the instructions to encode the one or more PTL syntax elements in such a way as:

[0359] The second PTL syntax element, which specifies the N, is encoded using a variable length.

[0360] 50. An apparatus comprising:

[0361] A memory configured to store instructions; and

[0362] A processor, coupled to the memory and configured to execute the instructions to cause the device to:

[0363] Encoding is performed using variable-length Video Parameter Set (VPS) syntax elements; and

[0364] The VPS syntax element is signaled within the VPS, and the VPS syntax element is associated with the number of output layer sets (OLS) contained in the coded video sequence (CVS) of the reference VPS.

[0365] 51. The apparatus according to claim 50, wherein the processor is configured to execute the instructions to:

[0366] When the maximum allowed number of layers in the encoded video sequence (CVS) of the reference VPS is less than a predefined length value, the length of the VPS syntax element is set to be equal to the maximum allowed number.

[0367] 52. An apparatus comprising:

[0368] A memory configured to store instructions; and

[0369] A processor, coupled to the memory and configured to execute the instructions to cause the device to:

[0370] Receive bitstreams including encoded video sequences (CVS);

[0371] Determine whether the CVS has the same number of File, Level, and Grade (PTL) syntax structures and Output Level Sets (OLS); and

[0372] In response to the number of PTL syntax structures being equal to the number of OLS, the decoding of the first PTL syntax element is skipped. The index of the first PTL syntax element, which is applied to the PTL syntax structure of the corresponding OLS when decoding the VPS, is specified in the list of PTL syntax structures in the VPS.

[0373] 53. The apparatus according to clause 52, wherein the processor is configured to execute the instructions to:

[0374] In response to the fact that the number of PTL syntax structures equals the number of OLS, the first PTL syntax element is determined to be equal to the index of the OLS to which the PTL syntax structure specified by the first PTL syntax element is applied.

[0375] 54. The apparatus according to claim 52, wherein the processor is configured to execute the instructions to:

[0376] Determine whether the number of PTL syntax structures is equal to 1; and

[0377] In response to the PTL syntax structure having a quantity of 1, the decoding of the first PTL syntax element is skipped when decoding the VPS.

[0378] 55. The apparatus according to clause 54, wherein the processor is configured to execute the instructions to:

[0379] In response to the fact that the number of PTL syntax structures is equal to 1, the first PTL syntax element is determined to be zero.

[0380] 56. The apparatus according to clause 52, wherein the processor is configured to execute the instructions to:

[0381] In response to the fact that the number of PTL syntax structures is greater than 1 and is different from the number of OLS, the first PTL syntax element is decoded in the VPS with a fixed length.

[0382] 57. An apparatus comprising:

[0383] A memory configured to store instructions; and

[0384] A processor, coupled to the memory and configured to execute the instructions to cause the device to:

[0385] Receive bitstreams including encoded video sequences (CVS);

[0386] Determine whether the CVS has an equal number of decoded image buffers (DPB), parameter syntax structures, and output layer sets (OLS); and

[0387] In response to the CVS having an equal number of DPB parameter syntax structures and OLS, the decoding of the first DPB syntax element is skipped, and the index of the DPB parameter syntax structure applied to the corresponding OLS is assigned to the list of DPB parameter syntax structures in the VPS.

[0388] 58. The apparatus according to clause 57, wherein the processor is configured to execute the instructions to:

[0389] Determine whether the number of the DPB parameter syntax structures is less than or equal to 1; and

[0390] In response to the number of DPB parameter syntax structures being less than or equal to 1, the decoding of the first DPB syntax element is skipped when decoding the VPS.

[0391] 59. The apparatus according to clause 58, wherein the processor is configured to execute the instructions to:

[0392] In response to the fact that the number of DPB parameter syntax structures is less than or equal to 1, the first DPB syntax element is determined to be zero; and

[0393] In response to the fact that the number of DPB syntax structures equals the number of OLS, the first DPB syntax element is determined to be equal to the index of the OLS to which the DPB parameter syntax structure specified by the first DPB syntax element applies.

[0394] 60. The apparatus according to clause 58, wherein the processor is configured to execute the instructions to:

[0395] In response to the fact that the number of DPB parameter syntax structures is greater than 1 and is different from the number of OLS, the first DPB syntax element is decoded in the VPS using a variable length.

[0396] 61. An apparatus comprising:

[0397] A memory configured to store instructions; and

[0398] A processor, coupled to the memory and configured to execute the instructions to cause the device to:

[0399] Receive bitstreams including Video Parameter Set (VPS) and Sequence Parameter Set (SPS);

[0400] In response to at least one of the File, Layer, and Type (PTL) syntax structure, Decoded Picture Buffer (DPB) parameter syntax structure, or Hypothetical Reference Decoder (HRD) parameter syntax structure present in the SPS, a first value is determined to be greater than 1, the first value specifying the maximum number of temporal sub-layers present in each coding layer video sequence (CLVS) referencing the SPS; and

[0401] In response to the first value being greater than 1, the flag configured to control the presence of syntax elements in the DPB parameter syntax structure in the SPS is decoded.

[0402] 62. The apparatus according to clause 61, wherein the processor is configured to execute the instructions to:

[0403] In response to the first value being equal to or less than 1, it is inferred that the flag is equal to zero, and one or more syntax elements in the DPB parameter syntax structure are decoded in the SPS without decoding the flag.

[0404] 63. An apparatus comprising:

[0405] The memory, wherein the processor is configured to store instructions; and

[0406] A processor, coupled to the memory and configured to execute the instructions to cause the device to:

[0407] Determine the value of a first Sequence Parameter Set (SPS) syntax element, wherein the first SPS syntax element specifies an identifier of a Video Parameter Set (VPS) referenced by an SPS when the value of the first SPS syntax element is greater than zero; and

[0408] The second SPS syntax element is decoded, which specifies the maximum number of temporal sub-layers present in each coding layer video sequence (CLVS) referencing the SPS. When the value of the first SPS syntax element is greater than zero, the range of the second SPS syntax element is based on the corresponding VPS syntax element of the VPS referenced by the SPS, or when the value of the first SPS syntax element is equal to zero, the range of the second SPS syntax element is based on a fixed value.

[0409] 64. An apparatus comprising:

[0410] A memory configured to store instructions; and

[0411] A processor, coupled to the memory and configured to execute the instructions to cause the device to:

[0412] Receive bitstreams including Video Parameter Set (VPS) or Sequence Parameter Set (SPS); and

[0413] Decode one or more file, tier, and level (PTL) syntax elements in the VPS or SPS, wherein the one or more PTL syntax elements specify PTL-related information.

[0414] 65. The apparatus according to clause 64, wherein the processor is configured to execute the instructions to decode the one or more PTL syntax elements in such a way as:

[0415] The first PTL syntax element, which specifies the index of the PTL syntax structure, is decoded using a variable length.

[0416] 66. The apparatus according to Clause 65, wherein the VPS or the SPS comprises N PTL syntax structures, N being an integer, and the length of the first PTL syntax element is the smallest integer greater than or equal to the logarithm of N to the base 2.

[0417] 67. The apparatus according to Clause 65, wherein the first PTL syntax element is encoded using exponential Golomb codes.

[0418] 68. The apparatus according to Clause 64, wherein the VPS or the SPS comprises N PTL syntax structures, where N is an integer, and the processor is configured to execute the instructions to decode the one or more PTL syntax elements in such a way as:

[0419] The second PTL syntax element, which specifies N, is decoded using a variable length.

[0420] 69. An apparatus comprising:

[0421] A memory configured to store instructions; and

[0422] A processor, coupled to the memory and configured to execute the instructions to cause the device to:

[0423] Receives a bitstream including a Video Parameter Set (VPS); and

[0424] VPS syntax elements in a VPS are decoded using a variable length, the VPS syntax elements being associated with the number of output layer sets (OLS) contained in a coded video sequence (CVS) referencing the VPS.

[0425] 70. The apparatus according to Clause 69, wherein the length of the VPS syntax element is equal to the maximum allowed number of layers when the maximum allowed number of layers in the encoded video sequence (CVS) referencing the VPS is less than a predefined length value.

[0426] 71. A non-transitory computer-readable storage medium storing a set of instructions executable by one or more processors of a device to cause the device to perform a method for encoding video, comprising:

[0427] Determine whether the encoded video sequence (CVS) contains an equal number of files, layers, and levels (PTL), syntax structure, and output layer set (OLS); and

[0428] In response to the CVS containing an equal number of PTL syntax structures and OLS, the bitstream is encoded without signaling the first PTL syntax element, which assigns the index of the PTL syntax structure corresponding to the OLS in the VPS to the list of PTL syntax structures in the VPS.

[0429] 72. A non-transitory computer-readable storage medium as described in Clause 71, wherein the set of instructions executable by the one or more processors of the device causes the device to further perform:

[0430] Determine whether the number of PTL syntax structures is equal to 1; and

[0431] In response to the PTL syntax structure having a quantity of 1, the bitstream is encoded without signaling the first PTL syntax element in the VPS.

[0432] 73. A non-transitory computer-readable storage medium as described in Clause 71, wherein the set of instructions executable by the one or more processors of the device causes the device to further perform:

[0433] In response to the PTL syntax structure having a number greater than 1 and different from the number of OLS, the first PTL syntax element is notified in the VPS with a signal of fixed length.

[0434] 74. A non-transitory computer-readable storage medium storing a set of instructions executable by one or more processors of a device to cause the device to perform a method for encoding video, comprising:

[0435] Determine whether the encoded video sequence (CVS) has an equal number of decoded image buffers (DPB), parameter syntax structure, and output layer set (OLS); and

[0436] In response to the CVS having an equal number of DPB parameter syntax structures and OLS, the bitstream is encoded without signaling the first DPB syntax element, which assigns the index of the DPB parameter syntax structure to be applied to the corresponding OLS to the list of DPB parameter syntax structures in the VPS.

[0437] 75. A non-transitory computer-readable storage medium as described in Clause 74, wherein the set of instructions executable by the one or more processors of the device causes the device to further perform:

[0438] Determine whether the number of the DPB parameter syntax structures is less than or equal to 1; and

[0439] In response to the number of DPB parameter syntax structures being equal to 1, the bitstream is encoded without signaling the first DPB syntax element in the VPS.

[0440] 76. A non-transitory computer-readable storage medium as described in Clause 74, wherein the set of instructions executable by the one or more processors of the device causes the device to further perform:

[0441] In response to the fact that the number of DPB parameter syntax structures is greater than 1 and is different from the number of OLS, the first DPB syntax element is signaled in the VPS with a variable length.

[0442] 77. A non-transitory computer-readable storage medium storing a set of instructions executable by one or more processors of a device to cause the device to perform a method for encoding video, comprising:

[0443] Determine whether at least one of the following exists in the Sequence Parameter Set (SPS) of the bitstream: File, Level, and Grade (PTL) syntax structure, Decoded Image Buffer (DPB) parameter syntax structure, or Hypothetical Reference Decoder (HRD) parameter syntax structure;

[0444] Determine whether a first value is greater than 1, where the first value specifies the maximum number of temporal sublayers present in the coded layer video sequence (CLVS) of the reference SPS; and

[0445] When at least one of the PTL syntax structure, the DPB parameter syntax structure, or the HRD parameter syntax structure exists in the SPS and the first value is greater than 1, a signal is used to notify the presence of a flag configured to control the presence of a syntax element in the DPB parameter syntax structure in the SPS.

[0446] 78. A non-transitory computer-readable storage medium as described in Clause 77, wherein the set of instructions executable by the one or more processors of the device causes the device to further perform:

[0447] When the first value is equal to or less than 1, one or more syntax elements are signaled in the DPB parameter syntax structure, but the flag is not signaled in the SPS.

[0448] 79. A non-transitory computer-readable storage medium storing a set of instructions executable by one or more processors of a device to cause the device to perform a method for encoding video, comprising:

[0449] Determine the value of a first sequence parameter set (SPS) syntax element, wherein the first SPS syntax element specifies an identifier of a video parameter set (VPS) referenced by the SPS when the value of the first SPS syntax element is greater than zero;

[0450] In response to a value greater than zero for the first SPS syntax element, a range of second SPS syntax elements is allocated based on the corresponding VPS syntax element. The second SPS syntax element specifies the maximum number of temporal sublayers present in each coded layer video sequence (CLVS) referencing the SPS; and

[0451] In response to the first SPS syntax element having a value of zero, the range of the second SPS syntax element is assigned to a closed interval from zero to a fixed value, the second SPS syntax element specifying the maximum number of temporal sublayers present in each CLVS of the reference SPS.

[0452] 80. A non-transitory computer-readable storage medium storing a set of instructions executable by one or more processors of a device to cause the device to perform a method for encoding video, comprising:

[0453] Encode one or more file, level, and grade (PTL) syntax elements that are related to a specified PTL; and

[0454] Use variable-length signaling to notify one or more PTL syntax elements in the bitstream's Video Parameter Set (VPS) or Sequence Parameter Set (SPS).

[0455] 81. A non-transitory computer-readable storage medium as described in Clause 80, wherein the set of instructions executable by the one or more processors of the device causes the device to encode the one or more PTL syntax elements in such a way as:

[0456] The first PTL syntax element is encoded using a variable length, and the first PTL syntax element specifies the index of the PTL syntax structure.

[0457] 82. A non-transitory computer-readable storage medium as described in Clause 81, wherein the VPS or the SPS comprises N PTL syntax structures, where N is an integer, and a set of instructions executable by one or more processors of the device causes the device to encode one or more PTL syntax elements in such a way as:

[0458] Set the length of the first PTL syntax element to the smallest integer greater than or equal to the logarithm of N to the base 2.

[0459] 83. A non-transitory computer-readable storage medium as described in Clause 81, wherein the set of instructions executable by the one or more processors of the device causes the device to encode the one or more PTL syntax elements in such a way as:

[0460] The first PTL syntax element is encoded using exponential Golomb codes.

[0461] 84. A non-transitory computer-readable storage medium as described in Clause 80, wherein the VPS or the SPS comprises N PTL syntax structures, where N is an integer, and a set of instructions executable by one or more processors of the device causes the device to encode one or more PTL syntax elements in such a way as:

[0462] The second PTL syntax element, which specifies the N, is encoded using a variable length.

[0463] 85. A non-transitory computer-readable storage medium storing a set of instructions executable by one or more processors of a device to cause the device to perform a method for encoding video, comprising:

[0464] Encoding is performed using variable-length Video Parameter Set (VPS) syntax elements; and

[0465] The VPS syntax element is signaled within the VPS, and the VPS syntax element is associated with the number of output layer sets (OLS) contained in the coded video sequence (CVS) of the reference VPS.

[0466] 86. A non-transitory computer-readable storage medium as described in Clause 85, wherein the set of instructions executable by the one or more processors of the device causes the device to further perform:

[0467] When the maximum allowed number of layers in the encoded video sequence (CVS) of the reference VPS is less than a predefined length value, the length of the VPS syntax element is set to be equal to the maximum allowed number.

[0468] 87. A non-transitory computer-readable storage medium storing a set of instructions executable by one or more processors of a device to cause the device to perform a method for decoding video, comprising:

[0469] Receive bitstreams including encoded video sequences (CVS);

[0470] Determine if the CVS has the same number of file, level, and grade (PTL) syntax structures and output level sets (OLS); and

[0471] In response to the number of PTL syntax structures being equal to the number of OLS, the decoding of the first PTL syntax element is skipped. The index of the first PTL syntax element, which is applied to the PTL syntax structure of the corresponding OLS when decoding the VPS, is specified in the list of PTL syntax structures in the VPS.

[0472] 88. A non-transitory computer-readable storage medium as described in Clause 87, wherein the set of instructions executable by the one or more processors of the device causes the device to further perform:

[0473] In response to the fact that the number of PTL syntax structures equals the number of OLS, the first PTL syntax element is determined to be equal to the index of the OLS to which the PTL syntax structure specified by the first PTL syntax element applies.

[0474] 89. A non-transitory computer-readable storage medium as described in Clause 87, wherein the set of instructions executable by the one or more processors of the device causes the device to further perform:

[0475] Determine whether the number of PTL syntax structures is equal to 1; and

[0476] In response to the PTL syntax structure having a quantity of 1, the decoding of the first PTL syntax element is skipped when decoding the VPS.

[0477] 90. A non-transitory computer-readable storage medium as described in Clause 89, wherein the set of instructions executable by the one or more processors of the device causes the device to further perform:

[0478] In response to the fact that the number of PTL syntax structures is equal to 1, the first PTL syntax element is determined to be zero.

[0479] 91. A non-transitory computer-readable storage medium as described in Clause 87, wherein the set of instructions executable by the one or more processors of the device causes the device to further perform:

[0480] In response to the fact that the number of PTL syntax structures is greater than 1 and is different from the number of OLS, the first PTL syntax element is decoded in the VPS with a fixed length.

[0481] 92. A non-transitory computer-readable storage medium storing a set of instructions executable by one or more processors of a device to cause the device to perform a method for decoding video, comprising:

[0482] Receive bitstreams including encoded video sequences (CVS);

[0483] Determine whether the CVS has an equal number of decoded image buffers (DPB), parameter syntax structures, and output layer sets (OLS); and

[0484] In response to the CVS having an equal number of DPB parameter syntax structures and OLS, the decoding of the first DPB syntax element is skipped, and the index of the DPB parameter syntax structure applied to the corresponding OLS is assigned to the list of DPB parameter syntax structures in the VPS.

[0485] 93. A non-transitory computer-readable storage medium as described in Clause 92, wherein the set of instructions executable by the one or more processors of the device causes the device to further perform:

[0486] Determine whether the number of the DPB parameter syntax structures is less than or equal to 1; and

[0487] In response to the number of DPB parameter syntax structures being less than or equal to 1, the decoding of the first DPB syntax element is skipped when decoding the VPS.

[0488] 94. A non-transitory computer-readable storage medium as described in Clause 93, wherein the set of instructions executable by the one or more processors of the device causes the device to further perform:

[0489] In response to the fact that the number of DPB parameter syntax structures is less than or equal to 1, the first DPB syntax element is determined to be zero; and

[0490] In response to the fact that the number of DPB syntax structures equals the number of OLS, the first DPB syntax element is determined to be equal to the index of the OLS to which the DPB parameter syntax structure specified by the first DPB syntax element applies.

[0491] 95. A non-transitory computer-readable storage medium as described in Clause 93, wherein the set of instructions executable by the one or more processors of the device causes the device to further perform:

[0492] In response to the fact that the number of DPB parameter syntax structures is greater than 1 and is different from the number of OLS, the first DPB syntax element is decoded in the VPS using a variable length.

[0493] 96. A non-transitory computer-readable storage medium storing a set of instructions executable by one or more processors of a device to cause the device to perform a method for decoding video, comprising:

[0494] Receive bitstreams including Video Parameter Set (VPS) and Sequence Parameter Set (SPS);

[0495] In response to at least one of the File, Layer, and Type (PTL) syntax structure, Decoded Picture Buffer (DPB) parameter syntax structure, or Hypothetical Reference Decoder (HRD) parameter syntax structure present in the SPS, a first value is determined to be greater than 1, the first value specifying the maximum number of temporal sub-layers present in each coding layer video sequence (CLVS) referencing the SPS; and

[0496] In response to the first value being greater than 1, the flag configured to control the presence of syntax elements in the DPB parameter syntax structure in the SPS is decoded.

[0497] 97. A non-transitory computer-readable storage medium as described in Clause 96, wherein the set of instructions executable by the one or more processors of the device causes the device to further perform:

[0498] In response to the first value being equal to or less than 1, it is inferred that the flag is equal to zero, and one or more syntax elements in the DPB parameter syntax structure are decoded in the SPS without decoding the flag.

[0499] 98. A non-transitory computer-readable storage medium storing a set of instructions executable by one or more processors of a device to cause the device to perform a method for decoding video, comprising:

[0500] Determine the value of a first Sequence Parameter Set (SPS) syntax element, wherein the first SPS syntax element specifies an identifier of the Video Parameter Set (VPS) referenced by the SPS when the value of the first SPS syntax element is greater than zero; and

[0501] The second SPS syntax element is decoded, which specifies the maximum number of temporal sub-layers present in each coding layer video sequence (CLVS) of the reference SPS. When the value of the first SPS syntax element is greater than zero, the range of the second SPS syntax element is based on the corresponding VPS syntax element of the VPS referenced by the SPS, or when the value of the first SPS syntax element is equal to zero, the range of the second SPS syntax element is based on a fixed value.

[0502] 99. A non-transitory computer-readable storage medium storing a set of instructions executable by one or more processors of a device to cause the device to perform a method for decoding video, comprising:

[0503] Receive bitstreams including Video Parameter Set (VPS) or Sequence Parameter Set (SPS); and

[0504] Decode one or more file, tier, and level (PTL) syntax elements in the VPS or SPS, wherein the one or more PTL syntax elements specify PTL-related information.

[0505] 100. A non-transitory computer-readable storage medium as described in Clause 99, wherein the set of instructions executable by the one or more processors of the device causes the device to decode the one or more PTL syntax elements in such a way that:

[0506] The first PTL syntax element, which specifies the index of the PTL syntax structure, is decoded using a variable length.

[0507] 101. The non-transitory computer-readable storage medium according to Clause 100, wherein the VPS or the SPS comprises N PTL syntax structures, where N is an integer, and the length of the first PTL syntax element is the smallest integer greater than or equal to the logarithm of N to the base 2.

[0508] 102. The non-transitory computer-readable storage medium as described in Clause 100, wherein the first PTL syntax element is encoded using exponential Golomb code.

[0509] 103. A non-transitory computer-readable storage medium as described in Clause 99, wherein the VPS or the SPS comprises N PTL syntax structures, where N is an integer, and a set of instructions executable by one or more processors of the device causes the device to decode one or more PTL syntax elements in such a way that:

[0510] The second PTL syntax element, which specifies N, is decoded using a variable length.

[0511] 104. A non-transitory computer-readable storage medium storing an instruction set, the instruction set being executable by one or more processors of a device to cause the device to perform a method for decoding video, comprising:

[0512] Receives a bitstream including a Video Parameter Set (VPS); and

[0513] VPS syntax elements in a VPS are decoded using a variable length, the VPS syntax elements being associated with the number of output layer sets (OLS) contained in a coded video sequence (CVS) referencing the VPS.

[0514] 105. A non-transitory computer-readable storage medium as described in Clause 104, wherein the length of the VPS syntax element is equal to the maximum allowed number of layers when the maximum allowed number of layers in the encoded video sequence (CVS) of the VPS is less than a predefined length value.

[0515] In some embodiments, a non-transitory computer-readable storage medium including instructions is also provided, and these instructions can be executed by a device (such as the disclosed encoder and decoder) to perform the methods described above. Common forms of non-transitory media include, for example, floppy disks, hard disks, solid-state drives, magnetic tape or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a perforated pattern, RAM, PROMs and EPROMs, FLASH-EPROMs or any other flash memory, NVRAM, caches, registers, any other memory chips or cassettes, and their networking versions. The device may include one or more processors (CPUs), input / output interfaces, network interfaces, and / or memory.

[0516] It should be noted that relational terms such as “first” and “second” in this document are used only to distinguish an entity or operation from another entity or operation, and do not require or imply any actual relationship or order between these entities or operations. Furthermore, the words “including,” “having,” “containing,” and “comprising,” and other similar forms are semantically equivalent and open-ended, because one or more items following any of these words do not imply an exhaustive list of such items, or that the list is limited to one or more items.

[0517] As used herein, unless otherwise specified, the term "or" includes all possible combinations except where impractical. For example, if a database is declared to include A or B, then unless otherwise expressly stated or impractical, the database may include A, or B, or A and B. As a second example, if a database is declared to include A, B, or C, then unless otherwise expressly stated or impractical, the database may include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C.

[0518] It should be understood that the above embodiments can be implemented by hardware, software (program code), or a combination of hardware and software. If implemented by software, it can be stored on the above-described computer-readable medium. The software, when executed by a processor, can perform the disclosed methods. The computing units and other functional units described in this disclosure can be implemented by hardware, software, or a combination of hardware and software. Those skilled in the art will also understand that the above-described multiple modules / units can be combined into one module / unit, and each of the above-described modules / units can be further divided into multiple sub-modules / sub-units.

[0519] In the foregoing description, numerous specific details have been described with reference to embodiments, which may vary as implementation progresses. Certain modifications and changes may be made to the described embodiments. Other embodiments will be apparent to those skilled in the art upon consideration of the specification and practice disclosed herein. This specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the appended claims. The sequence of steps shown in the accompanying drawings is for illustrative purposes only and is not intended to limit one to any particular sequence of steps. Therefore, those skilled in the art will understand that these steps may be performed in a different order while implementing the same method.

[0520] Exemplary embodiments have been disclosed in the accompanying drawings and description. However, many variations and modifications can be made to these embodiments. Therefore, although specific terminology has been used, it is used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A computer-implemented video encoding method, comprising: Determine whether the encoded video sequence (CVS) contains an equal number of decoded image buffers (DPB), parameter syntax structure, and output layer set (OLS); and In response to the CVS containing an equal number of DPB parameter syntax structures and OLS, the bitstream is encoded without signaling the first DPB syntax element, which assigns the index of the DPB parameter syntax structure applied to the corresponding OLS to the list of DPB parameter syntax structures in the Video Parameter Set (VPS).

2. The method according to claim 1, characterized in that, Also includes: Determine whether the number of the DPB parameter syntax structures is less than or equal to 1; and In response to the number of DPB parameter syntax structures being equal to 1, the bitstream is encoded without signaling the first DPB syntax element in the VPS.

3. The method according to claim 1, further comprising: In response to the fact that the number of DPB parameter syntax structures is greater than 1 and is different from the number of OLS, the first DPB syntax element is notified in the VPS with a variable length signal.

4. The method according to claim 1, further comprising: In response to the fact that the CVS contains an equal number of file, level, and grade (PTL) syntax structures and OLS, the bitstream is encoded without signaling a first PTL syntax element, which assigns an index of the PTL syntax structure corresponding to the OLS in the VPS to a list of PTL syntax structures in the VPS.

5. The method according to claim 4, further comprising: Determine whether the number of PTL syntax structures is equal to 1; and In response to the PTL syntax structure having a quantity of 1, the bitstream is encoded without signaling the first PTL syntax element in the VPS.

6. The method according to claim 4, further comprising: In response to the PTL syntax structure having a number greater than 1 and different from the number of OLS, the first PTL syntax element is notified in the VPS with a signal of fixed length.

7. A computer-implemented video decoding method, comprising: Receive bitstreams including encoded video sequences (CVS); Determine whether the encoded video sequence (CVS) contains the same number of decoded image buffers (DPB), parameter syntax structure, and output layer set (OLS); and In response to the fact that the CVS contains an equal number of DPB parameter syntax structures and OLS, the decoding of the first DPB syntax element is skipped. The index of the first DPB syntax element applied to the DPB parameter syntax structure of the corresponding OLS when decoding the video parameter set (VPS) is specified to the list of DPB parameter syntax structures in the VPS.

8. The method according to claim 7, further comprising: Determine whether the number of the DPB parameter syntax structures is less than or equal to 1; and In response to the number of DPB parameter syntax structures being equal to 1, the decoding of the first DPB syntax element is skipped when decoding the VPS.

9. The method according to claim 8, further comprising: In response to the fact that the number of DPB parameter syntax structures is equal to 1, the first DPB syntax element is determined to be zero.

10. The method of claim 7, further comprising: In response to the fact that the number of DPB parameter syntax structures is greater than 1 and is different from the number of OLS, the first DPB syntax element is decoded in the VPS with a variable length.

11. The method according to claim 7, characterized in that, Also includes: In response to the CVS containing an equal number of file, layer, and level (PTL) syntax structures and OLS, the bitstream is decoded, skipping the decoding of the first PTL syntax element, which will be used as an index of the PTL parameter syntax structure in the corresponding OLS when decoding the video parameter set (VPS) to the list of PTL parameter syntax structures in the VPS.

12. The method according to claim 11, further comprising: Determine whether the number of PTL syntax structures is equal to 1; and In response to the PTL syntax structure having a quantity equal to 1, the bitstream is decoded, and the decoding of the first PTL syntax element is skipped in the VPS.

13. A computer-readable storage medium storing a bitstream of video, the bitstream being generated by a method performed by a video processing apparatus, the method comprising: Determine whether the encoded video sequence (CVS) contains an equal number of decoded image buffers (DPB), parameter syntax structure, and output layer set (OLS); and In response to the CVS containing an equal number of DPB parameter syntax structures and OLS, the bitstream is encoded without signaling the first DPB syntax element, which assigns the index of the DPB parameter syntax structure applied to the corresponding OLS to the list of DPB parameter syntax structures in the Video Parameter Set (VPS).

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