Parallel simulation test method and related equipment based on HIL test system

Abstract

The present application provides a parallel simulation test method and related equipment based on a HIL test system. The HIL system includes a host computer, a slave computer and multiple controllers. The method includes: constructing multiple vehicle models through the host computer, and adjusting the internal parameters of the multiple vehicle models according to the simulation requirements to obtain multiple vehicle simulation models; using the host computer to compile the multiple vehicle simulation models; writing the compiled multiple vehicle simulation models into each of the multiple cores of the HIL test system slave computer, wherein the vehicle simulation model corresponds to the controller one-to-one; using inter-process communication IPC to establish information interaction between the multiple cores; using multiple controllers to respectively control all the vehicle simulation models in the multiple cores that have achieved information interaction to perform tests, and obtain simulation test results. Through the above method, parallel simulation testing is achieved, the resource utilization rate of the HIL test equipment is improved, and the application scope of the HIL test system is expanded.

Description

Technical Field

[0001] The present application relates to the technical field of simulation testing, and in particular to a parallel simulation testing method and related equipment based on a HIL test system. Background Art

[0002] In the automotive, aerospace, and other industrial fields requiring electronic control, HIL (Hardware-in-the-loop) simulation testing is often used to test the code in the controller. By combining the actual controller control with the virtual object model simulated by the HIL test system for testing, compared with the traditional test method in which the controller directly controls the actual equipment for testing, the HIL test system can shorten the development cycle, reduce testing costs, and reduce testing risks.

[0003] When conducting tests in existing HIL test systems, only one external controller can be connected for serial testing, resulting in low resource utilization of HIL test equipment. A single controller can only control one controlled object and cannot complete interactive testing between multiple controlled objects, limiting the application scope of HIL testing. Summary of the Invention

[0004] In view of this, the purpose of this application is to propose a parallel simulation test method and related equipment based on a HIL test system to solve or partially solve the above technical problems.

[0005] Based on the above objectives, the present application provides a parallel simulation test method based on a HIL test system, wherein the HIL system includes a host computer, a slave computer, and multiple controllers, and the method includes:

[0006] Constructing multiple vehicle models through the host computer, and adjusting internal parameters of the multiple vehicle models according to simulation requirements to obtain multiple vehicle simulation models;

[0007] Compiling the multiple vehicle simulation models using the host computer;

[0008] Writing the compiled multiple vehicle simulation models into each of the multiple cores of the HIL test system slave computer, wherein the vehicle simulation models correspond one-to-one to the controllers;

[0009] Using inter-process communication (IPC) to establish information interaction between the multiple cores;

[0010] The multiple controllers are used to respectively control all vehicle simulation models in the multiple cores that have realized the information interaction to perform testing and obtain simulation test results.

[0011] Based on the same inventive concept, the present application also provides a parallel simulation test device based on a HIL test system, comprising:

[0012] A construction module is configured to: construct a plurality of vehicle models through the host computer, and adjust internal parameters of the plurality of vehicle models according to simulation requirements to obtain a plurality of vehicle simulation models;

[0013] A compiling module is configured to: compile the plurality of vehicle simulation models using the host computer;

[0014] A configuration module is configured to: write the compiled multiple vehicle simulation models into each of the multiple cores of the HIL test system lower computer, wherein the vehicle simulation models correspond one-to-one to the controller;

[0015] The interaction module is configured to: establish information interaction between the multiple cores using inter-process communication (IPC);

[0016] The test module is configured to: use the multiple controllers to respectively control all the vehicle simulation models in the multiple cores that have realized the information interaction to perform tests and obtain simulation test results.

[0017] Based on the same inventive concept, the present application also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor implements the method described above when executing the computer program.

[0018] Based on the same inventive concept, the present application also provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable a computer to execute the method as described above.

[0019] From the above, it can be seen that the parallel simulation test method and related equipment based on the HIL test system provided by this application compile multiple pre-built vehicle simulation models and write them into different cores of the HIL test system's lower computer, and make the controller correspond to the vehicle simulation model one-to-one. Each controller controls a vehicle simulation model to run according to the control logic in the controller, thereby improving the resource utilization of the HIL test equipment. At the same time, the information interaction channel between multiple cores using inter-process communication IPC is used to enable information interaction between multiple vehicle simulation models, thereby realizing all-round multi-controller parallel interactive testing and expanding the application scope of HIL testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in this application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are merely embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 This is a flowchart of a parallel simulation test method based on a HIL test system according to an embodiment of the present application;

[0022] Figure 2 Schematic diagram of the HIL parallel simulation test system according to an embodiment of the present application;

[0023] Figure 3 This is a structural diagram of a parallel simulation test device based on a HIL test system according to an embodiment of the present application;

[0024] Figure 4 This is a structural diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the objectives, technical solutions and advantages of this application more clear, this application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0026] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the usual meanings understood by people with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in the embodiments of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0027] As can be seen from the background technology, when testing the HIL test system, only one external controller can be connected for serial testing. A single controller can only control one controlled object, resulting in low resource utilization of HIL test equipment and the inability to perform comprehensive multi-controller parallel interactive testing, which limits the application scope of HIL testing.

[0028] In order to solve the problems existing in the related technologies, this application compiles multiple pre-built vehicle simulation models and distributes them to different cores of the real-time parameter control processor of the HIL test system's lower computer, and makes the controller correspond to the vehicle simulation model one-to-one. Each controller controls a vehicle simulation model to run according to the control logic in the controller, thereby improving the resource utilization of the HIL test equipment. At the same time, the inter-process communication IPC information interaction channel between multiple cores is used to enable multiple vehicle simulation models to exchange information during the test process, thereby realizing all-round multi-controller parallel interactive testing and expanding the application scope of HIL testing.

[0029] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0030] This application provides a parallel simulation test method based on a HIL test system, which includes a host computer, a slave computer and multiple controllers. Figure 1 , Figure 2 , the method comprises the following steps:

[0031] Step S100: constructing multiple vehicle models through a host computer, and adjusting internal parameters of the multiple vehicle models according to simulation requirements to obtain multiple vehicle simulation models;

[0032] The host computer refers to a computer or single-chip microcomputer that can directly send operating instructions. Common host computers include: computers, tablets, panels and touch screens. The host computer can be used to run Simulink to build a whole vehicle model. According to the test requirements, the whole vehicle model can be copied to obtain multiple whole vehicle models. According to the need to simulate different types of vehicles, the internal parameters are adjusted to obtain a whole vehicle simulation model that meets the simulation requirements. Among them, Simulink is a visual simulation tool used for multi-domain simulation and model design.

[0033] Step S200: compiling multiple vehicle simulation models using a host computer;

[0034] The multiple vehicle simulation models constructed cannot be directly input into the lower computer. The vehicle simulation models need to be compiled into code and then written into the core of the corresponding processor of the lower computer. Before compilation, it is necessary to confirm that the vehicle simulation model constructed by Simulink can complete the simulation and discretize the continuous modules in the simulation model. The purpose of discretization is to reduce time complexity. After confirmation, the Simulink Coder toolbox can convert the model into optimizable embedded C code. To generate embedded code, at least three parts need to be configured: model solver, model system target file and hardware implementation regulations. The model solver type is selected as a fixed-step solver. The system target file of the model can be selected as ert.tlc. ert.tlc is a system target file provided by the Coder toolbox specifically for embedded system C code. The hardware implementation regulations require the configuration of the chip manufacturer and type. Here, the manufacturer and type of the lower computer RTPC (Real-time Parameter Controls) processor can be selected.

[0035] Step S300: writing the compiled multiple vehicle simulation models into each of the multiple cores of the HIL test system's lower computer, wherein the vehicle simulation models correspond one-to-one to the controllers;

[0036] The existing HIL test system can only test a single model. During the test, the processor schedules the model, but it can only run on a fixed core, where the core refers to the logical operation core on the processor. The present application allocates multiple compiled vehicle simulation models to different cores and prohibits the processor from dynamically allocating the models, so that each model runs in its assigned core. For example, based on the number of vehicle simulation models, multiple cores are isolated, and the isolcpus instruction can be used to isolate a specific core so that the processor cannot schedule its process. After verifying that the specific core is isolated, the compiled multiple vehicle simulation model codes are written into different cores, and the taskset instruction is used to bind them to the corresponding cores, so that a vehicle simulation model can run independently in each core.

[0037] Step S400: using inter-process communication (IPC) to establish information exchange between multiple cores;

[0038] If interactive simulation of multiple vehicle simulation models in multiple cores controlled by different controllers is required during the test process, information interaction between multiple cores must be implemented. This application uses IPC (Inter-Process Communication) to implement information interaction between multiple cores. The types of IPC include: half-duplex Unix pipes, named pipes, message queues, semaphores, shared memory, and network sockets. When performing interactive simulation of multiple vehicle simulation models, high real-time requirements for information and data interaction are required. The most efficient shared memory method in IPC can be selected to implement information interaction between multiple cores. Shared memory refers to a special area in the core as a memory area. Other cores that need to interact with information map it to their own private address space, so that multiple cores can directly read and write the same memory space to achieve information exchange.

[0039] Step S500: using multiple controllers to respectively control all vehicle simulation models in multiple cores that have achieved information interaction to perform testing and obtain simulation test results.

[0040] Multiple controllers control all vehicle simulation models for parallel simulation, which can be divided into two categories: the first category is that multiple controllers control the vehicle simulation models in the corresponding cores to run independently, without information interaction between each other. The purpose of independent operation of multiple models is to improve the utilization rate of hardware resources of the HIL test system; the second category is that multiple controllers control the vehicle simulation models in the corresponding cores to run independently. During the operation, different vehicle simulation models interact with each other. The purpose of interaction is to simulate the interaction scenario of multiple vehicle simulation models and expand the application scope of HIL testing.

[0041] As an optional embodiment, the parallel simulation test method based on the HIL test system provided by the present application is provided with a plurality of I / O interfaces for connecting to the controller on the lower computer.

[0042] The lower computer is equipped with multiple I / O interfaces, which can connect multiple controllers at the same time. The I / O interfaces are responsible for connecting the I / O circuits and controllers together.

[0043] As an optional embodiment, the present application provides a parallel simulation test method based on the HIL test system, in which the whole vehicle model includes: an engine model, a transmission system model, a battery system, an environmental model, a driver model and a vehicle dynamics model.

[0044] To realize vehicle operation, the whole vehicle dynamics model should at least include the engine model, transmission system model and vehicle dynamics model. The vehicle interacts with the environment during operation, and the environment model and driver model need to be established. If the controller needs to control other parts of the vehicle, the corresponding model can be added. For example, if the controller controls the lifting and lowering of the window, the window model needs to be added to the whole vehicle model. After all models are selected, different models and controllers are connected according to the information transmission relationship. For example, the torque generated by the engine will be transmitted to the transmission system, so a connection is established between the engine model and the transmission system model.

[0045] As an optional embodiment, the parallel simulation test method based on the HIL test system provided in the present application compiles multiple vehicle simulation models and writes them into each of the multiple cores of the HIL test system's lower computer, including: determining the interaction signals between the multiple cores.

[0046] The whole vehicle simulation model will generate multiple types of signals during operation, but only specific types of signals are required in the interactive simulation test of multiple whole vehicle simulation models, such as vehicle speed signals and vehicle head angle signals. When the whole vehicle simulation model is compiled and written into the core of the lower computer of the HIL test system, the interactive signals between multiple cores are determined. When the interactive simulation test of multiple whole vehicle simulation models is carried out, only the interactive signals of the determined types will be written into the memory space shared by multiple cores, so that the interactive process of multiple vehicle simulation models can ensure better real-time performance.

[0047] As an optional embodiment, the present application provides a parallel simulation test method based on the HIL test system, in which the lower computer is connected to a real sensor or a real actuator.

[0048] When some sensors or actuators cannot be effectively simulated, the lower computer can be connected to real sensors or actuators. The signals of the real sensors and real actuators can be controlled or read by the real-time system and then participate in the model operation.

[0049] As an optional embodiment, the present application provides a parallel simulation test method based on the HIL test system, in which the lower computer includes: a programmable power supply, an IO signal board, a communication board, a signal conditioning unit and an RTPC processor, and the RTPC processor includes multiple cores.

[0050] To ensure the operation of the simulation test process, the lower computer must at least include a programmable power supply, an IO signal board, a communication board, a signal conditioning unit and an RTPC processor. The RTPC processor is a processor that runs the controlled vehicle simulation model to simulate the vehicle status. The RTPC processor has multiple cores and can simulate the status of multiple vehicles at the same time in this application. The IO signal board and the communication board are responsible for realizing the information interaction between the controller and the vehicle simulation model. The signal conditioning unit is responsible for unifying the electrical specifications of the controller interface with the electrical specifications of the IO signal board and the communication board. The programmable power supply is responsible for simulating the power supply of the vehicle power supply.

[0051] As an optional embodiment, the present application provides a parallel simulation test method based on the HIL test system, in which the controller and the vehicle simulation model communicate through digital signals or hard-wired signals.

[0052] The controller needs to control the vehicle simulation model to run according to the control logic or algorithm in the controller. The controller and the vehicle simulation model must communicate, and the communication information can be transmitted through digital signals or hard-wired signals. Digital signals include CAN and vehicle Ethernet, and hard-wired signals include IO signals.

[0053] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied in a distributed scenario and performed by multiple devices working together. In such a distributed scenario, one of the multiple devices may only perform one or more steps of the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the method.

[0054] It should be noted that the above description is limited to some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in an order different from that described in the above embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0055] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a parallel simulation test device based on the HIL test system.

[0056] refer to Figure 3 The parallel simulation test device based on the HIL test system includes:

[0057] The construction module 11 is configured to: construct a plurality of vehicle models through the host computer, and adjust the internal parameters of the plurality of vehicle models according to simulation requirements to obtain a plurality of vehicle simulation models;

[0058] The compiling module 12 is configured to: compile the plurality of vehicle simulation models using the host computer;

[0059] The configuration module 13 is configured to: write the compiled multiple vehicle simulation models into each of the multiple cores of the HIL test system lower computer, wherein the vehicle simulation models correspond one-to-one to the controller;

[0060] The interaction module 14 is configured to: establish information interaction between the multiple cores using inter-process communication (IPC);

[0061] The testing module 15 is configured to: use the multiple controllers to respectively control all vehicle simulation models in the multiple cores that have achieved the information interaction to perform testing, and obtain simulation test results.

[0062] As an optional embodiment, the configuration module 13 is further configured to: determine the interaction signals between the multiple cores.

[0063] As an optional embodiment, the lower computer is externally provided with a plurality of I / O interfaces for connecting to the controller.

[0064] As an optional embodiment, the whole vehicle model includes: an engine model, a transmission system model, a battery model, an environment model, a driver model and a vehicle dynamics model.

[0065] As an optional embodiment, the lower computer is connected to a real sensor or a real actuator.

[0066] As an optional embodiment, the lower computer includes: a programmable power supply, an IO signal board, a communication board, a signal conditioning unit and an RTPC processor, and the RTPC processor includes the multiple cores.

[0067] As an optional embodiment, the controller communicates with the vehicle simulation model via digital signals or hard-wired signals.

[0068] For the convenience of description, the above devices are described as being divided into various modules according to their functions. Of course, when implementing this application, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0069] The device of the above embodiment is used to implement the corresponding parallel simulation test method based on the HIL test system in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0070] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and runnable on the processor. When the processor executes the program, it implements the parallel simulation test method based on the HIL test system described in any of the above embodiments.

[0071] Figure 4 10 is a schematic diagram showing a more specific hardware structure of an electronic device provided in this embodiment. The device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are communicatively connected to each other within the device via the bus 1050.

[0072] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0073] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage devices, dynamic storage devices, etc. The memory 1020 can store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0074] The input / output interface 1030 is used to connect input / output modules to implement information input and output. The input / output modules can be configured as components within the device (not shown in the figure) or can be externally connected to the device to provide corresponding functions. Input devices may include a keyboard, mouse, touch screen, microphone, various sensors, etc., and output devices may include a display, speaker, vibrator, indicator light, etc.

[0075] The communication interface 1040 is used to connect to a communication module (not shown) to enable communication between the device and other devices. The communication module can communicate via a wired method (such as USB, network cable, etc.) or a wireless method (such as mobile network, WiFi, Bluetooth, etc.).

[0076] The bus 1050 comprises a pathway for transmitting information between the various components of the device (eg, the processor 1010 , the memory 1020 , the input / output interface 1030 , and the communication interface 1040 ).

[0077] It should be noted that although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040, and the bus 1050, in a specific implementation, the device may also include other components necessary for normal operation. In addition, it will be understood by those skilled in the art that the above device may only include the components necessary to implement the embodiments of this specification, and does not necessarily include all the components shown in the figure.

[0078] The electronic device of the above embodiment is used to implement the corresponding parallel simulation test method based on the HIL test system in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be repeated here.

[0079] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute the parallel simulation test method based on the HIL test system as described in any of the above embodiments.

[0080] The computer-readable media of this embodiment include permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. The information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0081] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute the parallel simulation test method based on the HIL test system as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0082] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. Within the scope of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0083] In addition, for simplicity of description and discussion, and in order not to make the embodiment of the application difficult to understand, the known power supply / ground connection with integrated circuit (IC) chip and other components may or may not be shown in the accompanying drawings provided. In addition, the device can be shown in the form of a block diagram to avoid making the embodiment of the application difficult to understand, and this also takes into account the following fact, that is, the details of the embodiment of these block diagram devices are highly dependent on the platform to be implemented in the embodiment of the application (that is, these details should be fully within the scope of understanding of those skilled in the art). When specific details (for example, circuit) are set forth to describe exemplary embodiments of the application, it will be apparent to those skilled in the art that the embodiment of the application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0084] Although the present invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may utilize the embodiments discussed.

[0085] The embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of this application.

Claims

1. A parallel simulation test method based on a HIL test system, wherein the HIL test system includes a host computer, a slave computer, and multiple controllers, characterized in that: The method comprises: Constructing multiple vehicle models through the host computer and adjusting the internal parameters of the multiple vehicle models according to the simulation requirements to obtain multiple vehicle simulation models; wherein each controller controls a vehicle simulation model to operate according to the control logic in the controller; Compiling the multiple vehicle simulation models using the host computer; Writing the compiled multiple vehicle simulation models into each of the multiple cores of the HIL test system's lower computer, including: isolating a specific core using the isolcpus instruction so that the processor cannot schedule a process on it; after verifying that the specific core is isolated, writing the compiled multiple vehicle simulation model codes into different cores and binding them to the corresponding cores using the taskset instruction; wherein the vehicle simulation models correspond one-to-one to the multiple controllers, and each core independently runs a vehicle simulation model; Using inter-process communication (IPC) to establish information interaction between the multiple cores; The multiple controllers are used to respectively control all vehicle simulation models in the multiple cores that have realized the information interaction to perform testing and obtain simulation test results.

2. The parallel simulation test method based on the HIL test system according to claim 1, characterized in that: The lower computer is externally provided with a plurality of I / O interfaces for connecting to the controller.

3. The parallel simulation test method based on the HIL test system according to claim 1, characterized in that: The whole vehicle model includes: an engine model, a transmission system model, a battery system, an environment model, a driver model and a vehicle dynamics model.

4. The parallel simulation test method based on the HIL test system according to claim 1, characterized in that: After compiling, multiple vehicle simulation models are written into each of multiple cores of a lower computer of an HIL test system, including: determining interaction signals between the multiple cores.

5. The parallel simulation test method based on the HIL test system according to claim 1, characterized in that: The lower computer is connected to a real sensor or a real actuator.

6. The parallel simulation test method based on the HIL test system according to claim 1, characterized in that: The lower computer includes: a programmable power supply, an IO signal board, a communication board, a signal conditioning unit and an RTPC processor, and the RTPC processor includes the multiple cores.

7. The parallel simulation test method based on the HIL test system according to claim 1, characterized in that: The controller communicates with the vehicle simulation model via digital signals or hard-wired signals.

8. A parallel simulation test device based on a HIL test system, wherein the HIL test system includes a host computer, a slave computer, and multiple controllers, characterized in that: include: A construction module is configured to: construct a plurality of vehicle models through the host computer, and adjust internal parameters of the plurality of vehicle models according to simulation requirements to obtain a plurality of vehicle simulation models; A compiling module is configured to: compile the plurality of vehicle simulation models using the host computer; The configuration module is configured to: write the compiled multiple vehicle simulation models into each of the multiple cores of the HIL test system's lower computer, including: using the isolcpus instruction to isolate a specific core so that the processor cannot schedule a process on it; after verifying that the specific core is isolated, write the compiled multiple vehicle simulation model codes into different cores and bind them to the corresponding cores using the taskset instruction; wherein the vehicle simulation models correspond one-to-one to the multiple controllers, and each core independently runs a vehicle simulation model; The interaction module is configured to: establish information interaction between the multiple cores using inter-process communication (IPC); The test module is configured to: use the multiple controllers to respectively control all the vehicle simulation models in the multiple cores that have realized the information interaction to perform tests and obtain simulation test results.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 7 when executing the program. 10 . A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are configured to cause a computer to execute the method according to claim 1 .

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