Circuit layout structure verification method, device, storage medium and equipment

Abstract

The present disclosure relates to the field of semiconductors and integrated circuits, and provides a method, device, storage medium and equipment for verifying a circuit layout structure. The method for verifying the circuit layout structure includes: obtaining layout data and initial circuit diagram data corresponding to the layout data, the initial circuit diagram data including multiple identical repeating unit structures, and the repeating unit structure including multiple devices; replacing the repeating unit structure in the initial circuit diagram data with a target device to obtain the target circuit diagram data; performing LVS verification according to the target circuit diagram data and the layout data. The verification method provided by the present disclosure can directly identify the repeating unit structure in the layout data as a target device without specifically identifying the internal devices of the repeating unit structure, thereby reducing the recognition time for the layout data and improving the LVS verification efficiency. When the layout data contains a large number of repeating unit structures, the LVS verification efficiency of the layout data can be greatly improved by the method disclosed in the present disclosure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors and integrated circuits, and in particular, to a circuit layout structure verification method, device, storage medium and equipment. Background Art

[0002] In a typical integrated circuit design process, for example, a circuit schematic of an integrated circuit is first generated in a schematic compiler. A pre-layout simulation is performed to ensure that the schematic of the integrated circuit can meet the design specifications. After the pre-layout simulation, a layout of the integrated circuit is generated, for example, using a layout editor. Then, design verification is performed on the layout diagram, where the design verification includes design rule checking (DRC), layout versus schematic (LVS) verification, layout parameter extraction, and parasitic resistance-capacitance extraction.

[0003] In the related art, there is a problem that the extraction efficiency of the layout diagram is low, resulting in a long back-end physical verification time.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to overcome the deficiencies of the above-mentioned prior art and to provide a circuit layout structure verification method, device, storage medium and equipment.

[0006] According to one aspect of the present disclosure, there is provided a method for verifying a circuit layout structure, comprising: acquiring layout data and initial circuit diagram data corresponding to the layout data, the initial circuit diagram data comprising a plurality of identical repeating unit structures, the repeating unit structure comprising a plurality of devices; replacing the repeating unit structures in the initial circuit diagram data with target devices to obtain target circuit diagram data; and performing layout and circuit diagram (LVS) verification according to the target circuit diagram data and the layout data.

[0007] In an exemplary embodiment of the present disclosure, the connection relationship between the target device and the external structure is the same as the connection relationship between the repeating unit structure and the external structure, and the external structure includes all other devices and routings in the initial circuit diagram data except the repeating unit structure.

[0008] In an exemplary embodiment of the present disclosure, performing LVS verification based on the target circuit diagram data and the layout data includes: extracting a layout netlist to be tested from the layout data based on the target circuit diagram data; and verifying the layout data based on the layout netlist to be tested and the target circuit diagram data.

[0009] In an exemplary embodiment of the present disclosure, a layout netlist to be tested is extracted from the layout data according to the target circuit diagram data, including: determining an identification rule, the identification rule including a rule for identifying the target device; identifying the layout data according to the target circuit diagram data and the identification rule, and extracting the layout netlist to be tested.

[0010] In an exemplary embodiment of the present disclosure, the naming of the target device in the target circuit diagram data is the same as the naming of the target device in the identification rule.

[0011] In an exemplary embodiment of the present disclosure, verifying the layout data based on the layout netlist to be tested and the target circuit diagram data includes: extracting a target netlist according to the target circuit diagram data; and verifying the layout data based on the layout netlist to be tested and the target netlist.

[0012] In an exemplary embodiment of the present disclosure, the verifying of the layout data based on the layout netlist to be tested and the target netlist includes: comparing the layout netlist to be tested with the target netlist; and determining the difference between the layout data and the target circuit diagram data based on the comparison result.

[0013] In an exemplary embodiment of the present disclosure, determining the difference between the layout data and the target circuit diagram data based on the comparison results includes: determining whether the devices, device connection relationships, and device parameters of the layout data are the same as the devices, device connection relationships, and device parameters of the target circuit diagram data.

[0014] In an exemplary embodiment of the present disclosure, the layout data includes a layout structure.

[0015] In an exemplary embodiment of the present disclosure, the layout data and the initial circuit diagram data are layout data and initial circuit diagram data of a storage device, the repeating unit structure includes a storage unit, the storage unit includes a transistor and a storage capacitor, the control end of the transistor is connected to a bit line, the first end of the transistor is connected to a word line, and the second end of the transistor is connected to the storage capacitor; wherein the target device includes a first connection end and a second connection end, the first connection end is connected to the word line, and the second connection end is connected to the bit line.

[0016] In an exemplary embodiment of the present disclosure, replacing the repetitive unit structure in the initial circuit diagram data with a target device to obtain the target circuit diagram data includes: using the target device to replace the storage unit in the initial circuit diagram data and using the connection relationship between the target device and the word line and the bit line to replace the connection relationship between the storage unit and the word line and the bit line in the initial circuit diagram data.

[0017] In an exemplary embodiment of the present disclosure, the target circuit diagram data includes device information, and the device information includes at least a target device name and a target device number.

[0018] According to the second aspect of the present disclosure, a circuit layout structure verification device is also provided, including: an acquisition module, used to acquire layout data and initial circuit diagram data corresponding to the layout data, the initial circuit diagram data including multiple identical repeating unit structures, and the repeating unit structure including multiple devices; a reconstruction module, used to replace the repeating unit structure in the initial circuit diagram data with a target device to obtain target circuit diagram data; a verification module, used to perform LVS verification based on the target circuit diagram data and the layout data.

[0019] According to a third aspect of the present disclosure, a computer-readable storage medium is further provided, on which a computer program is stored, and when the program is executed by a processor, the circuit layout structure verification method described in any embodiment of the present disclosure is implemented.

[0020] According to the fourth aspect of the present disclosure, a verification device is also provided, including: one or more processors; a storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, the one or more processors implement the verification method of the circuit layout structure described in any embodiment of the present disclosure.

[0021] The verification method provided by the present disclosure obtains the target circuit diagram data by replacing the repetitive unit structure in the initial circuit diagram data as a whole with the target device. In this way, when performing LVS verification according to the target circuit diagram data and the layout data, the repetitive unit structure in the layout data can be directly identified as the target device without specifically identifying the internal device of the repetitive unit structure, thereby reducing the recognition time for the layout data and improving the LVS verification efficiency. When the layout data contains a large number of repetitive unit structures, the LVS verification efficiency of the layout data can be greatly improved by the method disclosed in the present disclosure.

[0022] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0024] Figure 1 A flow chart of a circuit layout structure verification method according to an embodiment of the present disclosure;

[0025] Figure 2 is a schematic structural diagram of a storage device according to an embodiment of the present disclosure;

[0026] Figure 3 A schematic diagram of a circuit structure after a storage unit in a storage device is replaced according to an embodiment of the present disclosure;

[0027] Figure 4 is a structural block diagram of a circuit layout structure verification device according to an embodiment of the present disclosure;

[0028] Figure 5 It is a schematic diagram of the structure of a verification device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0030] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0031] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0032] Figure 1 The present invention is a flow chart of a circuit layout structure verification method according to an embodiment of the present invention. The method can be executed by an electronic device, such as a computer or server running preset software. The verification method of the present invention is particularly suitable for integrated circuits with a large number of repeated unit structures, such as memory chips containing a large number of repeated unit structures. The verification efficiency of the layout data can be improved by replacing the repeated unit structure as a whole with a target device. Figure 1 As shown, the verification method may include the following steps:

[0033] S110, acquiring layout data and initial circuit diagram data corresponding to the layout data, wherein the initial circuit diagram data includes a plurality of identical repeating unit structures, and the repeating unit structure includes a plurality of devices;

[0034] S120, replacing the repeated unit structure in the initial circuit diagram data with the target device to obtain the target circuit diagram data;

[0035] S130 , performing LVS verification according to the target circuit diagram data and layout data.

[0036] The verification method provided by the present disclosure obtains the target circuit diagram data by replacing the repetitive unit structure in the initial circuit diagram data as a whole with the target device. In this way, when performing LVS verification according to the target circuit diagram data and the layout data, the repetitive unit structure in the layout data can be directly identified as the target device without specifically identifying the internal device of the repetitive unit structure, thereby reducing the recognition time for the layout data and improving the LVS verification efficiency. When the layout data contains a large number of repetitive unit structures, the LVS verification efficiency of the layout data can be greatly improved by the method disclosed in the present disclosure.

[0037] Next, the above steps of this exemplary embodiment are described in more detail.

[0038] In step S110 , layout data and initial circuit diagram data corresponding to the layout data are acquired, where the initial circuit diagram data includes a plurality of identical repeating unit structures, and the repeating unit structure includes a plurality of devices.

[0039] Among them, the layout data includes the specific physical structure of the circuit. For example, the layout data may include the layout structure corresponding to the equivalent circuit diagram. For example, the layout data of the semiconductor device may include active layer data, conductive layer data, insulating layer data, etc. The active layer data may include, for example, the channel region data of the transistor, and the conductive layer data may include, for example, the data of the source and drain of the transistor and the routing data. It can be understood that the corresponding equivalent circuit diagram can be constructed through the layout data.

[0040] The initial circuit diagram data is data generated by the software for constructing an initial equivalent circuit diagram. The initial circuit diagram data includes multiple identical repeating unit structures, and the repeating unit structure can be understood as a circuit structure that implements the same function and has the same device composition and device connection relationship. For example, a memory contains a large number of repeated storage units, and each storage unit is a repeating unit structure of the memory.

[0041] It should be understood that the present disclosure can achieve the purpose of reducing the number of device identifications and improving verification efficiency only by replacing the entire repeating unit structure composed of multiple devices. Therefore, the repeating unit structure described in the present disclosure needs to include multiple devices, for example, it may include two or more devices.

[0042] It can be understood that the layout data and the initial circuit diagram data can be generated by software, and the present disclosure does not limit the data format of the layout data and the initial circuit diagram data.

[0043] In step 120, the repetitive unit structure in the initial circuit diagram data is replaced with the target device to obtain the target circuit diagram data.

[0044] The purpose of this step is to replace the structure of the repeating unit structure in the initial circuit diagram data to obtain the target circuit diagram data. The target circuit diagram data after the structural replacement can reconstruct the corresponding equivalent circuit diagram, and in the reconstructed equivalent circuit diagram, for each repeating unit structure, it is only necessary to reflect the connection relationship between the repeating unit structure and the repeating unit structure and the external structure, without reflecting the specific structure inside the repeating unit structure, which is equivalent to simplifying the circuit, so as to improve the recognition efficiency of the layout data in the subsequent steps through the target circuit diagram data with simplified circuits. It should be understood that in this step, only the repeating unit structure is replaced, and other circuit structures in the initial circuit diagram data remain unchanged.

[0045] It can be understood that the connection relationship between the target device and the external structure is the same as the connection relationship between the repeating unit structure and the external structure. The external structure can be understood as all other devices and traces in the initial circuit diagram data except the repeating unit structure. For example, Figure 2 FIG. 1 is a schematic diagram of a storage device according to an embodiment of the present disclosure. Figure 2 As shown, the memory may include a plurality of repeated memory cells 100, each memory cell 100 having the same structure. Specifically, the memory cell 100 may include a transistor T and a storage capacitor C, the control end of the transistor T is connected to the word line WL, the first end of the transistor T is connected to the bit line BL, and the second end of the transistor T is connected to the storage capacitor C. When the initial circuit diagram data includes Figure 2 When the initial circuit data of the storage device is shown, the repeating unit structure in the initial circuit diagram may include the storage unit 100, and other devices and wirings in the storage unit except the storage unit 100 are the external structure of the storage unit 100, for example, the sensing device, word line, bit line, enable signal line, etc. in the storage unit are the external structure of the storage unit 100. It should be understood that the external structure is relative to the defined repeating unit structure, and when the defined repeating unit structure changes, the external structure may also change accordingly.

[0046] The target device can be understood as a modular device with corresponding connection ports. In other words, only the external structural features of the target device need to be defined without reflecting its internal structure. The connection port of the target device needs to be determined based on the connection relationship between the repeating unit structure and the external structure, that is, the repeating unit structure is regarded as a whole and the internal structure of the repeating unit structure is ignored, and only the connection relationship between the repeating unit structure and the external structure is retained to achieve the overall replacement of the repeating unit structure by the target device. For example, for Figure 2 For the storage device shown, according to the connection relationship between the transistor T and the word line WL and the bit line BL in the storage unit 100, it can be determined that the target device may include a first connection terminal and a second connection terminal, the first connection terminal is used to connect the word line WL, and the second connection terminal is used to connect the bit line BL.

[0047] Accordingly, Figure 2 For the storage device shown, this step is to treat the storage cell 100 as a whole, i.e., the target device, use the target device to replace the storage cell 100 structure in the initial circuit diagram data as a whole, and use the connection relationship between the target device and the word line WL and the bit line BL to replace the connection relationship between the transistor T and the word line WL and the bit line BL in the storage cell 100 in the initial circuit diagram data to obtain the target circuit diagram data.

[0048] For example, Figure 3 FIG. 1 is a schematic diagram of a circuit structure after a storage unit in a storage device is replaced according to an embodiment of the present disclosure, that is, a schematic diagram of a circuit structure of a storage device constructed according to target circuit diagram data, such as Figure 3As shown, in the target circuit diagram data, the internal structure of the target device 200 is no longer specifically reflected, that is, the transistor T and storage capacitor C structure of the storage unit 100 are no longer reflected. Obviously, the circuit structure of the target circuit diagram data is simpler than the circuit structure of the initial circuit diagram data.

[0049] In step S130 , LVS verification is performed based on the target circuit diagram data and layout data.

[0050] Among them, LVS (Layout Versus Schematic) verification can be used to verify the consistency between layout data and circuit schematics. In this step, the consistency between the layout data and the circuit schematic corresponding to the target circuit diagram data is verified.

[0051] In an exemplary embodiment, step S130 may include the following steps:

[0052] S131, extracting a layout netlist to be tested from the layout data according to the target circuit diagram data;

[0053] S132, verifying the layout data based on the layout netlist to be tested and the target circuit diagram data.

[0054] It can be known that, because the target device is used to represent the repetitive unit structure in the equivalent circuit corresponding to the target circuit diagram data, therefore, by using the target circuit diagram data to identify the layout data, the related devices used to form the repetitive unit structure in the layout data can be identified as the target device, and because the target circuit diagram data no longer contains the internal structure of the target device, the layout netlist to be tested obtained by identifying the layout data correspondingly only contains the target device and the connection relationship information between the target device and the external device, and no longer contains the internal device information of the target device. Obviously, compared with the related art that identifies the repetitive unit structure in the layout data as the specific devices contained in the repetitive unit structure, the identification method of this step can significantly reduce the number of device identifications, thereby improving the recognition efficiency of the layout data, especially when the layout data contains a large number of repetitive unit structures, the method disclosed in the present disclosure only identifies the repetitive unit structure as the target device, which can greatly improve the recognition efficiency of the layout data.

[0055] In an exemplary embodiment, when the layout data is recognized, a recognition rule may be defined by a recognition file, and the recognition rule defined by the recognition file recognizes the layout data using the circuit diagram data to extract the netlist.

[0056] In an exemplary embodiment, step S131 may specifically include the following steps:

[0057] S1311, determining an identification rule, where the identification rule includes a rule for identifying a target device;

[0058] S1312. Identify the layout data according to the target circuit diagram data and the identification rules, and extract the layout netlist to be tested.

[0059] The identification rules include rules for identifying target devices, that is, the devices constituting the repeating unit structure in the layout data are identified as a whole and identified as target devices.

[0060] The information for representing the device in the identification rule is the same as the information for representing the same device in the target circuit diagram data. For example, in the target circuit diagram data, a target device and a connection port are used to represent Figure 2 As shown in the figure, the connection relationship between the memory cell 100 and the word line WL and the bit line BL is represented by a target device and a connection port, and the name of the target device and the connection port in the identification rule is the same as the name of the same target device and the connection port in the target circuit diagram data.

[0061] In an exemplary embodiment, an LVS file can be used as an identification rule. The LVS file includes information such as operation settings, layer definitions, device definitions, device naming, ports, etc. Accordingly, determining the identification rule can be to update an existing LVS file to redefine part or all of the identification rules. Specifically, in this exemplary embodiment, the repeating unit structure in the layout data can be redefined based on the existing identification rules, that is, the repeating unit structure in the LVS file is replaced with the target device, and the connection relationship between the internal device and the corresponding external structure of the repeating unit structure in the LVS file is replaced with the connection relationship between the target device and the external structure, so as to update the existing identification rules.

[0062] For example, for Figure 2 The memory cell 100 shown in the figure has a connection relationship between the transistor T in the memory cell 100 and the word line WL and the bit line BL defined in the original LVS file. This step is to redefine the memory cell and its connection relationship with the word line and the bit line in the LVS file. Specifically, the transistor T and the storage capacitor C constituting the memory cell 100 are replaced with the target device, and the connection relationship between the target device and the word line WL and the bit line BL is used to replace the connection relationship between the transistor T and the word line WL and the bit line BL, and other devices and their connection relationships are kept unchanged, thereby redefining the recognition rules for the layout data using the existing recognition rules. According to the redetermined recognition rules, the target circuit diagram data is used to identify the corresponding Figure 2 The memory cell 100 in the layout data and its connection relationship with the word line WL and the bit line BL can be identified as Figure 3The target device 200 and the connection relationship between the target device 200 and the word line WL and the bit line BL, that is, the obtained layout netlist to be tested is used Figure 3 The circuit structure shown is used to represent a repeating unit structure (memory cell 100) in a memory device.

[0063] Because one word line WL and one bit line BL can uniquely identify one storage unit 100, the present disclosure uses the target circuit diagram data and the determined identification file to identify the storage unit 100. Figure 2 To identify the storage unit 199 in the corresponding layout data, it is equivalent to only needing to identify the word line WL and the bit line BL.

[0064] The present disclosure changes the identification of the storage unit 100 from the original identification of the specific transistor T, capacitor and connection node to the identification of the word line WL and the bit line BL, thereby greatly shortening the time required to extract the spice file from the layout, thereby greatly speeding up the entire LVS. Such a change not only shortens the back-end verification time of the entire design, but also when there is a subsequent design revision, the time reduction brought by such a change is very significant, especially for large-scale integrated circuits, the efficiency improvement is more significant.

[0065] For example, Table 1 shows the identification rules provided by the present disclosure and the prior art. Figure 2 The time benefit of the storage unit 100 is compared with the identification rule of identifying a transistor T and a storage capacitor C. It can be seen that after using the identification rule disclosed in the present invention, the efficiency of identifying the layout can be significantly improved, and the more complex the memory or the more repeated storage units 100, the more obvious the efficiency improvement.

[0066] Table 1

[0067] ProductA(4Gb) ProductB(8Gb) ProductC(16Gb) Existing Identification Rules 2.5h 3.7h Program Crash (>5h) This Public Identification Rules 1.1h 1.3h 1.5h Δt(%) 127％ 185％ >233％

[0068] It can be understood that the device information of the target device in the identification rule corresponds to the device information of the target device in the target circuit diagram data, and the device information at least includes the device name and the device number, that is, a device can be represented by the device name and the device number, so that the device information of each device is different. In this way, the obtained layout netlist to be tested can use the device name specified by the identification rule to represent the corresponding device, so that the layout netlist to be tested can be compared with the target netlist obtained based on the target circuit diagram data for consistency. For example, the storage device includes 100 storage units, then in the defined identification rules, the names of the target devices used to replace each storage unit can be M00, M01, M02...M99, and accordingly, in the target circuit diagram data, the names of the target devices are also M00, M01, M02...M99. In other embodiments, the device information can also include other information such as the device address, and the present disclosure does not limit the specific internal of the device information.

[0069] The present disclosure redefines the identification rules by using the target device and its connection relationship with the external structure, so that the representation of the same device in the identification rules is the same as the representation of the same electronic device in the target circuit diagram data.

[0070] After the layout netlist to be tested is obtained through the above steps, then in step S132 , the layout data is verified based on the layout netlist to be tested and the target circuit diagram data.

[0071] The layout data may include not only a repeating unit structure but also other circuit structures. For example, for a memory, it may also include a sensing amplifier circuit, a driving circuit, etc. This step verifies the layout data to verify the consistency of all circuit structures in the layout data with the same circuit structures in the target circuit diagram data.

[0072] In an exemplary embodiment, step S132 may include the following steps:

[0073] S1321, extracting a target netlist according to target circuit diagram data;

[0074] S1322. Verify the layout data based on the layout netlist to be tested and the target netlist.

[0075] Among them, the target circuit diagram data contains the circuit structure information after the structure replacement of the repeated unit structure. Obviously, the target netlist extracted based on the target circuit diagram data also contains the circuit structure information after the structure replacement of the repeated unit structure. Because the layout netlist to be tested is obtained by identifying the layout data according to the redefined identification rules, the verification result of the target netlist and the layout netlist to be tested reflects whether the target circuit diagram data is consistent with the layout data.

[0076] In an exemplary embodiment, step S1322 may specifically include the following steps:

[0077] S1421, comparing the layout netlist to be tested with the target netlist;

[0078] S1422. Determine the difference between the layout data and the target circuit diagram data according to the comparison result.

[0079] Among them, the layout netlist to be tested is compared with the target netlist, for example, the devices, device connection relationships, and device parameters in the layout netlist to be tested are compared with the devices, device connection relationships, and device parameters in the target netlist to determine whether the devices, device connection relationships, and device parameters of the layout data are the same as the devices, device connection relationships, and device parameters of the target circuit diagram data.

[0080] For example, for Figure 2 The memory cell 100 structure of the memory shown in FIG. 1 is a structure in which steps S1421 and S1422 are to represent the layout netlist to be tested. Figure 3 The connection relationship between the target device 200 and the word line WL and the bit line BL in the target circuit diagram data is compared with the connection relationship between the target device 200 and the word line WL and the bit line BL at the corresponding position in the target circuit diagram data. Only when the connection relationship between all the target devices 200 and the word line WL and the bit line BL is the same, it indicates that the LVS verification of the memory cell 100 in the layout data and the memory cell 100 in the target circuit diagram has passed. It should be understood that this step is to compare all the devices and their connection relationships and device parameters in the target circuit diagram data with all the devices and their connection relationships and device parameters in the layout data.

[0081] In summary, the verification method disclosed in the present invention, before identifying the layout data, first replaces the repetitive unit structure in the initial circuit diagram data with the target device 200 as a whole, and only needs to reflect the connection relationship between the target device and the external structure, and no longer reflects the internal structure of the repetitive unit structure, thereby achieving circuit simplification of the initial circuit diagram data, and then using the simplified circuit diagram data and the redefined identification rules to extract the netlist from the layout data, which can improve the netlist extraction efficiency. Especially when the layout data contains a large number of repetitive unit structures, the method disclosed in the present invention can greatly improve the netlist extraction efficiency for the layout, thereby greatly reducing the back-end verification time.

[0082] It should be understood that the above embodiments of the present disclosure are only Figure 2The memory shown is used as an example for illustrative explanation. The verification method disclosed herein includes but is not limited to the above circuit structure. All circuits with the same repeating unit structure can perform LVS verification of layout data and circuit diagram data through the method disclosed herein. In addition, the method of implementing LVS verification by comparing the netlist in the above embodiment is only an illustrative explanation and should not be understood as a limitation of the present disclosure. In other embodiments, LVS verification of layout data and circuit diagram data can also be performed by other methods.

[0083] Figure 4 FIG. 1 is a structural block diagram of a circuit layout structure verification device according to an embodiment of the present disclosure, as shown in FIG. Figure 4 As shown, the verification device 400 may include: an acquisition module 410, a reconstruction module 420 and a verification module 430, wherein:

[0084] An acquisition module 410 is used to acquire layout data and initial circuit diagram data corresponding to the layout data, wherein the initial circuit diagram data includes a plurality of identical repeating unit structures, and the repeating unit structure includes a plurality of devices;

[0085] A reconstruction module 420 is used to replace the repeated unit structure in the initial circuit diagram data with the target device to obtain the target circuit diagram data;

[0086] The verification module 430 is used to perform LVS verification according to the target circuit diagram data and layout data.

[0087] In an exemplary embodiment, the connection relationship between the target device and the external structure is the same as the connection relationship between the repeating unit structure and the external structure, and the external structure includes all other devices and traces in the initial circuit diagram data except the repeating unit structure.

[0088] In an exemplary embodiment, the verification module 430 may include:

[0089] A netlist extraction unit, used for extracting a layout netlist to be tested from the layout data according to the target circuit diagram data;

[0090] The verification unit is used to verify the layout data based on the layout netlist to be tested and the target circuit diagram data.

[0091] In an exemplary embodiment, the netlist extraction unit may also be used to:

[0092] Determining an identification rule, the identification rule including a rule for identifying a target device;

[0093] The layout data is identified according to the target circuit diagram data and the identification rules, and the layout netlist to be tested is extracted.

[0094] In an exemplary embodiment, the naming of the target device in the target circuit diagram data is the same as the naming of the target device in the recognition rule.

[0095] In an exemplary embodiment, the verification unit may also be used to:

[0096] Extracting a target netlist according to target circuit diagram data;

[0097] Verify the layout data based on the layout netlist under test and the target netlist.

[0098] In an exemplary embodiment, the verification unit may also be used to:

[0099] Compare the layout netlist to be tested with the target netlist;

[0100] The difference between the layout data and the target circuit diagram data is determined based on the comparison result.

[0101] In an exemplary embodiment, the verification unit may also be used to:

[0102] It is determined whether the devices, the connection relationship of the devices, and the parameters of the devices in the layout data are the same as the devices, the connection relationship of the devices, and the parameters of the devices in the target circuit diagram data.

[0103] In an exemplary embodiment, the layout data includes a layout structure.

[0104] In an exemplary embodiment, the layout data and the initial circuit diagram data are the layout data and the initial circuit diagram data of a storage device, the repeating unit structure includes a storage cell, the storage cell includes a transistor and a storage capacitor, the control end of the transistor is connected to a bit line, the first end of the transistor is connected to a word line, and the second end of the transistor is connected to the storage capacitor; wherein the target device includes a first connection end and a second connection end, the first connection end is connected to the word line, and the second connection end is connected to the bit line.

[0105] In an exemplary embodiment, the reconstruction module 420 may also be used to:

[0106] The target device is used to replace the storage unit in the initial circuit diagram data, and the connection relationship between the target device and the word line and the bit line is used to replace the connection relationship between the storage unit and the word line and the bit line in the initial circuit diagram data.

[0107] In an exemplary embodiment, the target circuit diagram data includes device information, and the device information includes at least a target device name and a target device number.

[0108] Figure 5 This is a schematic diagram of the structure of a verification device according to an embodiment of the present disclosure. It should be noted that: Figure 5 The verification device 500 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure. Figure 5 As shown, the verification device 500 may include but is not limited to a PC running setting software, a server, etc.

[0109] like Figure 5 As shown, the verification device 500 includes a central processing unit (CPU) 501, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 502 or the program loaded from the storage part 508 into the random access memory (RAM) 503. In the (RAM) 503, various programs and data required for system operation are also stored. (CPU) 501, (ROM) 502 and (RAM) 503 are connected to each other through a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0110] The following components are connected to the (I / O) interface 505: an input section 506 including a keyboard, a mouse, etc.; an output section 507 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN card, a modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to the (I / O) interface 505 as needed. A removable medium 511, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 510 as needed, so that a computer program read therefrom is installed into the storage section 508 as needed.

[0111] In particular, according to the embodiments of the present disclosure, the above reference process Figure 3 The described process can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable storage medium, and the computer program contains program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through the communication part 509, and / or installed from a removable medium 511. When the computer program is executed by the central processing unit (CPU) 501, various functions defined in the method and apparatus of the present disclosure are executed.

[0112] It should be noted that the computer-readable storage medium shown in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer-readable signal medium may also be any computer-readable storage medium other than a computer-readable storage medium that can send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, etc., or any suitable combination of the above.

[0113] As another aspect, the present disclosure further provides a computer-readable storage medium, which may be included in the verification device 500 described in the above embodiment; or may exist independently without being assembled into the verification device 500. The above computer-readable storage medium carries one or more programs, and when the above one or more programs are executed by the verification device 500, the verification device 500 implements the method in the above embodiment. For example, the verification device 500 may implement the following method: Figure 1 The various steps shown, etc.

[0114] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the generality of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

Claims

1. A circuit layout structure verification method, characterized in that: include: Acquire layout data and initial circuit diagram data corresponding to the layout data, wherein the initial circuit diagram data includes a plurality of identical repeating unit structures, and the repeating unit structure includes a plurality of devices; Replacing the repeating unit structure in the initial circuit diagram data with a target device to obtain target circuit diagram data; performing layout and schematic (LVS) verification according to the target schematic data and the layout data; The connection relationship between the target device and the external structure is the same as the connection relationship between the repeating unit structure and the external structure, and the external structure includes all other devices and routings in the initial circuit diagram data except the repeating unit structure; The performing of layout and schematic (LVS) verification according to the target circuit diagram data and the layout data comprises: Extracting a layout netlist to be tested from the layout data according to the target circuit diagram data; Verifying the layout data based on the layout netlist to be tested and the target circuit diagram data; Wherein, extracting a layout netlist to be tested from the layout data according to the target circuit diagram data comprises: determining an identification rule, wherein the identification rule includes a rule for identifying the target device; Identify the layout data according to the target circuit diagram data and the identification rule, and extract the layout netlist to be tested; The naming of the target device in the target circuit diagram data is the same as the naming of the target device in the identification rule.

2. The method according to claim 1, characterized in that The verifying the layout data based on the layout netlist to be tested and the target circuit diagram data includes: Extracting a target netlist according to the target circuit diagram data; The layout data is verified based on the layout netlist to be tested and the target netlist.

3. The method according to claim 2, characterized in that The verifying the layout data based on the layout netlist to be tested and the target netlist includes: Comparing the layout netlist to be tested with the target netlist; The difference between the layout data and the target circuit diagram data is determined according to the comparison result.

4. The method according to claim 3, characterized in that The step of determining the difference between the layout data and the target circuit diagram data according to the comparison result includes: It is determined whether the devices, the connection relationships of the devices, and the parameters of the devices in the layout data are the same as the devices, the connection relationships of the devices, and the parameters of the devices in the target circuit diagram data.

5. The method according to any one of claims 1 to 4, characterized in that: The layout data includes a layout structure.

6. The method according to claim 1, characterized in that The layout data and the initial circuit diagram data are layout data and initial circuit diagram data of a storage device, the repeating unit structure includes a storage unit, the storage unit includes a transistor and a storage capacitor, the control end of the transistor is connected to a bit line, the first end of the transistor is connected to a word line, and the second end of the transistor is connected to the storage capacitor; The target device includes a first connection terminal and a second connection terminal, the first connection terminal is connected to the word line, and the second connection terminal is connected to the bit line.

7. The method according to claim 6, characterized in that The step of replacing the repeating unit structure in the initial circuit diagram data with a target device to obtain target circuit diagram data includes: The target device is used to replace the storage unit in the initial circuit diagram data, and the connection relationship between the storage unit and the word line and the bit line in the initial circuit diagram data is replaced by the connection relationship between the target device and the word line and the bit line.

8. The method according to claim 1, characterized in that The target circuit diagram data includes device information, and the device information at least includes a target device name and a target device number.

9. A circuit layout structure verification device, characterized in that: include: An acquisition module, used for acquiring layout data and initial circuit diagram data corresponding to the layout data, wherein the initial circuit diagram data includes a plurality of identical repeating unit structures, and the repeating unit structure includes a plurality of devices; A reconstruction module, used for replacing the repeating unit structure in the initial circuit diagram data with a target device to obtain target circuit diagram data; A verification module, configured to perform layout and schematic (LVS) verification according to the target circuit diagram data and the layout data; The connection relationship between the target device and the external structure is the same as the connection relationship between the repeating unit structure and the external structure, and the external structure includes all other devices and routings in the initial circuit diagram data except the repeating unit structure; The verification module is used to perform layout and circuit diagram (LVS) verification according to the target circuit diagram data and the layout data, including: Extracting a layout netlist to be tested from the layout data according to the target circuit diagram data; Verifying the layout data based on the layout netlist to be tested and the target circuit diagram data; The verification module is used to perform layout and circuit diagram (LVS) verification according to the target circuit diagram data and the layout data, including: determining an identification rule, wherein the identification rule includes a rule for identifying the target device; Identify the layout data according to the target circuit diagram data and the identification rule, and extract the layout netlist to be tested; The naming of the target device in the target circuit diagram data is the same as the naming of the target device in the identification rule.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the circuit layout structure verification method according to any one of claims 4 to 8 is implemented.

11. A verification device, characterized in that: include: one or more processors; A storage device for storing one or more programs, when the one or more programs are executed by the one or more processors, enables the one or more processors to implement the circuit layout structure verification method according to any one of claims 4 to 8.

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