A device and method for verifying hash algorithm

Abstract

The present invention provides a device and method for verifying a hash algorithm, the device comprising: an excitation transmitter configured to output a random number; a functional model connected to the excitation transmitter, having a first hash algorithm written in a software programming language, and configured to receive a random number, and obtain a first operation result by operating the random number via the first hash algorithm, and output the first operation result; a device under test, connected to the excitation transmitter, having a second hash algorithm written in a hardware description language, and configured to receive a random number, and obtain a second operation result by operating the random number via the second hash algorithm, and output the second operation result; and a comparator, respectively connected to the functional model and the device under test, and configured to receive the first operation result and the second operation result, and compare the two to verify the second hash algorithm based on the comparison result. The present invention improves the verification efficiency and reliability of the hash algorithm in terms of hardware.

Description

Technical Field

[0001] The present invention relates to the field of algorithm technology, and in particular to a device and method for verifying a hash algorithm. Background Art

[0002] The hash algorithm is a widely used summary algorithm that converts plain text of any length into a fixed-length message digest through a hash algorithm. Commonly used hash algorithms include the MD series, the SHA (Secure Hash Algorithm) series, and the HMAC (Hash-based Message Authentication Code) algorithm based on these. Considering security factors, many SoC chips (system-on-chip) have integrated algorithm modules.

[0003] Most hash algorithms are implemented through software programming languages, and are relatively mature in software. In terms of hardware, traditional hash algorithm verification is based on a simple verification platform built on Verilog HDL language (a hardware description language), which directly writes incentives based on the verified input and output data set, collects outputs, and compares them with standard output data to determine whether they are consistent. Verification of hash algorithms based on this method is inefficient, the data used for verification is limited, the verification is not sufficient, and the coverage rate is difficult to meet the requirements. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a device and method for verifying a hash algorithm, so as to solve the problem of poor verification reliability and low verification efficiency when verifying the hash algorithm in hardware in the prior art.

[0005] Based on the above purpose, the present invention provides a device for verifying a hash algorithm, comprising:

[0006] an incentive transmitter configured to output a random number;

[0007] A functional model, the functional model is connected to the stimulus transmitter, the functional model has a first hash algorithm written in a software programming language, and is configured to receive a random number, and obtain a first operation result by operating the random number through the first hash algorithm, and output the first operation result;

[0008] A device under test, the device under test is connected to the stimulus transmitter, the device under test has a second hash algorithm written in a hardware description language, and is configured to receive a random number, and obtain a second operation result by operating the random number through the second hash algorithm, and output the second operation result; and

[0009] A comparator is connected to the functional model and the device under test respectively, and is configured to receive the first operation result and the second operation result, and compare the first operation result with the second operation result to verify the second hash algorithm based on the comparison result.

[0010] In some embodiments, the apparatus further comprises:

[0011] The driver has an input end connected to the stimulus transmitter, and an output end connected to the device under test through a bus, and is configured to receive random numbers and sequentially transmit a preset amount of random numbers in the random numbers to the device under test through the bus.

[0012] In some embodiments, the apparatus further comprises:

[0013] An input monitor is connected to the functional model and is configured to monitor the random numbers on the bus, and in response to monitoring the random numbers of the current preset amount, sends the random numbers of the current preset amount to the functional model.

[0014] In some embodiments, the functional model is further configured to obtain a first sub-operation result by operating the received random number of the current preset amount through a first hash algorithm, and send the first sub-operation result to the comparator.

[0015] In some embodiments, the device under test is further configured to obtain a second sub-operation result by operating the received random number of the current preset amount via a second hash algorithm, and output the second sub-operation result.

[0016] In some embodiments, the apparatus further comprises:

[0017] The output monitor has an input end connected to the device under test through a bus, and an output end connected to the comparator, and is configured to receive the second sub-operation result and send the second sub-operation result to the comparator.

[0018] In some embodiments, the comparator is further configured to compare multiple pairs of first sub-operation results and second sub-operation results respectively to obtain multiple comparison results, so as to verify the second hash algorithm based on the multiple comparison results.

[0019] In some embodiments, the comparator is further configured to:

[0020] Compare each pair of first sub-operation results and second sub-operation results to see if they are consistent;

[0021] In response to the first sub-operation result and the second sub-operation result being consistent, obtaining a consistent result; or

[0022] In response to the first sub-operation result and the second sub-operation result being inconsistent, obtaining a difference result;

[0023] Count the number of consistent results and different results respectively;

[0024] In response to the number of consistent results being greater than the number of different results and the difference between the two exceeding a preset value, it is confirmed that the second Hash algorithm has passed the verification.

[0025] In some embodiments, the software programming language includes at least C language, and the hardware description language includes at least SystemVerilog language.

[0026] Another aspect of the present invention further provides a method for verifying a hash algorithm, comprising the following steps:

[0027] Receiving a random number output by the stimulus transmitter through the functional model, and performing a first hash operation on the random number using a first hash algorithm written in a software programming language to obtain a first operation result, and sending the first operation result to the comparator;

[0028] The device under test receives the random number output by the stimulus transmitter, and operates the random number through a second hash algorithm written in a hardware description language to obtain a second operation result, and sends the second operation result to the comparator;

[0029] The received first operation result is compared with the second operation result by a comparator to verify the second hash algorithm based on the comparison result.

[0030] The present invention has at least the following beneficial technical effects:

[0031] The present invention verifies the hash algorithm in the device under test by using an excitation transmitter to output a large number of random numbers, thereby ensuring the adequacy of the verification. When the data type and range of the random numbers are relatively wide, the data coverage of the verification can be higher. The device for verifying the hash algorithm of the present invention can achieve reliable and effective verification, and compared with the traditional hardware hash algorithm verification method, the verification cycle is shortened and the verification efficiency is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A schematic diagram of a device for verifying a hash algorithm provided according to an embodiment of the present invention;

[0034] Figure 2A schematic diagram of the structure of a device for verifying a hash algorithm according to an embodiment of the present invention;

[0035] Figure 3 A schematic diagram of a method for verifying a hash algorithm according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0037] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are intended to distinguish two non-identical entities or non-identical parameters with the same name. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, other steps or units inherent to a process, method, system, product or device that includes a series of steps or units.

[0038] Based on the above purpose, a first aspect of an embodiment of the present invention provides an embodiment of a device for verifying a hash algorithm. Figure 1 FIG. 1 is a schematic diagram of an embodiment of a device for verifying a hash algorithm provided by the present invention. Figure 1 As shown, the device for verifying the hash algorithm according to the embodiment of the present invention includes:

[0039] An excitation transmitter 10 configured to output a random number;

[0040] The function model 20 is connected to the stimulus transmitter 10, and the function model 20 has a first hash algorithm written in a software programming language, and is configured to receive a random number, and obtain a first operation result by operating the random number through the first hash algorithm, and output the first operation result;

[0041] A device under test 30, the device under test 30 is connected to the stimulus transmitter 10, the device under test 30 has a second hash algorithm written in a hardware description language, and is configured to receive a random number, and obtain a second operation result by operating the random number through the second hash algorithm, and output the second operation result; and

[0042] The comparator 40 is connected to the functional model 20 and the device under test 30 respectively, and is configured to receive the first operation result and the second operation result, and compare the first operation result with the second operation result to verify the second hash algorithm based on the comparison result.

[0043] The embodiment of the present invention ensures the adequacy of the verification by adopting the stimulus transmitter 10 to output a large number of random numbers to verify the hash algorithm in the device under test 30. When the data type and range of the random numbers are relatively wide, the data coverage of the verification can be higher. The device for verifying the hash algorithm of the embodiment of the present invention can achieve reliable and effective verification, and compared with the traditional hardware hash algorithm verification method, the verification cycle is shortened and the verification efficiency is improved.

[0044] In this embodiment, the random number can be message data of any length and multiple types, and can also be randomly combined within a constraint range.

[0045] Figure 2 FIG. 2 shows a schematic diagram of the structure of a device for verifying a hash algorithm according to an embodiment of the present invention. Figure 2 As shown, the embodiment of the present invention adopts a verification platform development framework based on UVM (Universal Verification Methodology) to build a verification environment that is easy to reuse.

[0046] In some embodiments, the device also includes: a driver, the input end of the driver is connected to the stimulus transmitter 10, and the output end of the driver is connected to the device under test 30 through a bus, and is configured to receive random numbers and transmit a preset amount of random numbers in the random numbers to the device under test 30 through the bus in sequence.

[0047] In this embodiment, the driver ( Figure 2 Drv in will stimulate the transmitter 10 ( Figure 2 The random numbers output by the Sequencer or Seqr in the test are segmented or packaged according to certain rules, and then a preset amount of random numbers of the segmented or packaged numbers are sent to the bus each time, and then transmitted to the device under test 30 ( Figure 2 The bus is an Advanced High-performance Bus (AHB), which can be used as an on-chip system bus for SoCs (system-on-chip).

[0048] In some embodiments, the device also includes: an input monitor, which is connected to the functional model 20 and configured to monitor random numbers on the bus, and in response to monitoring the current preset amount of random numbers, sends the current preset amount of random numbers to the functional model 20.

[0049] In some embodiments, the functional model 20 is further configured to obtain a first sub-operation result by operating the received random number of the current preset amount through a first hash algorithm, and send the first sub-operation result to the comparator 40.

[0050] In the above embodiment, by setting the input monitor ( Figure 2 The Mon in in_agent monitors the data on the bus and sends the monitored preset amount of data to the functional model 20 ( Figure 2 The function model 20 then calculates the same preset random number, which can make the random number used in each calculation in the function model 20 and the device under test 30 the same, ensuring the orderliness of the data and the reliability of the calculation results. The input monitor can also monitor the correctness of the data when intercepting. Therefore, the input monitor can ensure the orderliness and correctness of the data and avoid affecting the final comparison result.

[0051] In some embodiments, the device under test 30 is further configured to obtain a second sub-operation result by operating the received random number of the current preset amount via a second hash algorithm, and output the second sub-operation result.

[0052] In some embodiments, the device also includes: an output monitor, whose input end is connected to the device under test 30 through a bus, and whose output end is connected to the comparator 40, and is configured to receive the second sub-operation result and send the second sub-operation result to the comparator 40.

[0053] In this embodiment, the output monitor ( Figure 2 The Mon in Out_agent is used to cooperate with the input monitor. The device under test 30 calculates the random number of the current preset amount through the second hash algorithm and sends the calculation result to the output monitor, which then transmits it to the comparator 40 ( Figure 2 Scb) in order to ensure the reliability of the operation.

[0054] In some embodiments, the comparator 40 is further configured to compare multiple pairs of first sub-operation results and second sub-operation results respectively to obtain multiple comparison results, so as to verify the second hash algorithm based on the multiple comparison results.

[0055] In some embodiments, the comparator 40 is further configured to: compare whether each pair of first sub-operation results and second sub-operation results are consistent; in response to the first sub-operation result and the second sub-operation result being consistent, obtain a consistency result; or in response to the first sub-operation result and the second sub-operation result being inconsistent, obtain a difference result; respectively count the number of consistency results and the number of difference results; in response to the number of consistency results being greater than the number of difference results and the difference between the two exceeding a preset value, confirm that the second hash algorithm has passed the verification.

[0056] In this embodiment, if the number of consistent results is much greater than the number of different results, it indicates that the reliability of the second hash algorithm is better. The best case is that each pair of the first sub-operation result and the second sub-operation result are consistent, then the hash algorithm written in the hardware description language achieves the same effect as that written in the software language.

[0057] like Figure 2 As shown, in this embodiment, multiple cache units (fifo) are also provided for temporarily storing data.

[0058] In some embodiments, the software programming language includes at least C language, and the hardware description language includes at least SystemVerilog language.

[0059] In this embodiment, the software programming language includes but is not limited to C language, for example, it can also be C++ language, Python language, etc. The hardware description language includes but is not limited to SystemVerilog language. SystemVerilog language is referred to as SV language, which is a relatively new language. It is based on Verilog language, is an extension and enhancement of IEEE 1364 Verilog-2001 standard, is compatible with Verilog2001, combines hardware description language (HDL) with modern high-level verification language (HVL), and has recently become the language for next-generation hardware design and verification.

[0060] A second aspect of an embodiment of the present invention further provides a method for verifying a hash algorithm. Figure 3 FIG. 1 is a schematic diagram of an embodiment of a method for verifying a hash algorithm provided by the present invention. Figure 3 As shown, a method for verifying a hash algorithm includes the following steps:

[0061] Step S10: receiving the random number output by the stimulus transmitter through the functional model, and performing a first operation operation on the random number through a first hash algorithm written in a software programming language to obtain a first operation result, and sending the first operation result to the comparator;

[0062] Step S20, receiving the random number output by the stimulus transmitter through the device under test, and performing a second operation operation on the random number through a second hash algorithm written in a hardware description language to obtain a second operation result, and sending the second operation result to the comparator;

[0063] Step S30: Compare the received first operation result with the second operation result through a comparator to verify the second Hash algorithm based on the comparison result.

[0064] The method for verifying a hash algorithm in an embodiment of the present invention ensures the adequacy of the verification by adopting an excitation transmitter to output a large number of random numbers to verify the hash algorithm in the device under test. When the data type and range of the random numbers are relatively wide, the data coverage of the verification can be higher. Reliable and effective verification can be achieved, and compared with traditional verification methods, the verification cycle is shortened and the verification efficiency is improved.

[0065] Finally, it should be noted that the various exemplary logic blocks, modules, circuits and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given of the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on the specific application and the design constraints imposed on the entire system. Those skilled in the art can implement the functions in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the scope disclosed in the embodiments of the present invention.

[0066] The various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure herein may be implemented or executed using the following components designed to perform the functions herein: a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and / or any other such configuration.

[0067] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope disclosed in the embodiments of the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0068] It should be understood that, as used herein, the singular form "a" or "an" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the items listed in association. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for description only and do not represent the advantages and disadvantages of the embodiments.

[0069] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. A device for verifying a hash algorithm, characterized in that: include: an incentive transmitter configured to output a random number; A functional model, the functional model is connected to the stimulus transmitter, the functional model has a first hash algorithm written in a software programming language, and is configured to receive the random number, and obtain a first operation result by operating the random number through the first hash algorithm, and output the first operation result; A device under test, the device under test is connected to the stimulus transmitter, the device under test has a second hash algorithm written in a hardware description language, and is configured to receive the random number, and obtain a second operation result by operating the random number through the second hash algorithm, and output the second operation result; as well as A comparator, wherein the comparator is connected to the functional model and the device under test respectively, and is configured to receive the first operation result and the second operation result, and compare the first operation result with the second operation result to verify the second hash algorithm based on the comparison result.

2. The device according to claim 1, characterized in that Also includes: A driver, wherein the input end of the driver is connected to the stimulus transmitter, and the output end of the driver is connected to the device under test through a bus, and is configured to receive the random numbers and sequentially transmit a preset amount of random numbers in the random numbers to the device under test through the bus.

3. The device according to claim 2, characterized in that Also includes: An input monitor is connected to the functional model and configured to monitor the random numbers on the bus, and in response to monitoring the current preset amount of random numbers, send the current preset amount of random numbers to the functional model.

4. The device according to claim 3, characterized in that The functional model is further configured to obtain a first sub-operation result by operating the received random number of the current preset amount through the first hash algorithm, and send the first sub-operation result to the comparator.

5. The device according to claim 4, characterized in that The device under test is further configured to obtain a second sub-operation result by operating the received random number of the current preset amount via the second hash algorithm, and output the second sub-operation result.

6. The device according to claim 5, characterized in that Also includes: An output monitor, wherein the input end of the output monitor is connected to the device under test through the bus, and the output end of the output monitor is connected to the comparator, and is configured to receive the second sub-operation result and send the second sub-operation result to the comparator.

7. The device according to claim 6, characterized in that The comparator is further configured to compare multiple pairs of the first sub-operation results and the second sub-operation results respectively to obtain multiple comparison results, so as to verify the second hash algorithm based on the multiple comparison results.

8. The device according to claim 7, characterized in that The comparator is further configured to: comparing whether each pair of the first sub-operation result and the second sub-operation result are consistent; In response to the first sub-operation result and the second sub-operation result being consistent, obtaining a consistency result; or In response to the first sub-operation result and the second sub-operation result being inconsistent, obtaining a difference result; Counting the number of the consistent results and the number of the different results respectively; In response to the number of the consistency results being greater than the number of the difference results and the difference between the two exceeding a preset value, it is confirmed that the second Hash algorithm has passed the verification.

9. The device according to claim 1, characterized in that The software programming language includes at least C language, and the hardware description language includes at least SystemVerilog language.

10. A method for verifying a hash algorithm, characterized in that: The following steps are involved: receiving a random number output by the stimulus transmitter through the functional model, and performing a first operation operation on the random number through a first hash algorithm written in a software programming language to obtain a first operation result, and sending the first operation result to the comparator; Receiving the random number output by the stimulus transmitter through the device under test, and operating the random number through a second hash algorithm written in a hardware description language to obtain a second operation result, and sending the second operation result to the comparator; The received first operation result is compared with the second operation result by the comparator to verify the second hash algorithm based on the comparison result.

Images