Storage unit, control method of storage unit, memory, and electronic device

Abstract

The application relates to a storage unit, a control method of the storage unit, a memory and an electronic device. The storage unit comprises a capacitor group, a contact pad above the capacitor group, a plurality of first contact holes and a plurality of second contact holes formed in the contact pad, and a control circuit electrically connected with the capacitor group through the first contact holes and the second contact holes. The control circuit is used for outputting a unit plate voltage to the capacitor group through the first contact holes and outputting the unit plate voltage to the capacitor group through the second contact holes when the temperature of the storage unit is higher than a preset temperature, and outputting the unit plate voltage to the capacitor group through the first contact holes and stopping outputting the voltage to the capacitor group through the second contact holes when the temperature of the storage unit is lower than the preset temperature. The above-mentioned storage unit can effectively reduce the metal resistance when the storage unit operates at high temperature.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a storage unit, a control method of the storage unit, a memory and an electronic device. BACKGROUND

[0002] In a conventional storage unit, a contact pad is formed above a capacitor. A contact hole is formed in the contact pad, and one end of a lead wire is arranged to pass through the contact hole and electrically connect with the capacitor. The other end of the lead wire inputs a cell plate voltage (VPLT) to the capacitor, so as to provide the cell plate voltage for the capacitor.

[0003] However, when the storage unit operates at high temperature, the metal resistance increases, so that the cell plate voltage cannot be effectively applied to the capacitor, thereby affecting the performance of the device. SUMMARY

[0004] Therefore, it is necessary to provide a storage unit, a control method of the storage unit, a memory and an electronic device to solve the problem that the metal resistance increases when the storage unit operates at high temperature, so that the cell plate voltage cannot be effectively applied to the capacitor, thereby affecting the performance of the device.

[0005] To achieve the above-mentioned purpose, in one aspect, the present application provides a storage unit, comprising:

[0006] a capacitor group;

[0007] a contact pad above the capacitor group, a plurality of first contact holes and a plurality of second contact holes are formed in the contact pad;

[0008] a control circuit electrically connected with the capacitor group through each of the first contact holes and electrically connected with the capacitor group through each of the second contact holes, the control circuit is configured to output a cell plate voltage to the capacitor group through the first contact holes and output the cell plate voltage to the capacitor group through the second contact holes when the temperature of the storage unit is higher than a preset temperature, and output the cell plate voltage to the capacitor group through the first contact holes and stop outputting the voltage to the capacitor group through the second contact holes when the temperature of the storage unit is lower than the preset temperature.

[0009] In one embodiment, the control circuit comprises:

[0010] a first input end connected with a temperature sensor signal line;

[0011] a second input end connected with a storage unit selection signal line;

[0012] a first output end electrically connected with the capacitor group through each of the first contact holes;

[0013] a second output end electrically connected with the capacitor group through each of the second contact holes;

[0014] a first switch unit, an input end of the first switch unit inputting the cell plate voltage, and an output end of the first switch unit connected with the first output end;

[0015] an OR gate, two input ends of the OR gate connected with the first input end and the second input end respectively, and an output end of the OR gate connected with a control end of the first switch unit;

[0016] a second switch unit, an input end of the second switch unit inputting the cell plate voltage, and an output end of the second switch unit connected with the second output end;

[0017] an AND gate, two input ends of the AND gate connected with the first input end and the second input end respectively, and an output end of the AND gate connected with a control end of the second switch unit.

[0018] In one of the embodiments, when the control end of the first switch unit receives a high level, the input end and the output end of the first switch unit are connected, and when the control end of the first switch unit receives a low level, the input end and the output end of the first switch unit are disconnected; when the control end of the second switch unit receives a high level, the input end and the output end of the second switch unit are connected, and when the control end of the second switch unit receives a low level, the input end and the output end of the second switch unit are disconnected.

[0019] When the temperature of the storage unit is higher than the preset temperature, the temperature sensor signal line inputs a high level to the first input end of the control circuit, and the storage unit selection signal line inputs a high level to the second input end of the control circuit.

[0020] When the temperature of the storage unit is lower than the preset temperature, the temperature sensor signal line inputs a low level to the first input end of the control circuit, and the storage unit selection signal line inputs a high level to the second input end of the control circuit.

[0021] In one of the embodiments, the preset temperature ranges from 80 degrees to 90 degrees.

[0022] In one of the embodiments, the capacitor group comprises a plurality of capacitors arranged in an array.

[0023] In one of the embodiments, an electrode lead-out layer is further included, the electrode lead-out layer being located between the capacitor group and the contact pad, one electrode of each of the capacitors being electrically connected with the electrode lead-out layer, and each of the first contact holes and each of the second contact holes being communicated with the electrode lead-out layer.

[0024] In one of the embodiments, the contact pad comprises a first contact hole region and a second contact hole region, the first contact hole region is located at an edge region of the contact pad, the second contact hole region is located at a central region of the contact pad, each of the first contact holes is formed in the first contact hole region, and each of the second contact holes is formed in the second contact hole region.

[0025] In one of the embodiments, the memory cell comprises two control circuits, the contact pad comprises a first region and a second region, the first region and the second region each comprise a plurality of the first contact holes and a plurality of the second contact holes, one of the control circuits is electrically connected to the capacitor group through the first contact holes of the first region and electrically connected to the capacitor group through the second contact holes of the first region, and the other of the control circuits is electrically connected to the capacitor group through the first contact holes of the second region and electrically connected to the capacitor group through the second contact holes of the second region.

[0026] A memory comprising a plurality of memory cells as claimed in any one of the preceding embodiments.

[0027] In one of the embodiments, the memory further comprises a temperature sensor, the temperature sensor is connected to the control circuit, and the temperature sensor is used to detect the temperature of the memory as the temperature of the memory cell.

[0028] In one of the embodiments, the memory is a dynamic random access memory.

[0029] An electronic device comprising a memory as claimed in any one of the preceding embodiments.

[0030] A control method of a memory cell, the memory cell comprising a capacitor group, a contact pad, and a control circuit; the contact pad is formed above the capacitor, a plurality of first contact holes and a plurality of second contact holes are formed in the contact pad; the control circuit is electrically connected to the capacitor group through each of the first contact holes and electrically connected to the capacitor group through each of the second contact holes; the method comprises:

[0031] When the temperature of the memory cell is higher than a preset temperature, the control circuit outputs a cell plate voltage to the capacitor group through the first contact holes and outputs a cell plate voltage to the capacitor group through the second contact holes;

[0032] When the temperature of the memory cell is lower than the preset temperature, the control circuit outputs a cell plate voltage to the capacitor group through the first contact holes and stops outputting a voltage to the capacitor group through the second contact holes.

[0033] In one of the embodiments, the control circuit comprises a first input end, a second input end, a first output end, a second output end, a first switch unit, a second switch unit, an OR gate and an AND gate; the first input end is connected with a temperature sensor signal line, the second input end is connected with a storage unit selection signal line; the first output end is electrically connected with the capacitor group through each first contact hole; the second output end is electrically connected with the capacitor group through each second contact hole; two input ends of the OR gate are connected with the first input end and the second input end respectively, an output end of the OR gate is connected with a control end of the first switch unit, an input end of the first switch unit inputs the cell plate voltage, an output end of the first switch unit is connected with the first output end, when the control end of the first switch unit receives a high level, the input end and the output end of the first switch unit are connected, and when the control end of the first switch unit receives a low level, the input end and the output end of the first switch unit are disconnected; two input ends of the AND gate are connected with the first input end and the second input end respectively, an output end of the AND gate is connected with a control end of the second switch unit, an input end of the second switch unit inputs the cell plate voltage, an output end of the second switch unit is connected with the second output end, when the control end of the second switch unit receives a high level, the input end and the output end of the second switch unit are connected, and when the control end of the second switch unit receives a low level, the input end and the output end of the second switch unit are disconnected; the method further comprises:

[0034] when the temperature of the storage unit is higher than the preset temperature, controlling the temperature sensor signal line to input a high level to the first input end, and controlling the storage unit selection signal line to input a high level to the second input end;

[0035] when the temperature of the storage unit is lower than the preset temperature, controlling the temperature sensor signal line to input a low level to the first input end, and controlling the storage unit selection signal line to input a high level to the second input end.

[0036] In one of the embodiments, the preset temperature ranges from 80 degrees to 90 degrees.

[0037] The above storage unit, the control method of the storage unit, the memory and the electronic device, when the temperature of the storage unit is lower than the preset temperature, the storage unit only outputs the cell plate voltage to the capacitor group through the first contact hole, when the temperature of the storage unit is higher than the preset temperature, the control circuit outputs the cell plate voltage to the capacitor group through the first contact hole and through the second contact hole, so that the metal resistance of the storage unit operating at a high temperature is effectively reduced, and thus the cell plate voltage can be effectively applied to the capacitor in the capacitor group, and the performance of the storage device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description only only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of these drawings.

[0039] Figure 1 The structural schematic diagram of the storage unit provided in an embodiment of the present application is shown in the figure.

[0040] Figure 2 The circuit diagram of the control circuit provided in an embodiment of the present application is shown in the figure.

[0041] Figure 3 The waveform diagram of the input signal and the output signal of the control circuit provided in an embodiment of the present application is shown in the figure.

[0042] Figure 4 The flow chart of the control method of the storage unit provided in an embodiment of the present application is shown in the figure.

[0043] Explanation of reference signs:

[0044] 11, contact pad; 12, control circuit; 13, second contact pad; 14, third contact pad; 111, first contact hole; 112, second contact hole; 121, OR gate; 122, AND gate; 21, first region; 22, second region; 211, first contact hole region; 212, second contact hole region; 123, first switch unit; 124, second switch unit. DETAILED DESCRIPTION

[0045] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The preferred embodiments of the present application are shown in the accompanying drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0047] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type being different doped types, e.g., a first doped type can be P-type and a second doped type can be N-type, or a first doped type can be N-type and a second doped type can be P-type.

[0048] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0049] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Also, as used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0051] Figure 1 This is a schematic diagram of the structure of a storage unit provided in one embodiment of this application. Please refer to [link / reference]. Figure 1 The storage unit includes a capacitor bank (not shown), a contact pad 11, and a control circuit 12. The contact pad 11 is located above the capacitor bank, and has multiple first contact holes 111 and multiple second contact holes 112 formed within it. The control circuit 12 is electrically connected to the capacitor bank through each of the first contact holes 111 and each of the second contact holes 112. The control circuit 12 is used to output a cell plate voltage to the capacitor bank through the first contact holes 111 and the second contact holes 112 when the temperature of the storage unit is higher than a preset temperature; and to output a cell plate voltage to the capacitor bank through the first contact holes 111 and stop outputting voltage to the capacitor bank through the second contact holes 112 when the temperature of the storage unit is lower than the preset temperature.

[0052] Specifically, the capacitor group can include one or more capacitors. The contact pad 11 is located above the capacitor group. The contact pad 11 can be in direct contact with one electrode of each capacitor in the capacitor group; or a capacitor lead-out layer can be provided between the capacitor group and the contact pad 11, and one electrode of each capacitor in the capacitor group is electrically connected to the electrode lead-out layer, thereby leading out one electrode of each capacitor, and the contact pad 11 is in contact with the capacitor lead-out layer. A plurality of first contact holes 111 and a plurality of second contact holes 112 are formed in the contact pad 11. The number of the first contact holes 111 and the second contact holes 112 and their positions on the contact pad 11 can be configured according to actual needs. The first contact holes 111 and the second contact holes 112 can each be provided with a conductive structure that is in electrical contact with one electrode of each capacitor in the capacitor group or in electrical contact with the electrode lead-out layer, and the conductive structures in the first contact holes 111 and the second contact holes 112 can be respectively electrically connected to two output terminals of the control circuit 12 through wires; or the two output terminals of the control circuit 12 can be directly connected to one electrode of each capacitor in the capacitor group or to the electrode lead-out layer through the first contact holes 111 and the second contact holes 112 through wires.

[0053] One input terminal of the control circuit 12 can input a cell plate voltage, or a voltage regulating module can be provided in the control circuit 12, which is used to convert the input voltage of the control circuit 12 into a cell plate voltage. A temperature sensor, such as a thermal resistance or a thermocouple, can be provided, which is used to measure the temperature of the storage unit. When the temperature of the storage unit is lower than a preset temperature, the control circuit 12 outputs the cell plate voltage to the capacitor group only through the first contact holes 111; when the temperature of the storage unit is higher than the preset temperature, the control circuit 12 outputs the cell plate voltage to the capacitor group through the first contact holes 111 and the second contact holes 112, that is, when the temperature of the storage unit is higher than the preset temperature, the number of conductive internal structures (wires or conductive structures) increases, thereby reducing the metal resistance.

[0054] The above-mentioned storage unit outputs the cell plate voltage to the capacitor group only through the first contact holes 111 when the temperature is lower than the preset temperature, and the control circuit 12 outputs the cell plate voltage to the capacitor group through the first contact holes 111 and the second contact holes 112 when the temperature is higher than the preset temperature, thereby effectively reducing the metal resistance of the storage unit when operating at high temperature, so that the cell plate voltage can be effectively applied to the capacitors in the capacitor group.

[0055] In some examples, the capacitor group can include a plurality of capacitors, which can be arranged in an array or irregularly.

[0056] In some examples, the memory cell can further include an electrode lead-out layer (not shown in the figure). The electrode lead-out layer can be located between the capacitor group and the contact pad 11, and can be referred to as the upper electrode plate of the capacitor group. One electrode of each capacitor is electrically connected to the electrode lead-out layer, and the electrode lead-out layer is in contact with the contact pad 11, so that each first contact hole 111 and each second contact hole 112 are in communication with the electrode lead-out layer, thereby facilitating electrical connection of the two output terminals of the control circuit 12 to the capacitor group through the first contact hole 111 and the second contact hole 112, respectively.

[0057] In some examples, the contact pad 11 can include a first contact hole region 211 and a second contact hole region 212. The first contact hole region 211 can be located at an edge region of the contact pad 11, and the second contact hole region 212 can be located at a central region of the contact pad 11. Each first contact hole 111 is formed in the first contact hole region 211, and each second contact hole 112 is formed in the second contact hole region 212.

[0058] In some examples, the memory cell can include two control circuits 12. The contact pad 11 includes a first region 21 and a second region 22. The first region 21 and the second region 22 each include a plurality of first contact holes 111 and a plurality of second contact holes 112. One of the control circuits 12 is electrically connected to the capacitor group through the first contact holes 111 of the first region 21 and electrically connected to the capacitor group through the second contact holes 112 of the first region 21. The other control circuit 12 is electrically connected to the capacitor group through the first contact holes 111 of the second region 22 and electrically connected to the capacitor group through the second contact holes 112 of the second region 22.

[0059] In some examples, the memory cell can further include a second contact pad 13 and a third contact pad 14. The second contact pad 13 is located between the control circuit 12 and the contact pad 11, and the third contact pad 14 is located on a side of the contact pad 11 away from the second contact pad 13. The leads leading out of the two output terminals of the control circuit 12 pass through the second contact pad 13 and the contact pad 11 in sequence and then reach the third contact pad 14.

[0060] In some examples, please refer to Figure 1 and 2The control circuit 12 includes a first input terminal X1, a second input terminal X2, a first output terminal X3, a second output terminal X4, a first switch unit 123, a second switch unit 124, an OR gate 121 and an AND gate 122. The first input terminal X1 of the control circuit 12 is connected with a temperature sensor signal line, so as to input a temperature signal TS_S to the first input terminal X1 of the control circuit 12. The second input terminal X2 of the control circuit 12 is connected with a storage unit selection signal line. The storage unit can include a plurality of storage units. The storage unit inputs a selection signal BG_S to the second input terminal X2 of the temperature sensor through the storage unit selection signal line.

[0061] The first output terminal X3 of the control circuit 12 is electrically connected with the capacitor group through each first contact hole 111. For example, the conductive structure is arranged in each first contact hole 111 in the contact pad 11. The first pads can be arranged on the upper surface of the contact pad 11 corresponding to the positions of the first contact holes 111. The lead wire leading out from the first output terminal X3 of the control circuit 12 is welded with each first pad, so that the first output terminal X3 of the control circuit 12 is electrically connected with the capacitor group through the first contact hole 111. The second output terminal X4 of the control circuit 12 is electrically connected with the capacitor group through each second contact hole 112. For example, the conductive structure is arranged in each second contact hole 112 in the contact pad 11. The second pads can be arranged on the upper surface of the contact pad 11 corresponding to the positions of the second contact holes 112. The lead wire leading out from the second output terminal X4 of the control circuit 12 is welded with each second pad, so that the second output terminal X4 of the control circuit 12 is electrically connected with the capacitor group through the second contact hole 112.

[0062] The input terminal (not shown in the figure) of the first switch unit 123 inputs a cell plate voltage. The control terminal of the first switch unit 123 is connected with the output terminal X5 of the OR gate 121. The output terminal of the first switch unit 123 is connected with the first output terminal X3 of the control circuit 12. The first switch unit 123 controls the output of the cell plate voltage to the capacitor group through the first contact hole 111 or stops the output of the cell plate voltage to the capacitor group through the first contact hole 111 according to the signal of the control terminal. The specific control mode can be set according to actual needs.

[0063] The input end (not shown in the figure) of the second switch unit 124 inputs the cell plate voltage, the control end of the second switch unit 124 is connected with the output end X6 of the AND gate 122, and the output end of the second switch unit 124 is connected with the second output end X4 of the control circuit 12. The second switch unit 124 controls the output of the cell plate voltage to the capacitor group through the second contact hole 112 according to the signal of the control end, or stops the output of the cell plate voltage to the capacitor group through the second contact hole 112, and the specific control mode can be set according to the actual demand. The two input ends of the OR gate 121 are respectively connected with the first input end X1 and the second input end X2 of the control circuit 12, that is, the two input ends of the OR gate 121 respectively input the temperature signal TS_S and the selection signal BG_S of the storage unit. The output end X5 of the OR gate 121 is connected with the control end of the first switch unit 123. The two input ends of the AND gate 122 are respectively connected with the first input end X1 and the second input end X2 of the control circuit 12, that is, the two input ends of the AND gate 122 respectively input the temperature signal TS_S and the selection signal BG_S of the storage unit. The output end X6 of the AND gate 122 is connected with the control end of the second switch unit 124.

[0064] In some examples, the first switch unit 123 can be configured to be conductive between the input end and the output end when the control end receives a high level, so that the control circuit 12 outputs the cell plate voltage to the capacitor group through the first contact hole 111. When the control end of the first switch unit 123 receives a low level, the input end and the output end of the first switch unit 123 are disconnected, so that the control circuit 12 stops outputting the cell plate voltage to the capacitor group through the first contact hole 111.

[0065] When the temperature of the storage unit is higher than the preset temperature, the temperature sensor signal line inputs a high level to the first input end X1 of the control circuit 12, and the storage unit selection signal line inputs a high level to the second input end X2 of the control circuit 12.

[0066] Specifically, please refer to Figure 2 and Figure 3When the temperature of the storage unit is higher than the preset temperature, the temperature signal TS_S is high level, the storage unit selection signal BG_S is high level, and the first output signal CT_S1 outputted by the output end X5 of the OR gate 121 is high level after passing through the OR gate 121, so that the input end and the output end of the first switch unit 123 are conducted, and the first output end X3 of the control circuit 12 outputs the unit plate voltage to the upper plate of the capacitor group through the first contact hole 111. The second output signal CT_S2 outputted by the output end X6 of the AND gate 122 is high level after passing through the AND gate 122, so that the input end and the output end of the second switch unit 124 are conducted, and the second output end X4 of the control circuit 12 outputs the unit plate voltage to the upper plate of the capacitor group through the second contact hole 112.

[0067] When the control end of the second switch unit 124 receives the high level, the input end and the output end of the second switch unit 124 are conducted, so that the control circuit 12 outputs the unit plate voltage to the capacitor group through the second contact hole 111. When the control end of the second switch unit 124 receives the low level, the input end and the output end of the second switch unit 124 are disconnected, so that the control circuit 12 stops outputting the unit plate voltage to the capacitor group through the second contact hole 111.

[0068] When the temperature of the storage unit is lower than the preset temperature, the temperature sensor signal line inputs the low level to the first input end X1 of the control circuit 12, and the storage unit selection signal line inputs the high level to the second input end X2 of the control circuit 12.

[0069] Specifically, please refer to Figure 2 and Figure 3 When the temperature of the storage unit is lower than the preset temperature, the temperature signal TS_S is low level, the storage unit selection signal BG_S is high level, and the first output signal CT_S1 outputted by the output end X5 of the OR gate 121 is high level after passing through the OR gate 121, so that the input end and the output end of the first switch unit 123 are conducted, and the first output end X3 of the control circuit 12 outputs the unit plate voltage to the upper plate of the capacitor group through the first contact hole 111. The second output signal CT_S2 outputted by the output end X6 of the AND gate 122 is low level after passing through the AND gate 122, so that the input end and the output end of the second switch unit 124 are disconnected, and the second output end X4 of the control circuit 12 stops outputting the unit plate voltage to the upper plate of the capacitor group through the second contact hole 112.

[0070] In some examples, a comparison circuit can be arranged between the temperature sensor and the first input terminal X1 of the control circuit 12, the signal output by the temperature sensor and the signal corresponding to the preset temperature being respectively taken as two input signals of the comparison circuit, when the temperature corresponding to the signal output by the temperature sensor is greater than the preset temperature, the temperature signal TS_S output by the comparison circuit is high, and when the temperature corresponding to the signal output by the temperature sensor is less than the preset temperature, the temperature signal TS_S output by the comparison circuit is low.

[0071] In other examples, an analog-digital conversion module and a master control module can be arranged, and the temperature sensor, the analog-digital conversion module, the master control module and the control circuit 12 are connected in sequence. The analog-digital conversion module converts the temperature measured by the temperature sensor into a digital signal. The master control circuit compares the digital signal with the preset temperature, when the temperature measured by the temperature sensor is greater than the preset temperature, the temperature signal TS_S output by the master control circuit is high, and when the temperature measured by the temperature sensor is less than the preset temperature, the temperature signal TS_S output by the master control circuit is low.

[0072] In some examples, the preset temperature ranges from 80 degrees to 90 degrees. Optionally, the preset temperature can be 80 degrees, 82 degrees, 85 degrees, 88 degrees or 90 degrees, etc.

[0073] The application also provides a memory. The memory comprises the storage unit in any one of the above examples.

[0074] In some examples, the memory further comprises a temperature sensor, the temperature sensor being connected with the control circuit 12, and the temperature sensor being used to detect the temperature of the memory as the temperature of the storage unit. The memory can comprise a plurality of storage units. One temperature sensor can be configured for each storage unit to respectively detect the temperature of the corresponding storage unit, or one temperature sensor can be arranged, the position of the temperature sensor can be set according to actual needs, and the temperature sensor can detect the overall temperature of the memory and take the temperature detected by the temperature sensor as the temperature of all the storage units in the memory.

[0075] In some examples, the memory can be a dynamic random access memory.

[0076] The application also provides an electronic device. The electronic device comprises the memory in any one of the above examples, for example, the electronic device can be a mobile phone, a tablet computer or a hard disk, etc.

[0077] The application also provides a control method of a storage unit. The storage unit comprises a capacitor group, a contact pad and a control circuit. The contact pad is formed above the capacitor, and a plurality of first contact holes and a plurality of second contact holes are formed in the contact pad. The control circuit is electrically connected with the capacitor group through each first contact hole and is electrically connected with the capacitor group through each second contact hole. Please refer to Figure 4The storage unit control method comprises the following steps:

[0078] In step S11, it is determined whether the temperature of the storage unit is higher than a preset temperature or lower than the preset temperature.

[0079] Specifically, a temperature sensor can be configured to detect the temperature of the storage unit. If the temperature of the storage unit is higher than the preset temperature, step S12 is performed, and if the temperature of the storage unit is lower than the preset temperature, step S13 is performed.

[0080] In step S12, the control circuit outputs the cell plate voltage to the capacitor group through the first contact hole and outputs the cell plate voltage to the capacitor group through the second contact hole.

[0081] In step S13, the control circuit outputs the cell plate voltage to the capacitor group through the first contact hole and stops outputting the voltage to the capacitor group through the second contact hole.

[0082] In some examples, the control circuit comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first switch unit, a second switch unit, an OR gate, and an AND gate. The first input terminal is connected to a temperature sensor signal line, and the second input terminal is connected to a storage unit selection signal line. The first output terminal is electrically connected to the capacitor group through each first contact hole. The second output terminal is electrically connected to the capacitor group through each second contact hole. Two input terminals of the OR gate are respectively connected to the first input terminal and the second input terminal, and an output terminal of the OR gate is connected to a control terminal of the first switch unit. An input terminal of the first switch unit inputs the cell plate voltage, an output terminal of the first switch unit is connected to the first output terminal, and when the control terminal of the first switch unit receives a high level, the input terminal and the output terminal of the first switch unit are conductive, and when the control terminal of the first switch unit receives a low level, the input terminal and the output terminal of the first switch unit are disconnected. Two input terminals of the AND gate are respectively connected to the first input terminal and the second input terminal, and an output terminal of the AND gate is connected to a control terminal of the second switch unit. An input terminal of the second switch unit inputs the cell plate voltage, an output terminal of the second switch unit is connected to the second output terminal, and when the control terminal of the second switch unit receives a high level, the input terminal and the output terminal of the second switch unit are conductive, and when the control terminal of the second switch unit receives a low level, the input terminal and the output terminal of the second switch unit are disconnected. The storage unit control method further comprises the following steps: when the temperature of the storage unit is higher than the preset temperature, controlling the temperature sensor signal line to input a high level to the first input terminal and controlling the storage unit selection signal line to input a high level to the second input terminal; and when the temperature of the storage unit is lower than the preset temperature, controlling the temperature sensor signal line to input a low level to the first input terminal and controlling the storage unit selection signal line to input a high level to the second input terminal.

[0083] In some examples, the preset temperature ranges from 80 degrees to 90 degrees.

[0084] It should be understood that, although Figure 4 The steps in the flowcharts are shown in sequence according to the arrows, but the steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, the execution of the steps is not strictly limited in sequence, and the steps can be executed in other sequences. Moreover, Figure 4 At least a part of the steps in the flowcharts can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of the steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least a part of other steps or steps or stages in other steps.

[0085] The technical features of the above-described embodiments can be combined in any manner. For the sake of brevity, not all possible combinations of the technical features of the above-described embodiments are described, but it should be understood that any combination of the technical features is within the scope of the present disclosure as long as there is no contradiction.

[0086] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these are all within the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.

Claims

1. A storage unit, characterized in that, include: Capacitor bank; A contact pad is located above the capacitor bank, and a plurality of first contact holes and a plurality of second contact holes are formed in the contact pad; The control circuit is electrically connected to the capacitor bank through each of the first contact holes and through each of the second contact holes. The control circuit is used to output the unit plate voltage to the capacitor bank through the first contact holes and the second contact holes when the temperature of the storage unit is higher than the preset temperature, and to output the unit plate voltage to the capacitor bank through the first contact holes and stop outputting voltage to the capacitor bank through the second contact holes when the temperature of the storage unit is lower than the preset temperature.

2. The storage unit according to claim 1, characterized in that, The control circuit includes: The first input terminal is connected to the temperature sensor signal line; The second input terminal is connected to the memory cell selection signal line; The first output terminal is electrically connected to the capacitor bank through each of the first contact holes; The second output terminal is electrically connected to the capacitor bank through each of the second contact holes; The first switching unit has the unit plate voltage input at its input terminal and its output terminal connected to the first output terminal. The OR gate has its two input terminals connected to the first input terminal and the second input terminal, respectively, and its output terminal connected to the control terminal of the first switching unit. The second switching unit has the unit plate voltage input at its input terminal and its output terminal connected to the second output terminal. The AND gate has its two input terminals connected to the first input terminal and the second input terminal, respectively, and its output terminal connected to the control terminal of the second switching unit.

3. The storage unit according to claim 2, characterized in that, When the control terminal of the first switch unit receives a high level, the input and output terminals of the first switch unit are connected, and when the control terminal of the first switch unit receives a low level, the input and output terminals of the first switch unit are disconnected; when the control terminal of the second switch unit receives a high level, the input and output terminals of the second switch unit are connected, and when the control terminal of the second switch unit receives a low level, the input and output terminals of the second switch unit are disconnected. When the temperature of the storage unit is higher than the preset temperature, the temperature sensor signal line inputs a high level to the first input terminal of the control circuit, and the storage unit selection signal line inputs a high level to the second input terminal of the control circuit. When the temperature of the storage unit is lower than the preset temperature, the temperature sensor signal line inputs a low level to the first input terminal of the control circuit, and the storage unit selection signal line inputs a high level to the second input terminal of the control circuit.

4. The storage unit according to claim 1, characterized in that, The preset temperature range is 80 degrees to 90 degrees.

5. The storage unit according to claim 1, characterized in that, The capacitor bank comprises multiple capacitors arranged in an array.

6. The storage unit according to claim 5, characterized in that, It also includes an electrode lead-out layer, which is located between the capacitor group and the contact pad. One electrode of each capacitor is electrically connected to the electrode lead-out layer, and each of the first contact holes and each of the second contact holes are connected to the electrode lead-out layer.

7. The storage unit according to claim 1, characterized in that, The contact pad includes a first contact hole region and a second contact hole region. The first contact hole region is located at the edge region of the contact pad, and the second contact hole region is located at the center region of the contact pad. Each first contact hole is formed in the first contact hole region, and each second contact hole is formed in the second contact hole region.

8. The storage unit according to claim 1, characterized in that, The storage unit includes two control circuits. The contact pad includes a first region and a second region. Both the first region and the second region include multiple first contact holes and multiple second contact holes. One of the control circuits is electrically connected to the capacitor bank through the first contact hole in the first region and also through the second contact hole in the first region. The other control circuit is electrically connected to the capacitor bank through the first contact hole in the second region and also through the second contact hole in the second region.

9. A memory, characterized in that, It includes multiple storage units as described in any one of claims 1 to 8.

10. The memory according to claim 9, characterized in that, The memory also includes a temperature sensor connected to the control circuit, which is used to detect the temperature of the memory as the temperature of the storage unit.

11. The memory according to claim 9, characterized in that, The memory is a dynamic random access memory.

12. An electronic device, characterized in that, Includes the memory as described in any one of claims 9 to 11.

13. A method for controlling a storage unit, characterized in that, The storage unit includes a capacitor bank, a contact pad, and a control circuit; the contact pad is formed above the capacitor, and a plurality of first contact holes and a plurality of second contact holes are formed in the contact pad. The control circuit is electrically connected to the capacitor bank through each of the first contact holes and also electrically connected to the capacitor bank through each of the second contact holes; the method includes: When the temperature of the storage unit is higher than the preset temperature, the control circuit outputs the unit plate voltage to the capacitor bank through the first contact hole and the unit plate voltage to the capacitor bank through the second contact hole. When the temperature of the storage unit is lower than the preset temperature, the control circuit outputs the unit plate voltage to the capacitor bank through the first contact hole and stops outputting voltage to the capacitor bank through the second contact hole.

14. The control method for a storage cell according to claim 13, characterized in that, The control circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first switching unit, a second switching unit, an OR gate, and an AND gate. The first input terminal is connected to the temperature sensor signal line, and the second input terminal is connected to the memory unit selection signal line. The first output terminal is electrically connected to the capacitor bank through each of the first contact holes. The second output terminal is electrically connected to the capacitor bank through each of the second contact holes. The two input terminals of the OR gate are respectively connected to the first input terminal and the second input terminal. The output terminal of the OR gate is connected to the control terminal of the first switching unit. The input terminal of the first switching unit receives the unit plate voltage, and the output terminal of the first switching unit is connected to the first output terminal. The control terminal of the first switching unit is connected to... When a high level is received, the input and output terminals of the first switching unit are connected, and when the control terminal of the first switching unit receives a low level, the input and output terminals of the first switching unit are disconnected; the two input terminals of the AND gate are respectively connected to the first input terminal and the second input terminal, the output terminal of the AND gate is connected to the control terminal of the second switching unit, the input terminal of the second switching unit receives the plate voltage of the unit, the output terminal of the second switching unit is connected to the second output terminal, when the control terminal of the second switching unit receives a high level, the input and output terminals of the second switching unit are connected, and when the control terminal of the second switching unit receives a low level, the input and output terminals of the second switching unit are disconnected; the method further includes: When the temperature of the storage unit is higher than the preset temperature, the temperature sensor signal line is controlled to input a high level to the first input terminal, and the storage unit selection signal line is controlled to input a high level to the second input terminal. When the temperature of the storage unit is lower than the preset temperature, the temperature sensor signal line is controlled to input a low level to the first input terminal, and the storage unit selection signal line is controlled to input a high level to the second input terminal.

15. The control method for a storage cell according to claim 14, characterized in that, The preset temperature range is 80 degrees to 90 degrees.

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