Split-gate flash memory cell and method of making same

Abstract

The application provides a split-gate flash memory cell and a preparation method thereof, which comprises a substrate, a first split-gate structure and a second split-gate structure located on the substrate and each comprising a floating gate and an erase gate arranged from bottom to top, wherein the erase gate covers part of the top surface of the floating gate; a source line layer located between the first split-gate structure and the second split-gate structure and comprising two first parts electrically connected and a second part located between the two first parts, each of the first parts covering the remaining top surface of the corresponding floating gate and extending upwards to cover the side surface of the corresponding erase gate, and the second part covering the substrate; and a source region located in the substrate below the second part and electrically connected with the second part. The application simplifies the interconnection process and the preparation process, reduces the source contact resistance and is conducive to reducing the area of the split-gate flash memory cell.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a split-gate flash memory unit and a preparation method thereof. Background Art

[0002] Flash memory, as a non-volatile memory, stores data by changing the threshold voltage of transistors or storage cells to control the switching of gate channels. This prevents the data stored in the memory from disappearing due to power outages. Flash memory, as a special structure of electrically erasable and programmable read-only memory, now occupies the majority of the market share of non-volatile semiconductor memory and has become the fastest-growing non-volatile semiconductor memory.

[0003] Figure 1 This is a cross-sectional diagram of a split-gate flash memory cell. Figure 1 The source region 20' is located in the substrate 10' below the erase gate 30'. The source region 20' and the erase gate 30' are isolated by an oxide layer 40'. The floating gate 50' is located on both sides of the erase gate 30'. In the subsequent interconnection process, a source electrical connector (not shown in the figure) needs to be formed to pass through the erase gate 30' and electrically connect to the source region 20'. Because the source electrical connector passes through the erase gate 30', the contact resistance of the electrical connector is large, that is, the interconnection contact resistance is large. In addition, the erase gate 30' needs to be led out through the erase gate electrical connector (not shown in the figure). The interconnection layout is relatively complex and the interconnection process requirements are relatively high. In addition, the device structure generally requires that the source region 20' and the floating gate 50' have a certain width of overlap in the lateral direction as a coupling portion (shown in the dotted box in the figure). The coupling portion is used to ensure the coupling coefficient between the source region 20' and the floating gate 50', which is beneficial for programming the split-gate flash memory cell. Therefore, in order to ensure that the source region 20' and the floating gate 50' have a certain width of overlap in the lateral direction, the width of the floating gate 50' cannot be too small, which makes it difficult to reduce the size of the device. Summary of the Invention

[0004] The object of the present invention is to provide a split-gate flash memory cell and a method for manufacturing the same, so as to simplify the interconnection process and the manufacturing process, reduce the source contact resistance and facilitate the reduction of the area of ​​the split-gate flash memory cell.

[0005] In order to achieve the above object, the present invention provides a split-gate flash memory cell, comprising:

[0006] substrate;

[0007] A first split-gate structure and a second split-gate structure are located on the substrate and each include a floating gate and an erase gate arranged from bottom to top, wherein the erase gate covers a portion of the top surface of the floating gate;

[0008] a source line layer, located between the first split gate structure and the second split gate structure, and comprising two electrically connected first portions and a second portion located between the two first portions, each first portion covering the remaining top surface of the corresponding floating gate and extending upward to cover the side surface of the corresponding erase gate, and the second portion covering the substrate;

[0009] The source region is located in the substrate below the second portion and is electrically connected to the second portion.

[0010] Optionally, the first split gate structure and the second split gate structure each further include a first sidewall spacer, and the first sidewall spacer covers a top surface of the erase gate and side surfaces of the erase gate and the floating gate close to the source line layer.

[0011] Optionally, the first split gate structure and the second split gate structure also include a second sidewall and a word line gate, the second sidewall covers the corresponding side of the floating gate and the erase gate away from the source line layer, and the word line gate covers the surface of the corresponding second sidewall.

[0012] Optionally, two drain regions are further included, each located in the substrate outside each word line gate.

[0013] Optionally, the source line layer is made of polysilicon.

[0014] The present invention also provides a method for preparing a split-gate flash memory cell, comprising:

[0015] providing a substrate; and,

[0016] A first split-gate structure and a second split-gate structure are formed on the substrate, and both include a floating gate and an erase gate arranged from bottom to top, the erase gate covering a portion of the top surface of the floating gate, and a source line layer is formed between the first split-gate structure and the second split-gate structure, and includes two electrically connected first portions and a second portion located between the two first portions, each first portion covering the remaining top surface of the corresponding floating gate and extending upward to cover the side surface of the corresponding erase gate, and the second portion covering the substrate, forming a source region in the substrate below the second portion and electrically connected to the second portion.

[0017] Optionally, the step of forming the floating gate, the erase gate, the second portion, and the source region includes:

[0018] forming a floating gate material layer, an erase gate material layer and a mask layer in sequence on the substrate;

[0019] etching the mask layer, the erase gate material layer, and the floating gate material layer in sequence to form an opening exposing the substrate;

[0020] performing ion implantation on the substrate at the bottom of the opening to form the source region in the substrate at the bottom of the opening;

[0021] Filling the opening to form the second portion, wherein the second portion is electrically connected to the source region; and

[0022] The mask layer and the floating gate material layer and the erase gate material layer directly below the mask layer are removed by etching, and the remaining floating gate material layer on each side of the opening is used as a floating gate, and the remaining erase gate material layer on each side of the opening is used as an erase gate.

[0023] Optionally, the step of forming the opening and the first portion includes:

[0024] Etching the mask layer to form a first opening exposing the erase gate material layer;

[0025] forming a first sub-spacer on a sidewall of the first opening;

[0026] etching the erase gate material layer using the first sub-spacer as a mask to form a second opening exposing the floating gate material layer;

[0027] forming a second sub-spacer on an inner wall of the second opening, wherein the second sub-spacer covers at least a portion of a surface of the first sub-spacer;

[0028] forming a first portion at least on the second sub-spacer of the sidewall of the second opening, wherein the first portion covers a portion of the surface of the second sub-spacer at the bottom of the second opening;

[0029] Using the first portion as a mask, sequentially etching the second sub-spacer and the floating gate material layer to form a third opening exposing the substrate, wherein the first opening, the second opening, and the third opening are connected to form the opening; and

[0030] A third sub-spacer is formed on the sidewall of the third opening, and the first sub-spacer, the second sub-spacer and the third sub-spacer constitute a first spacer.

[0031] Optionally, after forming the floating gate and the erase gate, the method further includes:

[0032] forming a second spacer on a side of each of the erase gate and the floating gate away from the source line layer; and

[0033] A word line gate is formed on a surface of each of the second spacers.

[0034] Optionally, after forming the word line gate, the method further includes:

[0035] Ion implantation is performed on the substrate outside each word line gate to form a drain region in the substrate.

[0036] In the split-gate flash memory cell and its preparation method provided by the present invention, a first split-gate structure and a second split-gate structure are located on a substrate and both include a floating gate and an erase gate arranged from bottom to top, with the erase gate covering a portion of the top surface of the floating gate; a source line layer is located between the first split-gate structure and the second split-gate structure and includes two electrically connected first portions and a second portion located between the two first portions, each first portion covering the remaining top surface of the corresponding floating gate and extending upward to cover the side of the corresponding erase gate, and the second portion covering the substrate; a source region is located in the substrate below the second portion and electrically connected to the second portion. In the present invention, erasure is performed through the erase gate above the floating gate, and the source region is electrically connected to the source line layer. When the interconnection process is subsequently performed, the source region is led out through the source line layer, which can reduce the source contact resistance (i.e., the interconnection contact resistance) and simplify the interconnection process and the preparation process; and the first portion covers a portion of the top surface of the floating gate, thereby increasing the coupling area between the source line layer and the floating gate, reducing the width of the floating gate, and facilitating the reduction of the area of ​​the split-gate flash memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a cross-sectional schematic diagram of a split-gate flash memory cell;

[0038] Figure 2 A flow chart of a method for preparing a split-gate flash memory cell provided in one embodiment of the present invention;

[0039] Figures 3A to 3I A schematic cross-sectional view of corresponding steps in a method for preparing a split-gate flash memory cell according to an embodiment of the present invention, wherein: Figure 3I A schematic cross-sectional view of a split-gate flash memory cell provided by one embodiment of the present invention;

[0040] Wherein, the accompanying drawings are marked as follows:

[0041] 10, 10'-substrate; 21-gate oxide layer; 22-tunneling oxide layer; 23-word line oxide layer; 30-floating gate material layer; 50', 31-floating gate; 40-erase gate material layer; 30', 41-erase gate; 50-mask layer; 61-first sub-spacer; 62-second sub-spacer; 63-third sub-spacer; 64-second spacer; 71-first opening; 72-second opening; 73-third opening; 81-first portion; 82-second portion; 20', 91-source region; 92-drain region; 100-word line gate; 40'-oxide layer; T1-first sub-gate structure; T2-second sub-gate structure. DETAILED DESCRIPTION

[0042] The following is a more detailed description of the specific embodiments of the present invention with reference to schematic diagrams. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention.

[0043] Figure 3I This is a cross-sectional diagram of the split-gate flash memory cell provided in this embodiment. Figure 3I This embodiment provides a split-gate flash memory cell, including: a substrate 10, a first split-gate structure T1, a first split-gate structure T2, a source line layer, a source region 91 and a drain region 92, wherein the material of the substrate 10 includes one or more of silicon, germanium, gallium, nitrogen or carbon.

[0044] The first split-gate structure T1 and the second split-gate structure T2 are both located on a substrate 10 and include a floating gate 31 and an erase gate 41 arranged from bottom to top. Specifically, the erase gate 41 is located above the floating gate 31 and covers a portion of the top surface of the floating gate 31. Both the floating gate 31 and the erase gate 41 are made of polysilicon. In this embodiment, a gate oxide layer 21 is formed between the floating gate 31 and the substrate 10; and a tunnel oxide layer 22 is formed between the floating gate 31 and the erase gate 41.

[0045] The source line layer is located between the first gate structure T1 and the second gate structure T2. The source line layer includes two electrically connected first parts 81 and a second part 82 located between the two first parts 81. Each first part 81 covers the remaining top surface of the corresponding floating gate 31 and extends upward to cover the side of the corresponding erase gate 41, and the second part 82 covers the substrate 10. In this embodiment, the material of the source line layer is preferably polysilicon, that is, the material of the first part 81 and the second part 82 are both polysilicon. In the subsequent process, a metal silicide layer is formed on the surface of the source line layer, which is beneficial to reducing the contact resistance.

[0046] Furthermore, both the first split-gate structure T1 and the second split-gate structure T2 include a first spacer, which covers the top surface of the erase gate 41 and the side surfaces of the erase gate 41 and the floating gate 31 near the source line layer. Specifically, the first spacer includes a first sub-spacer 61, a second sub-spacer 62, and a third sub-spacer 63, wherein the first sub-spacer 61 is located above the erase gate 41, that is, covers the top surface of the erase gate 41; the second sub-spacer 62 covers the side surfaces of the erase gate 41 and the tunneling oxide layer 22 near the source line layer and a portion of the top surface of the floating gate 31, and extends to cover at least a portion of the surface of the first sub-spacer 61, and the first portion 81 covers the second sub-spacer 62; the third sub-spacer 63 covers the side surfaces of the floating gate 31 and the gate oxide layer 21 near the second portion 82, and can extend to cover the side surfaces of the second sub-spacer 62 near the second portion 82.

[0047] The source region 91 is located in the substrate 10 below the second portion 82 , and the source region 91 is electrically connected to the second portion 82 , that is, the source region 91 is in direct contact with the second portion 82 , thereby achieving electrical connection between the source region 91 and the source line layer.

[0048] The first split-gate structure T1 and the second split-gate structure T2 also include a second spacer 64, a wordline gate 100, and a wordline oxide layer 23. The second spacer 64 covers the corresponding side surfaces of the gate oxide layer 21, floating gate 31, tunnel oxide layer 22, and erase gate 41 away from the source line layer and extends to cover at least a portion of the surface of the first sub-spacer 61. The wordline oxide layer 23 covers a portion of the surface of the substrate 10 and a portion of the surface of the second spacer 64. The wordline gate 100 is located on the wordline oxide layer 23 and covers the remaining surface of the corresponding second spacer 64. It can also extend to cover a portion of the side surface of the first sub-spacer 61 away from the source line layer 90. In this embodiment, the first split-gate structure T1 and the second split-gate structure T2 are symmetrically arranged around the source line layer. For ease of illustration, the first split-gate structure T1 and the second split-gate structure T2 are simply circled with a dotted rectangular frame in the figure. The circled portion does not represent all of the first split-gate structure T1 and the second split-gate structure T2. For the specific portions of the first split-gate structure T1 and the second split-gate structure T2, please refer to the description of this embodiment.

[0049] Furthermore, two drain regions 92 are included, each located in the substrate 10 outside each word line gate 100 , ie, located in the substrate 10 outside the word line gate 100 of the first split gate structure T1 and the word line gate 100 of the second split gate structure T2 .

[0050] Furthermore, it also includes the formation of a passivation layer, a source electrical connector and an erase gate electrical connector (all not shown in the figures), wherein the passivation layer covers the first sub-gate structure T1, the second sub-gate structure T2, the source line layer and the substrate 10, the source electrical connector passes through the passivation layer and is electrically connected to the source line layer, the erase gate electrical connector passes through the passivation layer and the first sub-side wall 61 and is electrically connected to the erase gate 41, and in addition, a floating gate electrical connector, a word line gate electrical connector and a drain region electrical connector (all not shown in the figures) are formed and are electrically connected to the floating gate 31, the word line gate 100 and the drain region 92 respectively.

[0051] In this embodiment, when the split-gate flash memory cell is erased, the erase gate 41 is connected to a relatively high positive voltage, and the other portions are kept at zero potential. Erasure is performed by electron tunneling from the floating gate 31 to the erase gate 41, so that electrons are pulled out from the floating gate 31 through the tunneling oxide layer 22. When the split-gate flash memory cell is read, the word line gate 100 is connected to the power supply voltage VDD, the source region 91 is connected to the read voltage, and the other portions are kept at zero potential to achieve reading. When the split-gate flash memory cell is written, the word line gate 100 is connected to the power supply voltage VDD, the source region 91 is connected to the write voltage, and the source line layer and the erase gate 41 are connected to a positive voltage to achieve writing.

[0052] In this embodiment, the floating gate 31 is erased through the erase gate 41 above. During erasure, the erase gate 41 is connected to a high voltage, and erasure is performed by electron tunneling from the floating gate 31 to the erase gate 41. The source region 91 is led out through the source line layer. During the subsequent interconnection process, there is no need to form a source electrical connector passing through the erase gate 41. The source electrical connector can be directly electrically connected to the source line layer. On the one hand, the source contact resistance can be reduced (i.e., the interconnection contact resistance is reduced). On the other hand, the source electrical connector and the erase gate electrical connector are separated in position on the interconnection layout, which can simplify the interconnection process of the source electrical connector and the erase gate electrical connector, as well as the manufacturing process. In addition, the first portion 81 covers part of the top surface of the floating gate 31, increases the coupling area between the source line layer and the floating gate 31, can reduce the width of the floating gate 31, and is conducive to reducing the area of ​​the split-gate flash memory cell.

[0053] In this embodiment, a split-gate flash memory device is formed using a plurality of split-gate flash memory cells. There is no limitation on how the plurality of split-gate flash memory cells are arranged in this description.

[0054] Figure 2 This is a flow chart of the method for preparing a split-gate flash memory cell provided in this embodiment. Figure 2 This embodiment provides a method for preparing a split-gate flash memory cell, comprising:

[0055] Step S1: providing a substrate; and,

[0056] Step S2: forming a first split-gate structure and a second split-gate structure on a substrate, and both include a floating gate and an erase gate arranged from bottom to top, the erase gate covering a portion of the top surface of the floating gate, forming a source line layer between the first split-gate structure and the second split-gate structure, and including two electrically connected first parts and a second part located between the two first parts, each first part covering the remaining top surface of the corresponding floating gate and extending upward to cover the side of the corresponding erase gate, and the second part covering the substrate, forming a source region in the substrate below the second part, and electrically connected to the second part.

[0057] Figures 3A to 3I The cross-sectional diagram of the corresponding steps in the method for preparing the split gate flash memory cell provided in this embodiment is shown below in conjunction with Figures 3A to 3I The method for preparing the split-gate flash memory cell provided in this embodiment is described in detail.

[0058] Please refer to Figure 3A , performing step S1: providing a substrate 10, wherein the material of the substrate 10 includes one or more of silicon, germanium, gallium, nitrogen or carbon.

[0059] Performing step S2: forming the first split gate structure, the second split gate structure, the source line layer and the source region includes:

[0060] Please continue to refer to Figure 3A A gate oxide layer 21, a floating gate material layer 30, a tunneling oxide layer 22, an erase gate material layer 40 and a mask layer 50 are sequentially formed on the substrate 10, wherein the floating gate material layer 30 and the erase gate material layer 40 are made of polysilicon. In this embodiment, the thicknesses of the gate oxide layer 21, the floating gate material layer 30, the tunneling oxide layer 22, the erase gate material layer 40 and the mask layer 50 are not limited, and the specific thicknesses depend on actual conditions.

[0061] Then, the mask layer 50, the erase gate material layer 40, the tunnel oxide layer 22, the floating gate material layer 21 and the gate oxide layer 21 are sequentially etched to form an opening exposing the substrate 10. The steps of forming the opening specifically include:

[0062] Please refer to Figure 3B , the mask layer 50 is etched to form a first opening 71 exposing the erase gate material layer 40 , and a first sub-spacer 61 is formed on the sidewall of the first opening 71 .

[0063] Please refer to Figure 3C , using the first sub-spacer 61 as a mask, the gate material layer 40 and the tunnel oxide layer 22 are etched and erased to form a second opening 72 exposing the floating gate material layer 30, and a second sub-spacer 62 is formed on the inner wall of the second opening 72, the inner wall of the second opening 72 includes the sidewall and bottom of the second opening 72, and the second sub-spacer 62 extends to cover at least part of the surface of the first sub-spacer 61.

[0064] Please refer to Figure 3D A first polysilicon layer is formed on the second sub-spacer 62 of the side wall of the second opening 72, and the first polysilicon layer is a first portion 81. The first portion 81 covers a portion of the surface of the second sub-spacer 62 at the bottom of the second opening 72, and the first portion 81 can also extend to cover the second sub-spacer 62 of the side wall of the first opening 71 and at least a portion of the surface of the first sub-spacer 61.

[0065] Please refer to Figure 3E , using the first portion 81 as a mask, the second sub-spacer 62 and the floating gate material layer 30 are sequentially etched to form a third opening 73 exposing the substrate 10. The first opening 71, the second opening 72 and the third opening 73 are connected to form an opening. In this embodiment, due to the presence of the gate oxide layer 21, after etching, it is preferred to retain the gate oxide layer 21 at the bottom of the third opening 73 (e.g., Figure 3D ) to reduce damage to the surface of the substrate 10 during subsequent ion implantation, and simultaneously etch away the gate oxide layer 21 at the bottom of the third opening 73 to expose the surface of the substrate 10. Furthermore, ion implantation is performed on the substrate 10 at the bottom of the third opening 73 to form a source region 91 in the substrate 10 at the bottom of the third opening 73.

[0066] For further information, please refer to Figure 3F If the gate oxide layer 21 at the bottom of the third opening 73 is retained after the third opening 73 is formed (e.g. Figure 3D ), the gate oxide layer 21 at the bottom of the third opening 73 is first etched away ( Figure 3F The gate oxide layer 21 at the bottom of the third opening 73 no longer exists, so that the third opening 73 extends to the surface of the substrate 10. Furthermore, a third sub-spacer 63 is formed on the sidewall of the third opening 73, and the third sub-spacer 63 can extend to cover the side surface of the second sub-spacer 62 near the third opening 73. The first sub-spacer 61, the second sub-spacer 62 and the third sub-spacer 63 constitute a first spacer.

[0067] Please refer to Figure 3G After the opening is formed, a second polysilicon layer is filled in the opening. The second polysilicon layer is the second portion 82. The first portion 81 and the second portion 82 constitute the source line layer, that is, the source line layer is filled in the first opening 71, the second opening 72 and the third opening 73. The source region 91 is located in the substrate 10 below the second portion 82. The source region 91 is in direct contact with the second portion 82 so that the source region 91 is electrically connected to the second portion 82, that is, the source region 91 is electrically connected to the source line layer; in the subsequent process, a metal silicide layer is formed on the surface of the source line layer, which is beneficial to reducing the contact resistance.

[0068] Please continue to refer to Figure 3G and references Figure 3H , the mask layer 50 and the erase gate material layer 41, the tunneling oxide layer 22, the floating gate material layer 30 and the gate oxide layer 21 directly below the mask layer 50 are etched away, and the etching stops at the surface of the substrate 10; after etching, the floating gate material layer 30 remaining on each side of the opening serves as a floating gate 31, and the erase gate material layer 41 remaining on each side of the opening serves as an erase gate 41.

[0069] Please refer to Figure 3I After forming the floating gate 31 and the erase gate 41, the method further includes: forming a second spacer 64 on a side of each erase gate 41 and the floating gate 31 away from the source line layer, and the second spacer 64 covers the side of the tunneling oxide layer 22 and the gate oxide layer 21 away from the source line layer 90 and at least a portion of the side of the first sub-spacer 61 away from the source line layer; forming a word line oxide layer 23 on a portion of the surface of each second spacer 64, and the word line oxide layer 23 covers a portion of the surface of the substrate 10; and forming a word line gate 100 on the remaining surface of each second spacer 64, the word line gate 100 is located on the word line oxide layer 23, and can extend to cover a portion of the side of the first sub-spacer 61 away from the source line layer.

[0070] For further information, please refer to Figure 3IAfter forming the word line gates 100, the method further includes: performing ion implantation on the substrate 10 outside each word line gate 100 to form two drain regions 92 in the substrate 10. Before or after forming the drain regions 92, a third spacer (not shown) is formed on the surface of each word line gate 100.

[0071] Furthermore, after the drain region 92 is formed, a passivation layer (not shown in the figure) is formed to cover the first sub-gate structure T1, the second sub-gate structure T2, the source line layer and the substrate 10, a source electrical connector (not shown in the figure) is formed to pass through the passivation layer and electrically connect to the source line layer, an erase gate electrical connector (not shown in the figure) is formed to pass through the passivation layer and the first sub-side wall 61 and electrically connect to the erase gate 41, and in addition, a floating gate electrical connector, a word line gate electrical connector and a drain region electrical connector (all not shown in the figure) are formed to electrically connect to the floating gate 31, the word line gate 100 and the drain region 92, respectively.

[0072] In this embodiment, the floating gate 31 is erased through the erase gate 41 above. During erasure, the erase gate 41 is connected to a high voltage, and erasure is performed by electron tunneling from the floating gate 31 to the erase gate 41. The source region 91 is led out through the source line layer. During the subsequent interconnection process, there is no need to form a source electrical connector passing through the erase gate 41. The source electrical connector can be directly electrically connected to the source line layer. On the one hand, the source contact resistance can be reduced (i.e., the interconnection contact resistance is reduced). On the other hand, the source electrical connector and the erase gate electrical connector are separated in position on the interconnection layout, which can simplify the interconnection process of the source electrical connector and the erase gate electrical connector, as well as the manufacturing process. In addition, the first portion 81 covers part of the top surface of the floating gate 31, increases the coupling area between the source line layer and the floating gate 31, can reduce the width of the floating gate 31, and is conducive to reducing the area of ​​the split-gate flash memory cell.

[0073] In summary, in the split-gate flash memory cell and its preparation method provided by the present invention, the first split-gate structure and the second split-gate structure are located on the substrate and both include a floating gate and an erase gate arranged from bottom to top, the erase gate covering a portion of the top surface of the floating gate; the source line layer is located between the first split-gate structure and the second split-gate structure and includes two electrically connected first portions and a second portion located between the two first portions, each first portion covering the remaining top surface of the corresponding floating gate and extending upward to cover the side of the corresponding erase gate, and the second portion covering the substrate; the source region is located in the substrate below the second portion and electrically connected to the second portion. In the present invention, erasure is performed through the erase gate above the floating gate, the source region is electrically connected to the source line layer, and when the interconnection process is subsequently performed, the source region is led out through the source line layer, which can reduce the source contact resistance (i.e., the interconnection contact resistance) and simplify the interconnection process and the preparation process; and the first portion covers a portion of the top surface of the floating gate, which increases the coupling area between the source line layer and the floating gate, can reduce the width of the floating gate, and is conducive to reducing the area of ​​the split-gate flash memory cell.

[0074] The above description is merely a preferred embodiment of the present invention and does not limit the present invention in any way. Any person skilled in the art who, without departing from the scope of the present invention, makes any equivalent substitution, modification, or other changes to the technical solution and technical content disclosed in the present invention shall be deemed to be within the scope of the present invention and still fall within the scope of protection of the present invention.

Claims

1. A split-gate flash memory cell, characterized in that: include: substrate; A first split-gate structure and a second split-gate structure are located on the substrate and each include a floating gate and an erase gate arranged from bottom to top, wherein the erase gate covers a portion of the top surface of the floating gate; a source line layer, located between the first split gate structure and the second split gate structure, and comprising two electrically connected first portions and a second portion located between the two first portions, each first portion covering a portion of the top surface of the corresponding floating gate and extending upward to cover a side surface of the corresponding erase gate, and the second portion covering the substrate; a source region located in the substrate below the second portion and electrically connected to the second portion; In which, the first split gate structure and the second split gate structure also include a first sidewall, the first sidewall covers the top surface of the erase gate and the side surfaces of the erase gate and the floating gate close to the source line layer, the first sidewall includes a first sub-sidewall, a second sub-sidewall and a third sub-sidewall, the first sub-sidewall covers the top surface of the erase gate, the second sub-sidewall covers the side surface of the erase gate close to the source line layer and part of the top surface of the floating gate, and the first part covers the second sub-sidewall, and the third sub-sidewall covers the side surface of the floating gate close to the second part.

2. The split-gate flash memory cell according to claim 1, wherein: The first split gate structure and the second split gate structure also include a second sidewall and a word line gate. The second sidewall covers the corresponding side of the floating gate and the erase gate away from the source line layer, and the word line gate covers the surface of the corresponding second sidewall.

3. The split-gate flash memory cell according to claim 2, wherein: The invention also includes two drain regions, each of which is located in the substrate outside each word line gate.

4. The split-gate flash memory cell according to claim 1, wherein: The source line layer is made of polysilicon.

5. A method for preparing a split-gate flash memory cell, characterized in that: include: providing a substrate; as well as, A first split-gate structure and a second split-gate structure are formed on the substrate, each including a floating gate and an erase gate arranged from bottom to top, the erase gate covering a portion of the top surface of the floating gate; a source line layer is formed between the first split-gate structure and the second split-gate structure, and includes two electrically connected first portions and a second portion located between the two first portions, each first portion covering a portion of the top surface of a corresponding floating gate and extending upward to cover a side surface of the corresponding erase gate; the second portion covers the substrate; a source region is formed in the substrate below the second portion and electrically connected to the second portion; In which, the first split gate structure and the second split gate structure also include a first sidewall, the first sidewall covers the top surface of the erase gate and the side surfaces of the erase gate and the floating gate close to the source line layer, the first sidewall includes a first sub-sidewall, a second sub-sidewall and a third sub-sidewall, the first sub-sidewall covers the top surface of the erase gate, the second sub-sidewall covers the side surface of the erase gate close to the source line layer and part of the top surface of the floating gate, and the first part covers the second sub-sidewall, and the third sub-sidewall covers the side surface of the floating gate close to the second part.

6. The method for preparing a split-gate flash memory cell according to claim 5, wherein: The steps of forming the floating gate, the erase gate, the second portion and the source region include: forming a floating gate material layer, an erase gate material layer and a mask layer in sequence on the substrate; etching the mask layer, the erase gate material layer, and the floating gate material layer in sequence to form an opening exposing the substrate; performing ion implantation on the substrate at the bottom of the opening to form the source region in the substrate at the bottom of the opening; Filling the opening to form the second portion, wherein the second portion is electrically connected to the source region; and The mask layer and the floating gate material layer and the erase gate material layer directly below the mask layer are removed by etching, and the remaining floating gate material layer on each side of the opening is used as a floating gate, and the remaining erase gate material layer on each side of the opening is used as an erase gate.

7. The method for preparing a split-gate flash memory cell according to claim 6, wherein: The steps of forming the opening and the first portion include: Etching the mask layer to form a first opening exposing the erase gate material layer; forming the first sub-spacer on the sidewall of the first opening; etching the erase gate material layer using the first sub-spacer as a mask to form a second opening exposing the floating gate material layer; forming a second sub-spacer on an inner wall of the second opening, wherein the second sub-spacer covers at least a portion of a surface of the first sub-spacer; forming a first portion at least on the second sub-spacer of the sidewall of the second opening, wherein the first portion covers a portion of the surface of the second sub-spacer at the bottom of the second opening; Using the first portion as a mask, sequentially etching the second sub-spacer and the floating gate material layer to form a third opening exposing the substrate, wherein the first opening, the second opening, and the third opening are connected to form the opening; and The third sub-spacer is formed on the sidewall of the third opening.

8. The method for preparing a split-gate flash memory cell according to claim 6, wherein: After forming the floating gate and the erase gate, the method further includes: forming a second spacer on a side of each of the erase gate and the floating gate away from the source line layer; and A word line gate is formed on a surface of each of the second spacers.

9. The method for preparing a split-gate flash memory cell according to claim 8, wherein: After forming the word line gate, the method further includes: Ion implantation is performed on the substrate outside each word line gate to form a drain region in the substrate.

Images