An adjustable dead band or overlap time generating circuit

Abstract

The present application belongs to the technical field of analog circuit power management, and particularly relates to a kind of adjustable dead zone or overlap time generation circuit.The circuit of the present application includes adjustable current generation circuit, delay circuit and comparator.The adjustable current generation circuit provides adjustable charging and discharging current for the delay circuit to determine the delay time, and the comparator shapes the signal passing through the delay circuit into a square wave signal.Under fixed dead zone or overlap time, the efficiency of switching power supply is relatively low or the power tube has the risk of punch-through under certain application conditions.By adjusting the size of the dead zone or overlap time with an external resistor, the efficiency of the switching power supply under all application conditions can be maximized.In addition, the present application realizes structure reuse and current self-compensation technology, thereby improving circuit utilization and implementation accuracy.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of analog circuit power management, and particularly relates to an adjustable dead zone or overlap time generation circuit which can be applied to a PWM controller to generate adjustable dead zone or overlap time. BACKGROUND

[0002] Power supplies are everywhere in life, and they play their roles in various occasions. With the development of society, people have higher and higher requirements for portable electronic devices, and the demand for power supplies is also increasing. Switching power supply is a common type of power management chip, and its advantages of high efficiency and low power consumption make it occupy an important position in the power supply field.

[0003] In a switching power supply, the driving circuit is a bridge between the control circuit and the main circuit, and the signal of the driving circuit has the demand of dead zone or overlap time. The setting of the dead zone or overlap time needs to be carefully weighed and set. Too small setting will make the power tube have the risk of through; and too large setting will make the efficiency of the switching power supply low. Since the working efficiency of the circuit will change with the change of the dead zone or overlap time, and the highest working efficiency of the dead zone or overlap time depends on different application occasions, input and load conditions, external components, etc., therefore, adjustable dead zone or overlap time has better applicability than fixed dead zone or overlap time. SUMMARY

[0004] The purpose of the application is to solve the problem that the highest working efficiency of the switching power supply under different application conditions needs different dead zone or overlap time. By connecting one end of the external resistance to the power supply or ground, the rising edge or falling edge of the input signal has a delay, and the delay time can be determined by the resistance value of the external resistance, so as to generate adjustable dead zone or overlap time. The scheme uses the peripheral devices of the chip to generate adjustable dead zone or overlap time, and has stronger applicability.

[0005] The technical scheme of the application is: an adjustable dead zone or overlap time generation circuit, which comprises an adjustable current generation circuit, a delay circuit and a comparator. The adjustable current generation circuit provides adjustable charging and discharging current for the delay circuit to determine the delay time, and the comparator shapes the signal passing through the delay circuit into a square wave signal; specifically:

[0006] The adjustable current generating circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor RST, a first capacitor C1, a second capacitor C2, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, an operational amplifier, a first current source I1, a second current source I2, a third current source I3, a fourth current source I4, or a NOR gate NOR; a power supply voltage is defined as VDD, a positive input terminal of the operational amplifier is connected to VDD / 2, a negative input terminal of the operational amplifier is connected to a source electrode of the second NMOS tube MN2, a source electrode of the third PMOS tube MP3, one end of the third resistor R3, a drain electrode of the sixth PMOS tube MP6 and a drain electrode of the fifth NMOS tube MN5, and an output terminal of the operational amplifier is connected to a gate electrode and a drain electrode of the first PMOS tube MP1 and a gate electrode and a drain electrode of the first NMOS tube MN1; a source electrode of the first PMOS tube MP1 is connected to an output terminal of the first current source and a gate electrode of the second NMOS tube MN2, and an input terminal of the first current source is connected to VDD; a drain electrode of the first NMOS tube MN1 is connected to the drain electrode of the first PMOS tube MP1, a source electrode of the first NMOS tube MN1 is connected to an input terminal of the second current source and a gate electrode of the third PMOS tube MP3, and an output terminal of the second current source is connected to ground; a source electrode of the second PMOS tube MP2 is connected to VDD, a gate electrode of the second PMOS tube MP2 is connected to one end of the first capacitor, one end of the first resistor, a gate electrode of the seventh PMOS tube MP7, a gate electrode of the eighth PMOS tube MP8, a drain electrode of the second PMOS tube MP2 is connected to a drain electrode of the second NMOS tube MN2 and the other end of the first resistor, and the other end of the second capacitor C1 is connected to VDD; a drain electrode of the third PMOS tube MP3 is connected to one end of the second resistor R2 and a drain electrode of the third NMOS tube MN3; a gate electrode of the third NMOS tube MN3 is connected to the other end of the second resistor R2, one end of the second capacitor C2 and a gate electrode of the fourth NMOS tube MN4, a source electrode of the third NMOS tube MN3 is connected to ground, and the other end of the second capacitor C2 is connected to a gate electrode of the eighth NMOS tube MN8; a source electrode of the fourth PMOS tube MP4 is connected to VDD, the gate electrode and the drain electrode of the fourth PMOS tube MP4 are interconnected and connected to a gate electrode of the fifth PMOS tube MP5 and a drain electrode of the fourth NMOS tube MN4, a source electrode of the fourth NMOS tube MN4 is connected to ground; a source electrode of the fifth PMOS tube MP5 is connected to VDD, a drain electrode of the fifth PMOS tube MP5 is connected to a source electrode of the sixth PMOS tube MP6; a gate electrode of the sixth PMOS tube MP6 is connected to a gate electrode of the fifth NMOS tube MN5 and an output terminal of the NOR gate NOR, and a source electrode of the fifth NMOS tube MN5 is connected to a drain electrode of the sixth NMOS tube MN6.The gate of the sixth NMOS MN6 is connected with the gate and the drain of the seventh NMOS MN7, the drain of the seventh PMOS MP7, and the source of the sixth NMOS MN6 is connected with the ground; the source of the seventh PMOS MP7 is connected with the power supply, and the source of the seventh NMOS MN7 is connected with the ground; the source of the eighth PMOS MP8 is connected with the power supply, the drain of the eighth PMOS MP8 is connected with one input end of the NOR gate and the input end of the third current source I3, and the output end of the third current source I3 is connected with the ground; the input end of the fourth current source I4 is connected with VDD, the output end of the fourth current source I4 is connected with the other input end of the NOR gate and the drain of the eighth NMOS MN8, and the source of the eighth NMOS MN8 is connected with the ground; when the other end of the third resistance R3 is connected with one end of the fourth resistance RST and the other end of the fourth resistance RST is connected with the ground, the adjustable current generating circuit generates the dead time, and when the other end of the fourth resistance RST is connected with VDD, the adjustable current generating circuit generates the overlap time;

[0007] The delay circuit comprises a third capacitor C3, a fourth capacitor C4, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, and a fourth NAND gate NAND4. The source of the tenth PMOS transistor MP10 is connected to VDD, the gate of the tenth PMOS transistor MP10 is connected to the gate of the second PMOS transistor MP2 and the gate of the thirteenth PMOS transistor MP13. The source of the ninth PMOS transistor MP9 is connected to the drain of the tenth PMOS transistor MP10, the gate of the ninth PMOS transistor MP9 is connected to the output of the NOR gate, the gate of the twelfth PMOS transistor MP12, and the gate of the twelfth NMOS transistor MN12. The drain of the ninth NMOS transistor MN9 is connected to the drain of the ninth PMOS transistor MP9, one end of the third capacitor C3, the drain of the eleventh PMOS transistor MP11, the drain of the eleventh NMOS transistor MN11, and serves as the first output end of the delay circuit. The other end of the third capacitor C3 is connected to ground. The drain of the tenth NMOS transistor MN10 is connected to the source of the ninth NMOS transistor MN9, the gate of the tenth NMOS transistor MN10 is connected to the gate of the third NMOS transistor MN3 and the gate of the thirteenth NMOS transistor MN13, and the source of the tenth NMOS transistor MN10 is connected to ground. The source of the eleventh PMOS transistor MP11 is connected to VDD, the gate of the eleventh PMOS transistor MP11 is connected to the output of the first NAND gate NAND1, one input end of the first NAND gate NAND1 is connected to the output of the first inverter INV1, the other input end of the first NAND gate NAND1 is connected to the output of the NOR gate, and the input end of the first inverter INV1 is connected to an input signal. The gate of the eleventh NMOS transistor MN11 is connected to the output of the second inverter INV2, the input end of the second inverter INV2 is connected to the output of the second NAND gate NAND2, and the source of the eleventh NMOS transistor MN11 is connected to ground. One input end of the second NAND gate NAND2 is connected to the output of the third inverter INV3, the other input end of the second NAND gate NAND2 is connected to an input signal, and the input end of the third inverter is connected to the output of the NOR gate. The source of the thirteenth PMOS transistor MP13 is connected to VDD, and the drain of the thirteenth PMOS transistor MP13 is connected to the source of the twelfth PMOS transistor MP12.The drain of the twelfth NMOS transistor MN12 is connected to the drain of the twelfth PMOS transistor MP12, one input terminal of the fourth capacitor C4, the drain of the fourteenth PMOS transistor MP13, the drain of the fourteenth NMOS transistor MN14 and is the second output terminal of the delay circuit; the other terminal of the fourth capacitor C4 is connected to ground; the drain of the thirteenth NMOS transistor MN13 is connected to the source of the twelfth NMOS transistor MN12, and the source of the thirteenth NMOS transistor MN13 is connected to ground; the source of the fourteenth PMOS transistor MP14 is connected to VDD, and its gate is connected to the output terminal of the third NAND gate NAND3; one input terminal of the third NAND gate NAND3 is connected to the output terminal of the fourth inverter INV4, and the other input terminal of the third NAND gate NAND3 is connected to the output terminal of the NOR gate; the input terminal of the fourth inverter INV4 is connected to the inverted signal of the input signal; the source of the fourteenth NMOS transistor MN14 is connected to ground, and its gate is connected to the output terminal of the fifth inverter INV5; the input terminal of the fifth inverter INV5 is connected to the output terminal of the fourth NAND gate NAND4; one input terminal of the fourth NAND gate NAND4 is connected to the output terminal of the sixth inverter INV6, and the other input terminal of the fourth NAND gate NAND4 is connected to the inverted signal of the input signal; the input terminal of the sixth inverter INV6 is connected to the output terminal of the NOR gate.

[0008] The comparator comprises a fifth current source I5, a sixth current source I6, a seventh current source I7, an eighth current source I8, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a fifteenth NMOS transistor MN15, a sixteenth NMOS transistor MN16, a seventeenth NMOS transistor MN17, an eighteenth NMOS transistor MN18, a nineteenth NMOS transistor MN19, a twentieth NMOS transistor MN20, a seventh inverter INV7, an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, a twelfth inverter INV12, a thirteenth inverter INV13, and a fourteenth inverter INV14. An input end of the fifth current source I5 is connected to VDD, and an output end of the fifth current source I5 is connected to a source electrode of the fifteenth PMOS transistor MP15 and a source electrode of the sixteenth PMOS transistor MP16. A gate electrode of the fifteenth PMOS transistor MP15 is connected to a first output end of the delay circuit, and a drain electrode of the fifteenth PMOS transistor MP15 is connected to a drain electrode and a gate electrode of the fifteenth NMOS transistor MN15 and a gate electrode of the sixteenth NMOS transistor MN16. Source electrodes of the fifteenth NMOS transistor MN15 and the sixteenth NMOS transistor MN16 are connected to ground. A gate electrode of the sixteenth PMOS transistor MP16 is connected to VDD / 2, and a drain electrode of the sixteenth PMOS transistor MP16 is connected to a drain electrode of the sixteenth NMOS transistor MN16 and a gate electrode of the seventeenth NMOS transistor MN17. A source electrode of the seventeenth NMOS transistor MN17 is connected to ground. An input end of the sixth current source I6 is connected to VDD, and an output end of the sixth current source I6 is connected to an input end of the seventh inverter INV7 and a drain electrode of the seventeenth NMOS transistor MN17. The seventh inverter INV7, the eighth inverter INV8, the ninth inverter INV9, and the tenth inverter INV10 are sequentially connected in cascade to form a first inverter chain. An output end of the first inverter chain outputs an output signal. An input end of the seventh current source I7 is connected to VDD, and an output end of the seventh current source I7 is connected to a source electrode of the seventeenth PMOS transistor MP17 and a source electrode of the eighteenth PMOS transistor MP18. A gate electrode of the seventeenth PMOS transistor MP17 is connected to a second output end of the delay circuit, and a drain electrode of the seventeenth PMOS transistor MP17 is connected to a drain electrode and a gate electrode of the eighteenth NMOS transistor MN18 and a gate electrode of the nineteenth NMOS transistor MN19. Source electrodes of the eighteenth NMOS transistor MN18 and the nineteenth NMOS transistor MN19 are connected to ground. A gate electrode of the eighteenth PMOS transistor MP18 is connected to VDD / 2, and a drain electrode of the eighteenth PMOS transistor MP18 is connected to a drain electrode of the nineteenth NMOS transistor MN19 and a gate electrode of the twentieth NMOS transistor MN20. A source electrode of the twentieth NMOS transistor MN20 is connected to ground. An input end of the eighth current source I8 is connected to VDD, and an output end of the eighth current source I8 is connected to an input end of the eleventh inverter INV11 and a drain electrode of the twentieth NMOS transistor MN20. The eleventh inverter INV11, the twelfth inverter INV12, the thirteenth inverter INV13, and the fourteenth inverter INV14 are sequentially connected in cascade to form a second inverter chain. An output end of the second inverter chain outputs an inverted signal of the output signal.

[0009] The advantages of this invention are: under fixed dead time or overlap time, switching power supplies may have low efficiency or the power transistors may be at risk of shoot-through under certain application conditions. By adjusting the dead time or overlap time using an external resistor, the efficiency of the switching power supply can be maximized under all application conditions. Furthermore, this invention implements structure reuse and current self-compensation technology, thereby improving circuit utilization and implementation accuracy. Attached Figure Description

[0010] Figure 1 The present invention provides a specific circuit diagram of an adjustable dead time or overlap time generation circuit.

[0011] Figure 2 The present invention provides a key waveform of an adjustable dead time or overlap time generation circuit.

[0012] Note: Transistors whose names begin with MP are PMOS (P-Metal-Oxide-Semiconductor) transistors; transistors whose names begin with MN are NMOS (N-Metal-Oxide-Semiconductor) transistors; devices whose names begin with R are resistors; devices whose names begin with C are capacitors; devices whose names begin with I are current sources; devices whose names begin with INV are inverters; and devices whose names begin with NAND are NAND gates. Detailed Implementation

[0013] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0014] The specific structural diagram of the adjustable dead time or overlap time generation circuit proposed in this invention is as follows: Figure 1 As shown. It consists of three parts: an adjustable current generation circuit, a delay circuit, and a comparator. Terminal R is connected to V. DD This can generate dead time; when R is connected to ground, it can generate overlap time. The specific adjustable current generation circuit includes: resistors R1, R2, R3, RST; capacitors C1, C2; PMOS transistors MP1-MP8; NMOS transistors MN1-MN8; operational amplifier AMP; current sources I1, I2, I3, I4; and NOR gate. The specific connection relationship is: the negative input terminal of the operational amplifier is connected to V... DDThe source of MN2 and MP3 is connected to the positive input end, and the drain of MN5 and MP6 is connected to the drain of MN2 and MP3. The gate and drain of MN1 and MP1 are connected to the output end. The source of MP1 is connected to the current source I1 and the gate of MN2, and the source of MN1 is connected to the current source I2 and the gate of MP3. The drain of MN2 is connected to the drain of MP2. The drain of MP3 is connected to the drain of MN3. The gate of MP2 is connected to the gate of MP7 and MP8. The source of MP2, MP7 and MP8 is connected to the power supply voltage VDD. The drain of MP7 is connected to the drain of MN7 with shorted gate and drain. The drain of MP8 is connected to the current source I3. The gate of MN3 is connected to the gate of MN4 and MN8. The source of MN3, MN4 and MN8 is connected to the ground. The drain of MN4 is connected to the drain of MP4 with shorted gate and drain. The drain of MN8 is connected to the current source I4. The gate of MN7 is connected to the gate of MN6. The source of MN6 and MN7 is connected to the ground. The drain of MN6 is connected to the source of MN5. The gate of MP4 is connected to the gate of MP5. The source of MP4 and MP5 is connected to the power supply VDD. The drain of MP5 is connected to the source of MP6. MP6 is connected to the drain of MN5 and the gate of MN5. The two inputs of the NOR gate are connected to the drain of MP8 and the drain of MN8 respectively, and the output is connected to the gate of MP6. The two ends of resistor R1 are connected to the gate and drain of MP2 respectively. The two ends of resistor R2 are connected to the gate and drain of MN3 respectively. One end of resistor R3 is connected to the source of MN2, and the other end is connected to one end of external resistor RST. The other end of external resistor RST is connected to the power supply VDD or the ground GND. The upper plate of capacitor C1 is connected to the power supply voltage VDD, and the lower plate is connected to the gate of MP2. The upper plate of capacitor C2 is connected to the gate of MP2, and the lower plate is connected to the ground.The specific connection relationship is: the drain of MP9, MN9, MP11 and MN11 are connected together, and the gate of MN9 and MP9 are connected together; the source of MP9 is connected with the drain of MP10, the source of MP10 is connected with the power voltage VDD, and the gate of MP10 is connected with the gate of MP2; the source of MN9 is connected with the drain of MN10, the source of MN10 is connected with the ground, and the gate of MN10 is connected with the gate of MN3; the source of MP11 is connected with the power voltage VDD, the gate of MP11 is connected with the output of NAND1, the two input ends of NAND1 are connected with the gate of MP6 and the output of INV1 respectively, and the input end of INV1 is connected with the input signal IN; the source of MN11 is connected with the ground, the gate of MN11 is connected with the output end of INV2, the input end of INV2 is connected with the output of NAND2, the two input ends of NAND2 are connected with the input signal IN and the output end of INV3 respectively, and the input end of INV3 is connected with the gate of MP6; the drain of MP12, MN12, MP13 and MN13 are connected together, and the gate of MN12 and MP12 are connected together; the source of MP12 is connected with the drain of MP13, the source of MP13 is connected with the power voltage VDD, and the gate of MP13 is connected with the gate of MP2; the source of MN12 is connected with the drain of MN13, the source of MN13 is connected with the ground, and the gate of MN13 is connected with the gate of MN3; the source of MP14 is connected with the power voltage VDD, the gate of MP14 is connected with the output of NAND3, the two input ends of NAND3 are connected with the gate of MP6 and the output end of INV4 respectively, and the input end of INV4 is connected with the inverse signal IN_inv of the input signal; the source of MN14 is connected with the ground, the gate of MN14 is connected with the output end of INV5, the input end of INV5 is connected with the output of NAND4, the two input ends of NAND4 are connected with the inverse signal IN_inv of the input signal and the output end of INV6 respectively, and the input end of INV6 is connected with the gate of MP6. The comparator comprises: current sources I5-I8, PMOS tubes MP15-MP18, NMOS tubes MN15-MN20 and inverters INV7-INV14.The specific connection relationship is: current source I5 is connected with source electrodes of MP15 and MP16; gate electrode of MP15 is connected with drain electrode of MN9; gate electrode of MP16 is connected with VDD / 2; gate-drain of MN15 is short-circuited and connected with gate electrode of MN16 and drain electrode of MP15, source electrodes of MN15, MN16 and MN17 are connected with ground potential, drain electrode of MP16 and drain electrode of MN16 are connected with gate-drain of MN17, drain electrode of MN17 is connected with input end of the inverter chain composed of current source I5 and INV7-INV10; output end of the inverter chain is output signal OUT; current source I7 is connected with source electrodes of MP17 and MP18; gate electrode of MP17 is connected with drain electrode of MN12; gate electrode of MP18 is connected with VDD / 2; gate-drain of MN18 is short-circuited and connected with gate electrode of MN19 and drain electrode of MP17, source electrodes of MN18, MN19 and MN20 are connected with ground potential, drain electrode of MP18 and drain electrode of MN19 are connected with gate-drain of MN20, drain electrode of MN20 is connected with input end of the inverter chain composed of current source I8 and INV11-INV14; output end of the inverter chain is inverse signal of output signal OUT_inv.

[0015] Taking the dead time as an example, the adjustable current generating circuit generates different currents of different sizes through different resistance values of the external resistance, and the delay time of the rising edge of the input signal and the inverse signal thereof is determined in combination with the size of the capacitor in the delay circuit. In the adjustable current generating circuit, the sizes of the current sources I1-I4 are equal. The negative feedback structure clamps the negative input end of the operational amplifier at V DD / 2, and thus the current flowing through MN3 is

[0016]

[0017] The current of MP2 is determined by the translinear loop composed of I1, I2, MP1-MP3 and MN1-MN3. Meanwhile, the resistance value of RST is limited to 10KΩ-100KΩ to ensure that the drain current of MP8 is less than I3 and the drain current of MN8 is greater than I4. Thus, the current comparator composed of MP8 and I3 and MN8 and I4 makes the S signal 1, and MN5 is opened to self-compensate the current flowing through MP2.

[0018] In the delay circuit, the device sizes of the two circuits are completely the same. Since the S signal is 1, MN9 is turned on, MP9 and MN11 are turned off, and the gate signal of MP11 is the input signal IN. Thus, the charging current of C3 is a digital signal controlled large current, and the discharging current of C3 is the drain current of MN3. That is, the rising edge slope of D1 signal is considered to be infinite, and the falling edge slope of D1 signal is considered to be V DDVDD / 2·C3·(RST+R3). Similarly, MN12 is on, MP12 and MN14 are off, and the gate signal of MP14 is the inverse signal IN_inv of the input signal. The rising edge of the D2 signal has an infinite slope, and the falling edge of the D2 signal has a slope of V DD VDD / 2·C4·(RST+R3).

[0019] The turning point of the comparator circuit is set to VDD / 2, so for the input signal IN and its inverse signal IN_inv, the time of the rising edge delay, i.e. the dead time, is

[0020] T=C3·RST+λ1

[0021] where the constant term λ is related to R3 and the time of the output signal of the comparator turning high.

[0022] The principle of generating the overlap time is similar to that of generating the dead time. The fast charging and slow discharging of the capacitors C3 (C4) cause the falling edge delay of the signal, and the overlap time can be expressed as

[0023] T=C3·RST+λ2

[0024] where the constant term λ is related to R3 and the time of the output signal of the comparator turning high.

[0025] The key waveforms of the adjustable dead time or overlap time generating circuit proposed by the present application are shown in Figure 2 .

[0026] As can be seen from Figure 2 , when R is connected to VDD, the rising edges of the input signal IN and its inverse signal IN_inv are delayed for a period of time by the fast charging and slow charging of C3 and C4 with a large current, and the dead time is generated. Similarly, when R is connected to GND, the falling edges of the input signal IN and its inverse signal IN_inv are delayed for a period of time by the slow charging and fast charging of C3 and C4 with a specific current, and the overlap time is generated. The dead time or overlap time can be adjusted by the external resistance RST, and has good applicability.

[0027] The key point of the present application is to adjust the size and direction of the current by using the external resistance, to delay the rising edge or falling edge of the input signal, and to generate the dead time or overlap time.

[0028] Those skilled in the art can make various other specific modifications and combinations of the present application without departing from the spirit of the present application, and these modifications and combinations are still within the protection scope of the present application.

Claims

1. An adjustable dead-band or overlap time generation circuit, characterized by, The adjustable current generating circuit, the delay circuit and the comparator are included, wherein the adjustable current generating circuit is used for generating a dead time or an overlap time, the adjustable charging and discharging current of the delay circuit is provided to determine the delay time, and the comparator shapes the signal passing through the delay circuit into a square wave signal, specifically: The adjustable current generating circuit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor RST, a first capacitor C1, a second capacitor C2, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a seventh PMOS tube MP7, an eighth PMOS tube MP8, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a fifth NMOS tube MN5, a sixth NMOS tube MN6, a seventh NMOS tube MN7, an eighth NMOS tube MN8, an operational amplifier, a first current source I1, a second current source I2, a third current source I3, a fourth current source I4, or a NOR gate NOR; a power supply voltage is defined as VDD, a positive input terminal of the operational amplifier is connected to VDD / 2, a negative input terminal of the operational amplifier is connected to a source electrode of the second NMOS tube MN2, a source electrode of the third PMOS tube MP3, one end of the third resistor R3, a drain electrode of the sixth PMOS tube MP6 and a drain electrode of the fifth NMOS tube MN5, and an output terminal of the operational amplifier is connected to a gate electrode and a drain electrode of the first PMOS tube MP1 and a gate electrode and a drain electrode of the first NMOS tube MN1; a source electrode of the first PMOS tube MP1 is connected to an output terminal of the first current source and a gate electrode of the second NMOS tube MN2, and an input terminal of the first current source is connected to VDD; a drain electrode of the first NMOS tube MN1 is connected to the drain electrode of the first PMOS tube MP1, a source electrode of the first NMOS tube MN1 is connected to an input terminal of the second current source and a gate electrode of the third PMOS tube MP3, and an output terminal of the second current source is connected to ground; a source electrode of the second PMOS tube MP2 is connected to VDD, a gate electrode of the second PMOS tube MP2 is connected to one end of the first capacitor, one end of the first resistor, a gate electrode of the seventh PMOS tube MP7, a gate electrode of the eighth PMOS tube MP8, a drain electrode of the second PMOS tube MP2 is connected to a drain electrode of the second NMOS tube MN2 and the other end of the first resistor, and the other end of the second capacitor C1 is connected to VDD; a drain electrode of the third PMOS tube MP3 is connected to one end of the second resistor R2 and a drain electrode of the third NMOS tube MN3; a gate electrode of the third NMOS tube MN3 is connected to the other end of the second resistor R2, one end of the second capacitor C2 and a gate electrode of the fourth NMOS tube MN4, a source electrode of the third NMOS tube MN3 is connected to ground, and the other end of the second capacitor C2 is connected to a gate electrode of the eighth NMOS tube MN8; a source electrode of the fourth PMOS tube MP4 is connected to VDD, the gate electrode and the drain electrode of the fourth PMOS tube MP4 are interconnected and connected to a gate electrode of the fifth PMOS tube MP5 and a drain electrode of the fourth NMOS tube MN4, a source electrode of the fourth NMOS tube MN4 is connected to ground; a source electrode of the fifth PMOS tube MP5 is connected to VDD, a drain electrode of the fifth PMOS tube MP5 is connected to a source electrode of the sixth PMOS tube MP6; a gate electrode of the sixth PMOS tube MP6 is connected to a gate electrode of the fifth NMOS tube MN5 and an output terminal of the NOR gate NOR, and a source electrode of the fifth NMOS tube MN5 is connected to a drain electrode of the sixth NMOS tube MN6.The gate of the sixth NMOS transistor MN6 is connected with the gate and the drain of the seventh NMOS transistor MN7, the drain of the seventh PMOS transistor MP7, and the source of the sixth NMOS transistor MN6 is connected with the ground; the source of the seventh PMOS transistor MP7 is connected with the power supply, and the source of the seventh NMOS transistor MN7 is connected with the ground; the source of the eighth PMOS transistor MP8 is connected with the power supply, the drain of the eighth PMOS transistor MP8 is connected with one input end of the NOR gate and the input end of the third current source I3, the output end of the third current source I3 is connected with the ground; the input end of the fourth current source I4 is connected with VDD, the output end of the fourth current source I4 is connected with the other input end of the NOR gate and the drain of the eighth NMOS transistor MN8, and the source of the eighth NMOS transistor MN8 is connected with the ground; when the other end of the third resistor R3 is connected with one end of the fourth resistor RST and the other end of the fourth resistor RST is connected with the ground, the adjustable current generating circuit generates the dead time, and when the other end of the fourth resistor RST is connected with VDD, the adjustable current generating circuit generates the overlap time; The delay circuit comprises a third capacitor C3, a fourth capacitor C4, a ninth PMOS transistor MP9, a tenth PMOS transistor MP10, an eleventh PMOS transistor MP11, a twelfth PMOS transistor MP12, a thirteenth PMOS transistor MP13, a fourteenth PMOS transistor MP14, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a sixth inverter INV6, a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, and a fourth NAND gate NAND4. The source of the tenth PMOS transistor MP10 is connected to VDD, the gate of the tenth PMOS transistor MP10 is connected to the gate of the second PMOS transistor MP2 and the gate of the thirteenth PMOS transistor MP13. The source of the ninth PMOS transistor MP9 is connected to the drain of the tenth PMOS transistor MP10, the gate of the ninth PMOS transistor MP9 is connected to the output of the NOR gate, the gate of the twelfth PMOS transistor MP12, and the gate of the twelfth NMOS transistor MN12. The drain of the ninth NMOS transistor MN9 is connected to the drain of the ninth PMOS transistor MP9, one end of the third capacitor C3, the drain of the eleventh PMOS transistor MP11, the drain of the eleventh NMOS transistor MN11, and serves as the first output end of the delay circuit. The other end of the third capacitor C3 is connected to ground. The drain of the tenth NMOS transistor MN10 is connected to the source of the ninth NMOS transistor MN9, the gate of the tenth NMOS transistor MN10 is connected to the gate of the third NMOS transistor MN3 and the gate of the thirteenth NMOS transistor MN13, and the source of the tenth NMOS transistor MN10 is connected to ground. The source of the eleventh PMOS transistor MP11 is connected to VDD, the gate of the eleventh PMOS transistor MP11 is connected to the output of the first NAND gate NAND1, one input end of the first NAND gate NAND1 is connected to the output of the first inverter INV1, the other input end of the first NAND gate NAND1 is connected to the output of the NOR gate, and the input end of the first inverter INV1 is connected to an input signal. The gate of the eleventh NMOS transistor MN11 is connected to the output of the second inverter INV2, the input end of the second inverter INV2 is connected to the output of the second NAND gate NAND2, and the source of the eleventh NMOS transistor MN11 is connected to ground. One input end of the second NAND gate NAND2 is connected to the output of the third inverter INV3, the other input end of the second NAND gate NAND2 is connected to an input signal, and the input end of the third inverter is connected to the output of the NOR gate. The source of the thirteenth PMOS transistor MP13 is connected to VDD, and the drain of the thirteenth PMOS transistor MP13 is connected to the source of the twelfth PMOS transistor MP12.The drain of the twelfth NMOS transistor MN12 is connected to the drain of the twelfth PMOS transistor MP12, one input terminal of the fourth capacitor C4, the drain of the fourteenth PMOS transistor MP13, the drain of the fourteenth NMOS transistor MN14 and is the second output terminal of the delay circuit; the other terminal of the fourth capacitor C4 is connected to the ground; the drain of the thirteenth NMOS transistor MN13 is connected to the source of the twelfth NMOS transistor MN12, and the source of the thirteenth NMOS transistor MN13 is connected to the ground; the source of the fourteenth PMOS transistor MP14 is connected to VDD, and its gate is connected to the output terminal of the third NAND gate NAND3; one input terminal of the third NAND gate NAND3 is connected to the output terminal of the fourth inverter INV4, and the other input terminal of the third NAND gate NAND3 is connected to the output terminal of the NOR gate; the input terminal of the fourth inverter INV4 is connected to the inverted signal of the input signal; the source of the fourteenth NMOS transistor MN14 is connected to the ground, and its gate is connected to the output terminal of the fifth inverter INV5; the input terminal of the fifth inverter INV5 is connected to the output terminal of the fourth NAND gate NAND4; one input terminal of the fourth NAND gate NAND4 is connected to the output terminal of the sixth inverter INV6, and the other input terminal of the fourth NAND gate NAND4 is connected to the inverted signal of the input signal; the input terminal of the sixth inverter INV6 is connected to the output terminal of the NOR gate. The comparator comprises a fifth current source I5, a sixth current source I6, a seventh current source I7, an eighth current source I8, a fifteenth PMOS transistor MP15, a sixteenth PMOS transistor MP16, a seventeenth PMOS transistor MP17, an eighteenth PMOS transistor MP18, a fifteenth NMOS transistor MN15, a sixteenth NMOS transistor MN16, a seventeenth NMOS transistor MN17, an eighteenth NMOS transistor MN18, a nineteenth NMOS transistor MN19, a twentieth NMOS transistor MN20, a seventh inverter INV7, an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, a twelfth inverter INV12, a thirteenth inverter INV13, and a fourteenth inverter INV14; an input end of the fifth current source I5 is connected with VDD, and output ends of the fifth current source I5 are connected with sources of the fifteenth PMOS transistor MP15 and the sixteenth PMOS transistor MP16; a gate of the fifteenth PMOS transistor MP15 is connected with a first output end of the delay circuit, a drain of the fifteenth PMOS transistor MP15 is connected with a drain and a gate of the fifteenth NMOS transistor MN15 and a gate of the sixteenth NMOS transistor MN16, and sources of the fifteenth NMOS transistor MN15 and the sixteenth NMOS transistor MN16 are connected with the ground; a gate of the sixteenth PMOS transistor MP16 is connected with VDD / 2, and a drain of the sixteenth PMOS transistor MP16 is connected with a drain of the sixteenth NMOS transistor MN16 and a gate of the seventeenth NMOS transistor MN17, and a source of the seventeenth NMOS transistor MN17 is connected with the ground; an input end of the sixth current source I6 is connected with VDD, and an output end of the sixth current source I6 is connected with an input end of the seventh inverter INV7 and a drain of the seventeenth NMOS transistor MN17; the seventh inverter INV7, the eighth inverter INV8, the ninth inverter INV9, and the tenth inverter INV10 are sequentially connected in cascade to form a first inverter chain, and an output end of the first inverter chain outputs an output signal; an input end of the seventh current source I7 is connected with VDD, and output ends of the seventh current source I7 are connected with sources of the seventeenth PMOS transistor MP17 and the eighteenth PMOS transistor MP18; a gate of the seventeenth PMOS transistor MP17 is connected with a second output end of the delay circuit, a drain of the seventeenth PMOS transistor MP17 is connected with a drain and a gate of the eighteenth NMOS transistor MN18 and a gate of the nineteenth NMOS transistor MN19, and sources of the eighteenth NMOS transistor MN18 and the nineteenth NMOS transistor MN19 are connected with the ground; a gate of the eighteenth PMOS transistor MP18 is connected with VDD / 2, a drain of the eighteenth PMOS transistor MP18 is connected with a drain of the nineteenth NMOS transistor MN19 and a gate of the twentieth NMOS transistor MN20, and a source of the twentieth NMOS transistor MN20 is connected with the ground; an input end of the eighth current source I8 is connected with VDD, and an output end of the eighth current source I8 is connected with an input end of the eleventh inverter INV11 and a drain of the twentieth NMOS transistor MN20; the eleventh inverter INV11, the twelfth inverter INV12, the thirteenth inverter INV13, and the fourteenth inverter INV14 are sequentially connected in cascade to form a second inverter chain, and an output end of the second inverter chain outputs an inverted signal of the output signal.

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