Chip failure type test system

Abstract

The application provides a chip failure type test system, comprising: a detection device configured to output a detection signal to a chip under test; a processing device in communication with the detection device and in electrical communication with the chip under test, the processing device configured to control at least a test frequency and a test power of the detection signal to test the chip under test, and determine whether the chip under test fails and determine a failure type in the case of failure according to an output signal of the chip under test during the test. The system connects the processing device with the detection device, controls at least the test frequency and the test power of the detection signal by the processing device to test the chip under test, and determines whether the chip under test fails and determines a failure type in the case of failure according to an output signal of the chip under test during the test, realizes automatic control of chip testing, and further solves the problem that chip failure types cannot be automatically identified and distinguished in the prior art.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a chip failure type testing system. Background Technology

[0002] The electromagnetic compatibility (EMC) immunity testing method for integrated circuits based on direct radio frequency (RF) power injection has been developed into a standard (IEC 62132-4) (International Electrotechnical Commission). The IEC 62132-4 standard is primarily used for EMC immunity testing of integrated circuits from 150 kHz to 1 GHz (extendable to higher frequencies). EMC immunity testing for integrated circuits is divided into two methods: radiated immunity and conducted immunity. The direct RF power injection method is a commonly used conducted immunity testing method.

[0003] Integrated circuit RF (Radio Frequency) DPI (Direct Power Injection) immunity test methods are as follows: Figure 1 As shown, failure criteria are derived based on the functionality of the DUT (Device Under Test). RF electromagnetic interference is injected at the RF injection point of the chip's pin under test. The signals related to the test are observed using an oscilloscope or other DUT monitoring equipment, and the forward injection power is used to characterize the electromagnetic immunity level. The test standard also provides a test flowchart for this method, as shown below. Figure 2 As shown, the general description is as follows: Start the test, set the initial frequency f = f start Set the initial injection power value (this power value is determined by the specified maximum power value P). specified The process involves: determining the power level and dividing it into several gradient power values ​​(incrementing from small to large); starting power injection and waiting for the injected power residence time to end; determining whether the DUT has failed or reached the specified power level; if not, continuing to increase the injected power value P; if so, stopping injection and recording the current frequency point and power value; and determining whether the current frequency point is the termination frequency point f. stop If not, proceed to the next frequency point and continue the above steps; if yes, end the test.

[0004] The purpose of the entire testing process is to determine whether the injected power at each specified test frequency point can reach the specified power value or the injected power value before failure occurs.

[0005] However, this test system offers an optional control computer, without specifying whether the test is implemented manually, semi-automatically, or automatically. This means that the RF signal source, RF amplifier, directional coupler, RF power meter, and DUT monitoring equipment may all require manual control. Furthermore, due to the power step setting, there is a possibility that the DUT may fail and fail to return to normal operation before the next test frequency. In such cases, the test must be paused, the DC power supply or excitation source manually reset, and then the test can be restarted. Even testing a single pin is a time-consuming process; manual intervention significantly increases test time and reduces efficiency. Moreover, this test system cannot automatically identify and differentiate failure types caused by injected interference (the IEC 62132-1 standard classifies failures into categories A, B, C, D, and E, as described in Table 1 below).

[0006] Table 1 Definition of Failure Types in Immunity Tests

[0007]

[0008]

[0009] Therefore, there is an urgent need for a chip testing system that can automatically identify and distinguish chip failure types.

[0010] The information disclosed above in the background section is only intended to enhance the understanding of the background art of the art described herein. Therefore, the background art may contain certain information that does not constitute prior art known to those skilled in the art in this country. Summary of the Invention

[0011] The main purpose of this application is to provide a chip failure type testing system to solve the problem that the existing technology cannot automatically identify and distinguish chip failure types.

[0012] To achieve the above objectives, according to one aspect of this application, a chip failure type testing system is provided, comprising a detection device and a processing device, wherein the detection device is used to output a detection signal to a chip under test; the processing device is communicatively connected to the detection device and electrically connected to the chip under test, and the processing device is used to at least control the test frequency and test power of the detection signal to test the chip under test, and determine whether the chip under test has failed based on the output signal of the chip under test during the test process, and, if it has failed, determine the failure type.

[0013] Furthermore, the system also includes a power supply device, which includes a first DC power supply and a second DC power supply. The first DC power supply and the second DC power supply are respectively communicatively connected to the processing device and electrically connected to the chip under test. The first DC power supply is used to supply power to the chip under test, and the second DC power supply is used to control the chip under test to reset.

[0014] Furthermore, the processing device includes a processor and a monitoring device, wherein the processor is used to control at least the test frequency and the test power of the detection signal to perform the test on the chip under test, and to determine the failure type in the event of failure; the monitoring device is communicatively connected to the processor and is used to determine whether the chip under test has failed based on the output signal of the chip under test during the test process.

[0015] Further, the processing device is used to control at least the test frequency and test power of the detection signal to test the chip under test, and to determine whether the chip under test has failed and, if it has failed, to determine the failure type based on the output signal of the chip under test during the test process, including: acquiring a frequency range and a power range, wherein the frequency range and the power range are determined based on the chip under test; sequentially performing at least one set of tests on the chip under test, wherein the test frequency is the same in one set of tests, and, if there are multiple sets of tests, the test frequencies of any two sets of tests are different, and, in one set of tests, the test power of multiple tests is multiple powers in the power range from small to large; if it is determined that the chip under test has failed, controlling the detection device to stop inputting the detection signal to the chip under test, and determining the failure type based on the output signal of the chip under test after a predetermined action and a predetermined time.

[0016] Further, the processing device is used to at least control the test frequency and test power of the detection signal to test the chip under test, and to determine whether the chip under test has failed and, if it has failed, to determine the failure type based on the output signal of the chip under test during the test process. The device further includes: a first determining step, in which, if the chip under test is determined not to have failed, determining whether the maximum value of the test power in the current group of tests is less than a power threshold; a first controlling step, in which, if the maximum value of the test power is less than the power threshold, controlling the test power to increase by a first predetermined step to test the chip under test, and determining whether the chip under test has failed based on the output signal of the chip under test; a second determining step, in which, if the chip under test has failed, controlling the detection device to stop inputting the detection signal to the chip under test, and determining the failure type based on the predetermined action and the output signal of the chip under test after the predetermined time; and, in which, if the chip under test is not failed, repeating the first controlling step until the test power reaches the power threshold.

[0017] Further, the processing device is used to control at least the test frequency and test power of the detection signal to test the chip under test, and to determine whether the chip under test has failed and, if it has failed, to determine the failure type based on the output signal of the chip under test during the test process. The device further includes: a third determining step, in which, if the failure type is determined, determining whether the maximum value of the test frequency in the current group of tests is less than a frequency threshold; a second controlling step, in which, if the maximum value of the test frequency is less than the frequency threshold, controlling the test frequency to increase by a second predetermined step to perform at least one group of tests on the chip under test, wherein the test frequency in the group of tests is the same, and the test power in the group of tests is multiple powers in the power range from small to large, and determining whether the chip under test has failed based on the output signal of the chip under test; a fourth determining step, in which, if the chip under test fails, controlling the detection device to stop inputting the detection signal to the chip under test, and determining the failure type based on the predetermined action and the output signal of the chip under test after the predetermined time; repeating the second controlling step until the test frequency reaches the frequency threshold.

[0018] Further, determining the failure type based on the output signal of the chip under test after a predetermined action and a predetermined time includes: after a first predetermined action and a first predetermined time, the monitoring device acquires the output signal of the chip under test, wherein the first predetermined action is to control the monitoring device to reset; if the monitoring device determines that the chip under test is normal based on the output signal, the processor determines the failure type as a first failure type; if the monitoring device determines that the chip under test is abnormal based on the output signal, after a second predetermined action and a second predetermined time, the processor acquires the output signal of the chip under test and determines the failure type, wherein the second predetermined action is to control the chip under test to reset and control the monitoring device to reset.

[0019] Further, after the second predetermined action and the second predetermined time, acquiring the output signal of the chip under test and determining the failure type includes: after the second predetermined action and the second predetermined time, the monitoring device acquires the output signal of the chip under test; if the monitoring device determines that the chip under test is normal based on the output signal, the processor determines that the failure type is the second failure type; if the monitoring device determines that the chip under test is abnormal based on the output signal, after the third predetermined action and the third predetermined time, acquiring the output signal of the chip under test and determining the failure type, wherein the third predetermined action is to control the chip under test to power on again and control the monitoring device to reset.

[0020] Further, after the third predetermined action and the third predetermined time, acquiring the output signal of the chip under test and determining the failure type includes: after the third predetermined action and the third predetermined time, the monitoring device acquires the output signal of the chip under test; if the monitoring device determines that the chip under test is normal based on the output signal, the processor determines that the failure type is a third failure type; if the monitoring device determines that the chip under test is abnormal based on the output signal, the processor determines that the failure type is a fourth failure type.

[0021] Furthermore, the detection device includes a radio frequency (RF) signal source, an RF amplifier, and a power meter. The RF signal source is used to generate an RF interference signal. The RF amplifier is electrically connected to the RF signal source and is used to amplify the power of the RF interference signal and separate the amplified RF interference signal to obtain a forward power signal and a reflected power signal, wherein the forward power signal is the detection signal. The power meter is electrically connected to the RF amplifier and is used to measure the power of the forward power signal.

[0022] Furthermore, the system also includes a test board, which includes the detection signal injection point and a DC blocking capacitor. One end of the detection signal injection point is electrically connected to the detection device, one end of the DC blocking capacitor is electrically connected to the other end of the detection signal injection point, and the other end is electrically connected to the chip under test. The other end of the DC blocking capacitor is electrically connected to the chip under test through the DC blocking capacitor. The chip under test is located on the test board.

[0023] The chip failure type testing system, applying the technical solution of this application, includes a detection device and a processing device. The detection device outputs a detection signal to the chip under test (DUT). The processing device is communicatively connected to the detection device and electrically connected to the DUT. The processing device controls at least the test frequency and test power of the detection signal to test the DUT, and determines whether the DUT has failed and, if so, the failure type based on the output signal of the DUT during the testing process. This system connects the processing device to the detection device, controls at least the test frequency and test power of the detection signal to test the DUT, and determines whether the DUT has failed and, if so, the failure type based on the output signal of the DUT during the testing process. This achieves automated control of chip testing, thereby solving the problem in the prior art of not being able to automatically identify and distinguish chip failure types. Attached Figure Description

[0024] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0025] Figure 1 This illustrates a chip failure type testing system in the prior art;

[0026] Figure 2 This diagram illustrates a prior art chip failure type testing flowchart;

[0027] Figure 3 This application illustrates a typical embodiment of a chip failure type testing system;

[0028] Figure 4 This application illustrates a chip failure type testing system according to one embodiment;

[0029] Figure 5 A flowchart of a chip failure type test according to an embodiment of this application is shown.

[0030] The above figures include the following reference numerals:

[0031] 10. Detection device; 20. Processing device; 30. Chip under test; 40. Power supply device; 101. Radio frequency signal source; 102. Radio frequency amplifier; 103. Power meter; 201. Processor; 202. Monitoring device. Detailed Implementation

[0032] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0033] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0034] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be an intermediate element present. Furthermore, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element via a third element.

[0035] As described in the background section, existing technologies cannot automatically identify and distinguish chip failure types. To address this issue, this application proposes a chip failure type testing system.

[0036] In a typical embodiment of this application, a chip failure type testing system is provided, such as... Figure 3 As shown, the device includes a detection device 10 and a processing device 20. The detection device 10 is used to output a detection signal to the chip under test 30. The processing device 20 is communicatively connected to the detection device 10 and electrically connected to the chip under test 30. The processing device 20 is used to at least control the test frequency and test power of the detection signal to test the chip under test 30, and to determine whether the chip under test has failed based on the output signal of the chip under test during the test process, and to determine the failure type if the chip has failed.

[0037] The aforementioned chip failure type testing system includes a detection device and a processing device. The detection device outputs a detection signal to the chip under test (DUT). The processing device is communicatively connected to the detection device and electrically connected to the DUT. The processing device controls at least the test frequency and test power of the detection signal to test the DUT, and determines whether the DUT has failed and, if so, the failure type based on the output signal of the DUT during the test. This system connects the processing device to the detection device, controls at least the test frequency and test power of the detection signal to test the DUT, and determines whether the DUT has failed and, if so, the failure type based on the output signal of the DUT during the test. This achieves automated control of chip testing, thereby solving the problem of the inability to automatically identify and distinguish chip failure types in existing technologies.

[0038] In practical applications, the chip failure type testing system described above can be used in integrated circuit electromagnetic compatibility testing and analysis. RF electromagnetic interference is injected into the pins of the chip under test. That is, the processing device controls the test frequency and test power of the detection signal to test the chip under test. Based on the output signal of the chip under test during the test process, it is determined whether the chip under test has failed, and if so, the failure type is determined. The test power is the forward injection power, which is used to characterize the electromagnetic immunity level.

[0039] In one embodiment of this application, such as Figure 4 As shown, the system also includes a power supply device 40, which comprises a first DC power supply and a second DC power supply. The first and second DC power supplies are communicatively connected to the processing device and electrically connected to the chip under test (DUT). The first DC power supply powers the DUT, and the second DC power supply controls the DUT's reset. The power supply device is communicatively connected to the processing device, which can automatically control the first DC power supply to power and de-power the DUT, and control the second DC power supply to reset the DUT during chip testing. This eliminates the need for manual intervention during chip testing, significantly reducing testing time and improving testing efficiency.

[0040] Specifically, the processor can control the power supply voltage of the first DC power supply to the chip under test, and can also control the interval between switching the on / off state of the first DC power supply. The processor can provide the reset signal voltage value and duration to the chip under test through the second DC power supply.

[0041] In order to quickly obtain the output signal and accurately process it to determine the failure type of the chip under test, in another embodiment of this application, such as... Figure 4 As shown, the above-mentioned processing device includes a processor 201 and a monitoring device 202. The processor 201 is used to control at least the test frequency and the test power of the detection signal to perform the test on the chip under test 30, and to determine the failure type in the event of failure. The monitoring device 202 is communicatively connected to the processor 201 and is used to determine whether the chip under test has failed based on the output signal of the chip under test during the test process.

[0042] In practical applications, the aforementioned monitoring device can be a digital storage oscilloscope. Digital storage oscilloscopes have powerful real-time signal processing and analysis capabilities, and can store waveforms. The oscilloscope can observe the disturbance amplitude on the power supply pin of the chip under test package to obtain the interference amplitude of the internal power supply pad of the chip, monitor the output signal of the chip under test as a failure criterion, set the limit value of the output signal, and when the output signal of the chip under test exceeds the limit value, it is determined that the chip under test has failed and the result is fed back to the processor. The oscilloscope reset waiting time can also be set.

[0043] In another embodiment of this application, such as Figure 5 As shown, the processing device is used to control at least the test frequency and test power of the detection signal to test the chip under test, and to determine whether the chip under test has failed and, if it has failed, to determine the failure type based on the output signal of the chip under test during the test process. This includes: acquiring a frequency range and a power range, wherein the frequency range and the power range are determined based on the chip under test; sequentially performing at least one set of the tests on the chip under test, wherein the test frequency is the same in one set of tests, and if there are multiple sets of tests, the test frequencies of any two sets of tests are different, and the test power of multiple tests in one set of tests is a plurality of powers in the power range from small to large; and, if the chip under test is determined to have failed, controlling the detection device to stop inputting the detection signal to the chip under test, and determining the failure type based on the output signal of the chip under test after a predetermined action and a predetermined time. By testing the chip under test at different test frequencies with power levels ranging from low to high, it is possible to determine whether the chip under test can withstand the specified power value at each specified test frequency. It is also possible to determine the test power value before the chip under test failed. In addition, if the chip under test is determined to have failed, the detection device is controlled to stop inputting the detection signal to the chip under test. Based on the output signal of the chip under test after a predetermined action and a predetermined time, the failure type can be determined more quickly and accurately.

[0044] In order to determine whether the test power that the chip under test can withstand at various test frequencies can reach the power threshold, in another embodiment of this application, such as... Figure 5 As shown, the processing device described above is used to at least control the test frequency and test power of the detection signal to test the chip under test (DUT), and to determine whether the DUT has failed and, if it has failed, to determine the failure type based on the output signal of the DUT during the test process. The device further includes: a first determining step, in which, if the DUT is determined not to have failed, determining whether the maximum value of the test power in the current group of tests is less than a power threshold; a first controlling step, in which, if the maximum value of the test power is less than the power threshold, controlling the test power to increase by a first predetermined step to test the DUT, and determining whether the DUT has failed based on the output signal of the DUT; a second determining step, in which, if the DUT has failed, controlling the detection device to stop inputting the detection signal to the DUT, and determining the failure type based on the predetermined action and the output signal of the DUT after the predetermined time; and, in which, if the DUT has not failed, repeating the control step until the test power reaches the power threshold.

[0045] To determine whether the test power that the chip under test can withstand at the frequency threshold can reach the power threshold, in another embodiment of this application, such as... Figure 5 As shown, the processing device described above is used to control at least the test frequency and test power of the detection signal to test the chip under test, and to determine whether the chip under test has failed and, if it has failed, to determine the failure type based on the output signal of the chip under test during the test process. The device further includes: a third determining step, in which, if the failure type is determined, determining whether the maximum value of the test frequency in the current group of tests is less than a frequency threshold; a second controlling step, in which, if the maximum value of the test frequency is less than the frequency threshold, controlling the test frequency to increase by a second predetermined step to perform at least one group of tests on the chip under test, wherein the test frequency in the group of tests is the same, and the test power in the group of tests is multiple powers in the power range from small to large, and determining whether the chip under test has failed based on the output signal of the chip under test; a fourth determining step, in which, if the chip under test fails, controlling the detection device to stop inputting the detection signal to the chip under test, and determining the failure type based on the predetermined action and the output signal of the chip under test after the predetermined time; repeating the second controlling step until the test frequency reaches the frequency threshold.

[0046] In one specific embodiment of this application, the system is first initialized by setting a starting test frequency, a frequency threshold, and a frequency increment step to generate multiple test frequencies to be tested. The frequency increment step can be the second predetermined step. A starting test power, a power threshold, a power increment step, and a power dwell time are set. The power increment step can be the first predetermined step. The test frequency in the detection signal is set as the starting test frequency, and the test power is set as the starting test power. The detection device starts inputting the detection signal to the chip under test and tests the chip under test. After the power dwell time ends, the monitoring device acquires the output signal of the chip under test and determines whether the chip under test has failed.

[0047] In another embodiment of this application, such as Figure 5 As shown, the failure type is determined based on the output signal of the chip under test after a predetermined action and a predetermined time, including: after a first predetermined action and a first predetermined time, the monitoring device acquires the output signal of the chip under test, where the first predetermined action is to control the monitoring device to reset; if the monitoring device determines that the chip under test is normal based on the output signal, the processor determines the failure type as the first failure type; if the monitoring device determines that the chip under test is abnormal based on the output signal, after a second predetermined action and a second predetermined time, the output signal of the chip under test is acquired and the failure type is determined, where the second predetermined action is to control the chip under test to reset and control the monitoring device to reset. During the input of the detection signal, the chip's operation becomes abnormal, but after stopping the input of the detection signal to the chip under test and controlling the monitoring device to reset, the chip returns to its original normal state. At this time, the chip's failure type is the first failure type. If the chip cannot return to its original state, the failure type is further determined by acquiring the output signal of the chip under test after the second predetermined action and the second predetermined time.

[0048] In practical applications, after the detection device stops inputting the detection signal to the chip under test, it saves the monitoring screenshot of the current monitoring device, and then executes the first predetermined action to control the monitoring device to reset, that is, to clear the current status of the monitoring device. After waiting for a first predetermined time, the monitoring device obtains the output signal of the chip under test again and determines whether the chip under test is abnormal. The first predetermined time is the interval time for waiting for the monitoring device. If the chip under test is normal, the failure type is saved as the first failure type, and the current test frequency and test power are also saved.

[0049] To further determine the aforementioned failure type, in another embodiment of this application, such as Figure 5As shown, after a second predetermined action and a second predetermined time, the output signal of the chip under test (DUT) is acquired and the failure type is determined. This includes: after the second predetermined action and the second predetermined time, the monitoring device acquires the output signal of the DUT; if the monitoring device determines that the DUT is normal based on the output signal, the processor determines the failure type as the second failure type; if the monitoring device determines that the DUT is abnormal based on the output signal, after a third predetermined action and a third predetermined time, the output signal of the DUT is acquired and the failure type is determined. The third predetermined action is to control the DUT to power on again and to control the monitoring device to reset. Even after controlling the monitoring device to reset, the chip cannot return to its original normal state. However, after controlling the DUT to reset and the monitoring device to reset, the chip can return to its original normal state. In this case, the chip's failure type is the second failure type.

[0050] In practical applications, the monitoring device acquires a first predetermined action and a monitoring screenshot of the chip under test (DUT) after a first predetermined time. Then, a second predetermined action is executed to control the DUT to reset and the monitoring device to reset. Specifically, the DUT reset source is turned on once, waits for a predetermined time, and then turned off, causing the DUT to reset. After the reset source is turned off, the monitoring device is controlled to reset. After a second predetermined time, the monitoring device acquires the output signal of the DUT again to determine whether the DUT is abnormal. The second predetermined time is the interval for waiting for the monitoring device. If the DUT is normal, the failure type is saved as the second failure type, and the current test frequency and test power are also saved.

[0051] In another embodiment of this application, such as Figure 5 As shown, after a third predetermined action and a third predetermined time, the output signal of the chip under test (DUT) is acquired and the failure type is determined. This includes: after the third predetermined action and the third predetermined time, the monitoring device acquires the output signal of the DUT; if the monitoring device determines that the DUT is normal based on the output signal, the processor determines the failure type as a third failure type; if the monitoring device determines that the DUT is abnormal based on the output signal, the processor determines the failure type as a fourth failure type. If, after controlling the DUT to reset and the monitoring device to reset, the chip cannot return to its original normal state, but after controlling the DUT to power on again and controlling the monitoring device to reset, the chip can return to its normal state, then the chip's failure type is the third failure type. If the chip still cannot return to its original normal state, then the chip's failure type is the fourth failure type.

[0052] In practical applications, the monitoring screenshot of the chip under test (DUT) acquired by the monitoring device after the second predetermined action and the second predetermined time is saved. Then, the third predetermined action is executed to control the DUT to power on again and to control the monitoring device to reset. Specifically, the power supply is turned off, and after the power supply interval ends, the power supply is turned on again to power on the DUT. After the DUT is powered on again, the monitoring device is reset. After the third predetermined time, the monitoring device acquires the output signal of the DUT again to determine whether the DUT is abnormal. The third predetermined time is the interval for waiting for the monitoring device to complete. If the DUT is normal, the failure type is saved as the third failure type, and the current test frequency and test power are also saved. If the DUT is abnormal, the failure type is saved as the fourth failure type, and the current test frequency and test power are also saved. At this point, the DUT is completely damaged.

[0053] Since the output signal power of the radio frequency signal source is low, in order to obtain a higher power output signal, in another embodiment of this application, such as... Figure 4 As shown, the detection device includes a radio frequency signal source 101, a radio frequency amplifier 102, and a power meter 103. The radio frequency signal source 101 is used to generate a radio frequency interference signal. The radio frequency amplifier 102 is electrically connected to the radio frequency signal source 101 and is used to amplify the power of the radio frequency interference signal and separate the amplified radio frequency interference signal to obtain a forward power signal and a reflected power signal. The forward power signal is the detection signal. The power meter 103 is electrically connected to the radio frequency amplifier 102 and is used to measure the power of the forward power signal.

[0054] In practical applications, the aforementioned RF amplifier includes a built-in directional coupler, which can separate the amplified RF interference signal to obtain the forward power signal and the reflected power signal.

[0055] In another embodiment of this application, the system further includes a test board. The test board includes the detection signal injection point and a DC blocking capacitor. One end of the detection signal injection point is electrically connected to the detection device, and the other end is electrically connected to the chip under test (DUT) via the DC blocking capacitor. One end of the DC blocking capacitor is electrically connected to the other end of the detection signal injection point, and the other end is electrically connected to the DUT. The DUT is located on the test board. The test board can connect the detection device and processing device to the DUT for convenient testing.

[0056] To enable those skilled in the art to better understand the technical solution of this application, the technical solution of this application will be described in detail below with reference to specific embodiments and comparative examples.

[0057] Example

[0058] The chip failure type testing system in this embodiment, such as Figure 3 and Figure 4 As shown:

[0059] The device includes a detection device 10 and a processing device 20. The detection device 10 is used to output a detection signal to the chip under test 30. The processing device 20 is communicatively connected to the detection device 10 and electrically connected to the chip under test 30. The processing device 20 includes a processor 201 and a monitoring device 202.

[0060] The chip failure type testing process in this embodiment is as follows: Figure 5 As shown:

[0061] First, the system is initialized by setting the starting test frequency, frequency threshold, and frequency increment step to generate multiple test frequencies to be tested. The starting test power, power threshold, power increment step, and power dwell time are also set. The test frequency in the detection signal is set as the starting test frequency, and the test power is set as the starting test power. The detection device starts inputting the detection signal to the chip under test and tests the chip under test. After the power dwell time ends, the monitoring device acquires the output signal of the chip under test and determines whether the chip under test has failed.

[0062] If the chip under test is normal, the test power is increased by a first predetermined step, and the test process is repeated until the test power reaches the power threshold.

[0063] If the chip under test (DUT) malfunctions, the detection device stops inputting the detection signal to the DUT, saves the current monitoring screenshot, and then executes a first predetermined action: resetting the monitoring device (clearing its current state). After waiting for a first predetermined time, the monitoring device acquires the output signal of the DUT again to determine if the DUT is malfunctioning. The first predetermined time is the interval between waiting for the monitoring device to complete the process. If the DUT is normal, the failure type is saved as the first failure type, along with the current test frequency and test power. If the DUT malfunctions, the monitoring device saves the first predetermined action and the monitoring screenshot of the DUT after the first predetermined time, and then executes a second predetermined action: resetting the DUT and the monitoring device. Specifically, the reset source of the chip under test (DUT) is turned on once, and after a predetermined time, the reset source is turned off to reset the DUT. Then, after the reset source is turned off, the monitoring device is reset. After a second predetermined time, the monitoring device again acquires the output signal of the DUT to determine if the DUT is malfunctioning. The second predetermined time is the interval between waiting for the monitoring device. If the DUT is normal, the failure type is recorded as the second failure type, and the current test frequency and test power are also saved. If the DUT is malfunctioning, the monitoring screenshot of the DUT acquired by the monitoring device after the second predetermined action and the second predetermined time is saved. Then, a third predetermined action is executed: the DUT is powered on again, and the monitoring device is reset. Specifically, the power supply is turned off, and after the power supply interval ends, the power supply is turned on again to power on the DUT. After the DUT is powered on again, the monitoring device is reset. After a third predetermined time, the monitoring device again acquires the output signal of the DUT to determine if the DUT is malfunctioning. The third predetermined time is the interval between waiting for the monitoring device. If the chip under test is normal, the failure type is recorded as the third failure type, and the current test frequency and test power are also saved. If the chip under test is abnormal, the failure type is recorded as the fourth failure type, and the current test frequency and test power are also saved. At this time, the chip under test is completely damaged.

[0064] Determine if the test frequency has reached the frequency threshold. If it has not reached the frequency threshold, repeat the above test process until the test power reaches the power threshold.

[0065] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0066] The aforementioned chip failure type testing system includes a detection device and a processing device. The detection device outputs a detection signal to the chip under test (DUT). The processing device is communicatively connected to the detection device and electrically connected to the DUT. The processing device controls at least the test frequency and test power of the detection signal to test the DUT, and determines whether the DUT has failed and, if so, the failure type based on the output signal of the DUT during the test. This system connects the processing device to the detection device, controls at least the test frequency and test power of the detection signal to test the DUT, and determines whether the DUT has failed and, if so, the failure type based on the output signal of the DUT during the test. This achieves automated control of chip testing, thereby solving the problem of the inability to automatically identify and distinguish chip failure types in existing technologies.

[0067] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A chip failure type testing system, characterized in that, include: The detection device is used to output a detection signal to the chip under test; A processing device, communicatively connected to the detection device and electrically connected to the chip under test (DUT), is used to control at least the test frequency and test power of the detection signal to test the DUT, and to determine whether the DUT has failed based on the output signal of the DUT during the test, and, if it has failed, to determine the type of failure. The processing device includes: a processor, configured to control at least the test frequency and the test power of the detection signal to perform the test on the chip under test, and to determine the failure type in the event of failure; and a monitoring device, communicatively connected to the processor, configured to determine whether the chip under test has failed based on the output signal of the chip under test during the test process. The processing device is used to control at least the test frequency and test power of the detection signal to test the chip under test, and to determine whether the chip under test has failed and, if it has failed, to determine the failure type based on the output signal of the chip under test during the test process. This includes: acquiring a frequency range and a power range, wherein the frequency range and the power range are determined based on the chip under test; sequentially performing at least one set of tests on the chip under test, wherein the test frequency is the same in one set of tests, and if there are multiple sets of tests, the test frequencies of any two sets of tests are different; and in one set of tests, the test power of multiple tests is multiple powers in the power range from small to large; and, if the chip under test is determined to have failed, controlling the detection device to stop inputting the detection signal to the chip under test, and determining the failure type based on the output signal of the chip under test after a predetermined action and a predetermined time. Determining the failure type based on the output signal of the chip under test after a predetermined action and a predetermined time includes: after a first predetermined action and a first predetermined time, the monitoring device acquires the output signal of the chip under test, wherein the first predetermined action is to control the monitoring device to reset; if the monitoring device determines that the chip under test is normal based on the output signal, the processor determines the failure type as a first failure type; if the monitoring device determines that the chip under test is abnormal based on the output signal, after a second predetermined action and a second predetermined time, the processor acquires the output signal of the chip under test and determines the failure type, wherein the second predetermined action is to control the chip under test to reset and control the monitoring device to reset.

2. The system according to claim 1, characterized in that, The system also includes: The power supply device includes a first DC power supply and a second DC power supply. The first DC power supply and the second DC power supply are respectively communicatively connected to the processing device and electrically connected to the chip under test. The first DC power supply is used to supply power to the chip under test, and the second DC power supply is used to control the reset of the chip under test.

3. The system according to claim 1, characterized in that, The processing device is used to at least control the test frequency and test power of the detection signal to test the chip under test, and to determine whether the chip under test has failed based on the output signal of the chip under test during the test process, and to determine the failure type in the event of failure, and further includes: The first determining step is to determine whether the maximum value of the test power in the current group's test is less than the power threshold, provided that the chip under test is not faulty. The first control step involves controlling the test power to increase by a first predetermined step size when the maximum value of the test power is less than the power threshold, and determining whether the chip under test is faulty based on the output signal of the chip under test. The second determination step involves controlling the detection device to stop inputting the detection signal to the chip under test when the chip under test fails, and determining the failure type based on the predetermined action and the output signal of the chip under test after the predetermined time. If the chip under test is not faulty, repeat the first control step until the test power reaches the power threshold.

4. The system according to claim 1, characterized in that, The processing device is used to at least control the test frequency and test power of the detection signal to test the chip under test, and to determine whether the chip under test has failed based on the output signal of the chip under test during the test process, and to determine the failure type in the event of failure, and further includes: The third determination step, in the case of determining the failure type, is to determine whether the maximum value of the test frequency in the current group's tests is less than the frequency threshold; The second control step involves controlling the test frequency to increase by a second predetermined step size when the maximum value of the test frequency is less than the frequency threshold, so as to perform at least one set of tests on the chip under test. The test frequency is the same in one set of tests, and the test power of multiple tests in one set of tests is multiple power in the power range from small to large. The chip under test is then determined to be faulty based on the output signal of the chip under test. The fourth determination step involves controlling the detection device to stop inputting the detection signal to the chip under test when the chip under test fails, and determining the failure type based on the predetermined action and the output signal of the chip under test after the predetermined time. Repeat the second control step until the test frequency reaches the frequency threshold.

5. The system according to claim 1, characterized in that, After the second predetermined action and the second predetermined time, the output signal of the chip under test is acquired and the failure type is determined, including: After the second predetermined action and the second predetermined time, the monitoring device acquires the output signal of the chip under test; If the monitoring device determines that the chip under test is normal based on the output signal, the processor determines that the failure type is the second failure type; If the monitoring device determines that the chip under test is abnormal based on the output signal, it acquires the output signal of the chip under test and determines the failure type according to the third predetermined action and the third predetermined time. The third predetermined action is to control the chip under test to be powered on again and to control the monitoring device to be reset.

6. The system according to claim 5, characterized in that, After the third predetermined action and the third predetermined time, the output signal of the chip under test is acquired and the failure type is determined, including: After the third predetermined action and the third predetermined time, the monitoring device acquires the output signal of the chip under test; If the monitoring device determines that the chip under test is normal based on the output signal, the processor determines that the failure type is the third failure type. If the monitoring device determines that the chip under test is abnormal based on the output signal, the processor determines that the failure type is the fourth failure type.

7. The system according to any one of claims 1 to 6, characterized in that, The detection device includes: Radio frequency signal source, used to generate radio frequency interference signals; A radio frequency amplifier, electrically connected to the radio frequency signal source, is used to amplify the power of the radio frequency interference signal and separate the amplified radio frequency interference signal to obtain a forward power signal and a reflected power signal, wherein the forward power signal is the detection signal; A power meter, electrically connected to the radio frequency amplifier, is used to measure the power of the forward power signal.

8. The system according to any one of claims 1 to 6, characterized in that, The system also includes: The test board includes a detection signal injection point and a DC blocking capacitor. One end of the detection signal injection point is electrically connected to the detection device, one end of the DC blocking capacitor is electrically connected to the other end of the detection signal injection point, and the other end of the DC blocking capacitor is electrically connected to the chip under test. The chip under test is located on the test board.

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