Logic firmware loading method and device, electronic equipment and storage medium

Abstract

Embodiments of the present application disclose a logic firmware loading method and device, electronic equipment and a storage medium. The method comprises: querying device information of a programmable logic device in a to-be-processed daughter card connected to a mainboard; wherein the device information comprises a device identifier, or a device identifier and D flip-flop series connection information on a JTAG chain; determining a daughter card type of the to-be-processed daughter card according to the device information of the programmable logic device; and performing logic firmware loading on the programmable logic device in the to-be-processed daughter card according to the daughter card type of the to-be-processed daughter card. According to the application, the daughter card type can be accurately identified in the case that the device ID of the programmable logic device CPLD in the daughter card is the same or the single-board ID of the daughter card is not required, and the logic firmware of the programmable logic device CPLD in the daughter card is automatically loaded, thereby avoiding the use of a large number of single-board ID signal bits due to a large number of daughter cards, and thus a large number of connector pins and mainboard hardware resources are occupied.

Description

Technical Field

[0001] The present invention relates to the field of computer application technology, and in particular to a logical firmware loading method, apparatus, electronic device and storage medium. Background Technology

[0002] Typically, the hardware of a complex electronic device consists of a motherboard and multiple daughter cards. During the design phase, each daughter card is assigned a unique board ID. During system software initialization, the board ID needs to be identified to perform the corresponding initialization configuration for each board, such as loading the logic firmware of programmable devices. However, obtaining the board ID is achieved by defining an ID signal on the connector that connects the board to the motherboard. The more bits the ID signal has, the more board IDs it supports, and the less likely it is to conflict. However, a large number of board ID bits often occupies connector pins and consumes a significant amount of motherboard hardware resources. Furthermore, a complex system platform often has a long lifespan, making it highly susceptible to running out of board IDs. Summary of the Invention

[0003] This invention provides a logic firmware loading method, apparatus, electronic device, and storage medium to enable loading of programmable device logic firmware without requiring a board ID.

[0004] In a first aspect, embodiments of the present invention provide a logical firmware loading method, the method comprising:

[0005] Query the device information of the programmable logic device in the daughter card to be processed connected to the motherboard; wherein the device information includes the device identifier, or the device identifier and the serial connection information of D flip-flops on the JTAG chain;

[0006] Based on the device information of the programmable logic device, determine the sub-card type of the sub-card to be processed;

[0007] Based on the sub-card type of the sub-card to be processed, the programmable logic devices in the sub-card to be processed are loaded with logic firmware.

[0008] Secondly, this invention also provides a logic firmware loading device, which includes:

[0009] The device information query module is used to query the device information of the programmable logic devices in the daughter card to be processed connected to the motherboard; wherein the device information includes the device identifier, or the device identifier and the serial connection information of D flip-flops on the JTAG chain;

[0010] The sub-card type determination module is used to determine the sub-card type of the sub-card to be processed based on the device information of the programmable logic device;

[0011] The logic firmware loading module is used to load the logic firmware of the programmable logic devices in the sub-card to be processed according to the sub-card type.

[0012] Thirdly, this invention also provides an electronic device, comprising:

[0013] One or more processors;

[0014] Storage device for storing one or more programs;

[0015] The one or more programs are executed by the one or more processors, causing the one or more processors to implement the logical firmware loading method provided in any embodiment of the present invention.

[0016] Fourthly, embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the logical firmware loading method provided in any embodiment of the present invention.

[0017] This invention provides a method for loading logic firmware. The method queries the device information of programmable logic devices (CPLDs) in a daughter card connected to the motherboard. The device information includes a device identifier, or a device identifier and the serial connection information of D flip-flops on the JTAG chain. Based on the device information, the daughter card type is determined, and then the logic firmware of the CPLDs in the daughter card is loaded. Using the technical solution provided in this application, even when the device IDs of the CPLDs in the daughter cards are the same or the single-board ID of the daughter card is not required, the daughter card type can still be accurately identified. This allows for automatic loading of the logic firmware for the CPLDs in the daughter card, avoiding the problem of insufficient single-board IDs due to the large number of daughter cards and the resulting high number of connector pins. Simultaneously, it improves the expandability of the motherboard for connecting daughter cards and avoids the problem of insufficient single-board IDs.

[0018] The above description of the invention is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0019] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. The drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0020] Figure 1 This is a flowchart of a logic firmware loading method provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of a motherboard connection daughter card provided in an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of another motherboard connection daughter card provided in an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of another motherboard connection daughter card provided in an embodiment of the present invention;

[0024] Figure 5 This is a flowchart of another logical firmware loading method provided in this embodiment of the invention;

[0025] Figure 6 This is a logic flowchart of automatic loading of logical firmware provided in an embodiment of the present invention;

[0026] Figure 7 This is a structural diagram of a logic firmware loading device provided in an embodiment of the present invention;

[0027] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention and not the entire structure.

[0029] Before discussing the exemplary embodiments in more detail, it should be mentioned that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts describe the operations (or steps) as sequential processes, many of the operations (or steps) may be performed in parallel, concurrently, or simultaneously. Furthermore, the order of the operations may be rearranged. The process may be terminated when its operation is completed, but may also have additional steps not included in the figures. The process may correspond to a method, function, procedure, subroutine, subroutine, etc.

[0030] The following describes in detail the logical firmware loading method, apparatus, electronic device, and storage medium provided in the embodiments of the present invention through various examples.

[0031] Figure 1This is a flowchart illustrating a logic firmware loading method provided in an embodiment of the present invention. This embodiment is applicable to situations where the CPLD logic firmware of each daughter card is automatically loaded. This method can be executed by a logic firmware loading device, which can be implemented in software and / or hardware and can be integrated into any electronic device with network communication capabilities. Figure 1 As shown, the logical firmware loading method provided in this embodiment of the invention may include the following steps:

[0032] S110. Query the device information of the programmable logic device in the daughter card to be processed connected to the motherboard; wherein the device information includes the device identifier, or the device identifier and the serial connection information of the D flip-flops on the JTAG chain.

[0033] S120. Determine the sub-card type of the sub-card to be processed based on the device information of the programmable logic device.

[0034] Defining an ID signal on the connector connecting the daughter card and the motherboard typically involves adding a board ID to the daughter card and loading different CPLD firmware based on the different board IDs. However, board ID signals have many bits, often occupying connector pins and consuming significant motherboard hardware resources. Furthermore, a system platform's lifespan is often long, making it prone to running out of board IDs. Alternatively, besides board IDs, a low-speed bus such as an I2C interface or serial port can be added to the daughter card, allowing the daughter card type to be read via I2C or serial. However, implementing I2C or serial port functionality on the daughter card significantly increases its hardware cost. Therefore, relying on board IDs, I2C interfaces, or serial port functionality for daughter card type identification and firmware loading has certain drawbacks.

[0035] Based on the above, the unique characteristics of the CPLD integrated in the daughter card can be utilized. After selecting the daughter card to be upgraded, a certain number of interface clock signals (TCK) are sent to the CPLD in the selected daughter card to read its device identifier (DEVICE ID). Then, based on the pre-recorded device identifiers of the CPLDs integrated in each daughter card supported by the motherboard, the type of daughter card to be upgraded can be determined.

[0036] For each daughter card supported by the motherboard, if multiple daughter cards are designed with programmable logic devices (CPLDs) with different device identifiers, then by reading the device identifier of the CPLD in the daughter card to be processed, the different daughter cards can be distinguished by identifying the device identifier of the CPLD, and the daughter card type of the daughter card to be processed can be determined.

[0037] For the various daughter cards supported by the motherboard, different daughter cards may also have programmable logic devices (CPLDs) with the same device identifier. Therefore, relying solely on reading the device identifier of the CPLD in the daughter card may not be sufficient to distinguish the daughter card type. To address this, in addition to referring to the device identifier of the CPLD, the cascading arrangement of the D flip-flops on the JTAG chain of the programmable logic devices in different daughter cards with the same device identifier can also be considered. This allows for differentiation between different types of daughter cards with the same device identifier. The D flip-flops on the JTAG chain can be single-bit D flip-flops.

[0038] S130. Based on the sub-card type of the sub-card to be processed, load the logic firmware of the programmable logic device in the sub-card to be processed.

[0039] By introducing the device identifier of the programmable logic device in the daughter card and the cascade connection method of the programmable logic device and the D flip-flop, the daughter card type can be set accordingly. Even if different daughter cards have programmable logic devices with the same device identifier, the daughter card type can still be distinguished based on the device identifier of the programmable logic device in the daughter card, or based on the combination of the device identifier of the programmable logic device and the cascade connection method of the D flip-flop on the JTAG chain of the programmable logic device. Furthermore, the logic firmware of the corresponding programmable logic device CPLD in the daughter card to be processed can be automatically loaded according to the daughter card type.

[0040] As an alternative, for different types of daughter cards of programmable logic devices (CPLDs) with different device identifiers, the type of daughter card can be distinguished by the different device identifiers of the programmable logic devices integrated in the different daughter cards.

[0041] As another alternative, see Figure 2 , Figure 3 as well as Figure 4 For different types of daughter cards of programmable logic devices (CPLDs) with the same device identifier, the daughter card type can be distinguished by the device identifier of the programmable logic device integrated in the daughter card and the number of D flip-flops connected in series on the interface data output signal TDO of the programmable logic device JTAG chain.

[0042] According to the logic firmware loading method provided in the embodiments of the present invention, even when the device IDs of the programmable logic devices (CPLDs) in the daughter card are the same or the single-board ID of the daughter card is not required, the daughter card type can still be accurately identified to automatically load the logic firmware of the programmable logic devices (CPLDs) in the daughter card. This avoids the problem of using the single-board ID of the daughter card, which would result in a large number of single-board ID signal bits occupying a large number of connector pins and thus occupying a large amount of motherboard hardware resources due to the large number of daughter cards. At the same time, it can improve the expandability of the motherboard to connect daughter cards and avoid the problem of insufficient single-board IDs.

[0043] Figure 5 This is a flowchart of another logical firmware loading method provided in this embodiment of the invention. This embodiment is an optimization based on the above embodiments, and this embodiment of the invention can be combined with various optional solutions in one or more of the above embodiments. For example... Figure 5 As shown, the logical firmware loading method provided in this embodiment of the invention may include the following steps:

[0044] S510 sends at least one target value period of interface clock signal to the programmable logic device in the daughter card to be processed connected to the motherboard, in order to read the device identifier of the programmable logic device.

[0045] The target value is greater than or equal to the preset number of device identifier bits.

[0046] See Figure 2 , Figure 3 as well as Figure 4 Assume the motherboard supports three sub-cards: sub-card 1, sub-card 2, and sub-card 3. All three sub-cards use programmable logic devices (CPLDs) with the same device identifier, such as the M8866 CPLD, whose device identifier is 0x4c37. Referring to Table 1, CPLDs with the same device identifier are used in different sub-cards to match appropriate functions. Therefore, the CPLDs in sub-cards 1, 2, and 3 will correspond to different CPLD firmware 1, firmware 2, and firmware 3, respectively. This demonstrates that even CPLDs with the same device identifier do not necessarily use the same firmware.

[0047] Table 1. Logic firmware of CPLDs with the same device identifier in different daughter cards

[0048] Sub-card name CPLD model CPLD firmware Sub-card 1 M8866 Firmware 1 Sub-card 2 M8866 Firmware 2 Sub-card 3 M8866 Firmware 3

[0049] For different daughter cards with the same device identifier for programmable logic devices, if the number of pre-connected D flip-flops in the programmable logic device is different, the number of cycles of the interface clock signal TCK required to read the device identifier of the programmable logic device with the same device identifier in different daughter cards will be different. Therefore, it is necessary to adjust the number of cycles of the interface clock signal TCK based on the preset value of the number of bits of the device identifier, and use several different target values ​​of the interface clock signal TCK to read the device identifier according to the number of D flip-flops connected in the JTAG chain of the programmable logic device in each daughter card, so as to read the correct device identifier under a target value.

[0050] Optionally, for different daughter cards of programmable logic devices with the same device identifier, when loading the corresponding CPLD firmware according to the CPLD, if the device identifiers of the programmable logic devices CPLDs in different daughter cards are the same, then M D flip-flops (falling edge triggered) are connected in series on the last interface data output signal TDO signal of the JTAG chain of the programmable logic device CPLD in different daughter cards, where M is greater than or equal to 1, and the value of M used in different daughter cards of programmable logic devices with the same device identifier is different. In this way, when reading the device identifier of the programmable logic device in the daughter card, it is only necessary to add M cycles to the interface clock signal TCK based on the preset device identifier bit value, and shift the mask left by M bits to obtain the correct device identifier of the corresponding programmable logic device CPLD.

[0051] See Figure 2 When zero 1-bit D flip-flops are connected in series on the CPLD of the programmable logic device in daughter card 1, 16 TCKs need to be sent when reading the device identifier of the CPLD in daughter card 1. The value read should be 0x4c37, and the mask is 0xffff, which means that the device identifier of the CPLD is read correctly.

[0052] See Figure 3 When a 1-bit D flip-flop is connected in series on the CPLD of the programmable logic device in daughter card 2, (16+1) TCKs need to be sent when reading the device identifier of the CPLD in daughter card 2. The value read should be 0x986f, the mask is 0x1fffe, and the final value after mask calculation is the correct device identifier 0x4c37.

[0053] Similarly, see Figure 4When two 1-bit D flip-flops are connected in series on the CPLD of the programmable logic device in daughter card 3, it is necessary to send (16+2) TCKs when reading the device identifier of the CPLD in daughter card 3. The result reads 0x130df, the mask is 0x3fffc, and the final value after mask calculation is the correct device identifier 0x4c37.

[0054] In one optional embodiment, before querying the device information of the programmable logic device in the daughter card to be processed connected to the motherboard, steps A1-A3 are further included:

[0055] Step A1: The motherboard sends an interface clock signal to the programmable logic device in the daughter card to be processed, and controls the TMS timing to make the programmable logic device on the daughter card enter the instruction register shift (SHIFT_IR) mode.

[0056] Step A2: The motherboard sends a device identification instruction to the programmable logic device in the daughter card to be processed.

[0057] Step A3: The motherboard sends the interface clock signal again to the programmable logic device (CPLD) in the daughter card to be processed, controlling the TMS timing to put the CPLD into the data register shift (SHIFT_DR) mode. Based on this, the CPLD in the daughter card can sequentially enter the instruction register shift (SHIFT_IR) mode and the data register shift (SHIFT_DR) mode, thus enabling the motherboard to send the interface clock signal TCK to the CPLD connected to the motherboard to perform a device identifier read operation.

[0058] S520. Based on the device identifier reading result corresponding to at least one target value cycle, determine the device information of the programmable logic device in the sub-card to be processed.

[0059] The information on the cascaded D flip-flops on the JTAG chain of the programmable logic device includes the number of D flip-flops pre-cascaded on the interface data output signal TDO of the JTAG chain of the programmable logic device.

[0060] In one optional embodiment, the device information of the programmable logic device in the daughter card to be processed is determined based on the device identifier reading result corresponding to at least one target value cycle, including steps B1-B2:

[0061] Step B1: Determine the preset mask information associated with each period of the target value based on the incremental change value of at least one target value relative to the preset device identifier bit value.

[0062] Step B2: Based on the preset mask information associated with the target value period and the corresponding device identifier reading results, determine the device identifier of the programmable logic device and the number of pre-connected D flip-flops on the JTAG chain of the programmable logic device.

[0063] See Figure 2 , Figure 3 as well as Figure 4 For different daughter cards with the same device identifier for programmable logic devices, if the preset device identifier bit length of the programmable logic device in a daughter card is N, and the number of D flip-flops pre-connected in series on the interface data output signal TDO of the JTAG chain of the programmable logic device is M, then (N+M) cycles of interface clock signals need to be sent to the programmable logic device to correctly read its device identifier. It is easy to see that for any target value, the incremental change of the target value relative to the preset device identifier bit length is actually related to the number of D flip-flops pre-connected in series on the interface data output signal TDO of the JTAG chain of the programmable logic device.

[0064] Of course, the incremental change value M of the target value relative to the preset device identifier bit value is an attempt value configured in the transmit interface clock signal TCK. The incremental change value M used under different device identifier reading operations is constantly changed. This is so that different target values ​​can be used to try to send different numbers of interface clock signals TCK in order to read the correct device identifier of the programmable logic device.

[0065] See Figure 6 The process involves determining the associated preset mask information by the incremental change of the target value relative to the preset device identifier bit value. Then, based on the preset mask information, a reverse value is calculated for the device identifier read result corresponding to the target value over a given period. This reverse value is then used to determine if it belongs to the preset device identifier value. If it does, the correct device identifier is considered to be obtainable under the target value. In this case, the incremental change of the target number relative to the preset device identifier bit value is determined as the pre-connected number of programmable logic devices and D flip-flops in the daughter card to be processed; and the obtained reverse value is used as the device identifier of the programmable logic device. If it does not exist, the correct device identifier is considered not to be obtainable under the target value. The target value needs to be updated, and the programmable logic device (CPLD) is re-entered into instruction register shift SHIFT_IR mode and data register shift SHIFT_DR mode, and the updated interface clock signal for the target value period is sent. The device identifier read operation for the programmable logic device in the daughter card to be processed is then performed again.

[0066] As an optional approach, the preset device identifier bit length value is determined based on the device identifier bit length of the programmable logic devices in different daughter cards. Where the device identifier bit length of the programmable logic devices in different daughter cards is the same or partially the same, all different bit length values ​​are used as the preset device identifier bit length values.

[0067] As an optional approach, the target value used during multiple consecutive device identifier reads increases relative to the preset device identifier bit length by a preset value. During device identifier reads, which involves sending an interface clock signal for one cycle of the target value, a target value may fail to read correctly. Therefore, the target value needs to be updated before querying the device identifier again. The preset value is 1. Thus, the target value can be updated sequentially to: N, (N+1), (N+2), ..., (N+M), increasing by 1 each time compared to the previous target.

[0068] S530: Determine the sub-card type of the sub-card to be processed based on the device information of the programmable logic device.

[0069] S540: Based on the sub-card type of the sub-card to be processed, load the logic firmware of the programmable logic device in the sub-card to be processed.

[0070] According to the logic firmware loading method provided in the embodiments of the present invention, the type of the programmable logic device (CPLD) in the daughter card can be accurately identified when the device IDs of the CPLDs in the daughter card are the same or when the single board ID of the daughter card is not required. Even if different daughter cards have CPLDs with the same device identifier, the daughter card type can still be identified to automatically load the logic firmware of the CPLDs in the daughter card. This avoids the problem of using the single board ID of the daughter card, which would result in a large number of single board ID signal bits occupying a large number of connector pins and thus occupying a large amount of motherboard hardware resources due to the large number of daughter cards. At the same time, it can improve the expandability of the motherboard to connect daughter cards and avoid the problem of insufficient single board IDs.

[0071] Figure 7 This is a structural diagram of a logic firmware loading device provided in an embodiment of the present invention. This embodiment is applicable to situations where the CPLD logic firmware of each daughter card is automatically loaded. This device can be implemented in software and / or hardware and can be integrated into any electronic device with network communication capabilities. Figure 7 As shown, the logical firmware loading device provided in this embodiment of the invention may include the following:

[0072] The device information query module 710 is used to query the device information of the programmable logic device in the daughter card to be processed connected to the motherboard; wherein the device information includes the device identifier, or the device identifier and the serial connection information of the D flip-flops on the JTAG chain.

[0073] The sub-card type determination module 720 is used to determine the sub-card type of the sub-card to be processed based on the device label information of the programmable logic device;

[0074] The logic firmware loading module 730 is used to load logic firmware onto the programmable logic devices in the sub-card to be processed according to the sub-card type of the sub-card to be processed.

[0075] Based on the above embodiments, optionally, the device information query module 710 includes:

[0076] Send at least one target value for one cycle of an interface clock signal to the programmable logic device in the daughter card to be processed connected to the motherboard, so as to read the device identifier of the programmable logic device;

[0077] Based on the device identifier reading results corresponding to each cycle of the at least one target value, the device information of the programmable logic device in the sub-card to be processed is determined;

[0078] Wherein, the target value is greater than or equal to the value of the preset number of device identifier bits, and the JTAG chain D flip-flop cascade information includes the number of D flip-flops pre-cascaded on the interface data output signal TDO of the JTAG chain of the programmable logic device.

[0079] Based on the above embodiments, optionally, the device information of the programmable logic device in the sub-card to be processed is determined according to the device identifier reading result corresponding to the at least one target value period, including:

[0080] Based on the incremental change of the at least one target value relative to the preset device identifier bit value, the preset mask information associated with the target value in each period is determined;

[0081] Based on the preset mask information associated with each period of the target value and the corresponding device identifier reading result, the device identifier of the programmable logic device and the number of pre-connected D flip-flops on the JTAG chain of the programmable logic device are determined.

[0082] Based on the above embodiments, optionally, the preset device identifier bit length value is determined based on the device identifier bit length of the programmable logic devices in different daughter cards.

[0083] Based on the above embodiments, optionally, the target value used in the process of reading device identifiers in successive times increases with respect to the preset number of device identifier bits according to a preset value.

[0084] Based on the above embodiments, optionally, before querying the device information of the programmable logic device in the daughter card to be processed connected to the motherboard, the process includes:

[0085] The motherboard sends an interface clock signal to the programmable logic device in the daughter card to be processed, and controls the TMS timing to make the programmable logic device on the daughter card to be processed enter the instruction register shift mode.

[0086] The motherboard sends a device identification command to the programmable logic device in the daughter card to be processed;

[0087] The motherboard sends the interface clock signal to the programmable logic device in the daughter card to be processed again, and controls the TMS timing to make the programmable logic device on the daughter card to be processed enter the data register shift mode.

[0088] The logical firmware loading device provided in the embodiments of the present invention can execute the logical firmware loading method provided in any of the embodiments of the present invention, and has the corresponding functions and beneficial effects of executing the logical firmware loading method. For technical details not described in detail in the above embodiments, please refer to the logical firmware loading method provided in any of the embodiments of this application.

[0089] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. For example... Figure 8 The structure shown in this embodiment of the invention includes an electronic device comprising one or more processors 810 and a storage device 820; the processors 810 in this electronic device may be one or more. Figure 8 Taking a processor 810 as an example; storage device 820 is used to store one or more programs; the one or more programs are executed by the one or more processors 810, so that the one or more processors 810 implement the logical firmware loading method as described in any one of the embodiments of the present invention.

[0090] The electronic device may also include an input device 830 and an output device 840.

[0091] The processor 810, storage device 820, input device 830, and output device 840 in this electronic device can be connected via a bus or other means. Figure 8 Taking the example of a connection between China and Israel via a bus.

[0092] The storage device 820 in this electronic device serves as a computer-readable storage medium, capable of storing one or more programs. These programs can be software programs, computer-executable programs, or modules, such as the program instructions / modules corresponding to the logical firmware loading method provided in this embodiment of the invention. The processor 810 executes various functional applications and data processing of the electronic device by running the software programs, instructions, and modules stored in the storage device 820, thereby implementing the logical firmware loading method described in the above embodiment.

[0093] Storage device 820 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, storage device 820 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some instances, storage device 820 may further include memory remotely located relative to processor 810, which can be connected to the device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0094] Input device 830 can be used to receive input digital or character information, and to generate key signal inputs related to user settings and function control of the electronic device. Output device 840 may include display devices such as a display screen.

[0095] Furthermore, when one or more programs included in the aforementioned electronic device are executed by one or more processors 810, the programs perform the following operations:

[0096] Query the device information of the programmable logic device in the daughter card to be processed connected to the motherboard; wherein the device information includes the device identifier, or the device identifier and the serial connection information of D flip-flops on the JTAG chain;

[0097] Based on the device information of the programmable logic device, determine the sub-card type of the sub-card to be processed;

[0098] Based on the sub-card type of the sub-card to be processed, the programmable logic devices in the sub-card to be processed are loaded with logic firmware.

[0099] Of course, those skilled in the art will understand that when one or more programs included in the above-mentioned electronic device are executed by one or more processors 810, the programs can also perform related operations in the logical firmware loading method provided in any embodiment of the present invention.

[0100] This invention provides a computer-readable storage medium storing a computer program thereon. When executed by a processor, the program is used to perform a logical firmware loading method, the method comprising:

[0101] Query the device information of the programmable logic device in the daughter card to be processed connected to the motherboard; wherein the device information includes the device identifier, or the device identifier and the serial connection information of D flip-flops on the JTAG chain;

[0102] Based on the device information of the programmable logic device, determine the sub-card type of the sub-card to be processed;

[0103] Based on the sub-card type of the sub-card to be processed, the programmable logic devices in the sub-card to be processed are loaded with logic firmware.

[0104] Optionally, when the program is executed by the processor, it can also be used to execute the logical firmware loading method provided in any embodiment of the present invention.

[0105] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, a portable CD-ROM, an optical storage device, a magnetic storage device, or any suitable combination thereof. A computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0106] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit programs for use by or in connection with an instruction execution system, apparatus, or device.

[0107] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to: wireless, wire, optical fiber, radio frequency (RF), etc., or any suitable combination thereof.

[0108] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0109] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0110] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A method for loading logical firmware, characterized in that, The method includes: Query the device information of the programmable logic device in the daughter card to be processed connected to the motherboard; wherein the device information includes the device identifier, or the device identifier and the serial connection information of D flip-flops on the JTAG chain; Based on the device information of the programmable logic device, the sub-card type of the sub-card to be processed is determined; wherein, the sub-card type is distinguished by the different device identifiers of the programmable logic devices integrated in different sub-cards, or by the device identifier of the programmable logic device integrated in the sub-card and the number of D flip-flops connected in series on the interface data output signal TDO of the JTAG chain of the programmable logic device. Based on the sub-card type of the sub-card to be processed, the programmable logic device in the sub-card to be processed is loaded with logic firmware; The query of device information for programmable logic devices in the daughter card to be processed connected to the motherboard includes: Send at least one target value for one cycle of an interface clock signal to the programmable logic device in the daughter card to be processed connected to the motherboard, so as to read the device identifier of the programmable logic device; Based on the device identifier reading results corresponding to each cycle of the at least one target value, the device information of the programmable logic device in the sub-card to be processed is determined; Wherein, the target value is greater than or equal to the value of the preset number of device identifier bits, and the JTAG chain D flip-flop cascade information includes the number of D flip-flops pre-cascaded on the interface data output signal TDO of the JTAG chain of the programmable logic device.

2. The method according to claim 1, characterized in that, Based on the device identifier reading results corresponding to at least one target value cycle, the device information of the programmable logic device in the daughter card to be processed is determined, including: Based on the incremental change of the at least one target value relative to the preset device identifier bit value, the preset mask information associated with the target value in each period is determined; Based on the preset mask information associated with each period of the target value and the corresponding device identifier reading result, the device identifier of the programmable logic device and the number of pre-connected D flip-flops on the JTAG chain of the programmable logic device are determined.

3. The method according to claim 1 or 2, characterized in that, The preset device identifier bit length is determined based on the device identifier bit length of the programmable logic devices in different daughter cards.

4. The method according to claim 1 or 2, characterized in that, During multiple consecutive device identifier readings, the target value used increases relative to the preset device identifier bit length according to a preset value.

5. The method according to claim 1, characterized in that, Before querying the device information of the programmable logic devices in the daughter card connected to the motherboard, the process includes: The motherboard sends an interface clock signal to the programmable logic device in the daughter card to be processed, and controls the TMS timing to make the programmable logic device on the daughter card to be processed enter the instruction register shift mode. The motherboard sends a device identification command to the programmable logic device in the daughter card to be processed; The motherboard sends the interface clock signal to the programmable logic device in the daughter card to be processed again, and controls the TMS timing to make the programmable logic device on the daughter card to be processed enter the data register shift mode.

6. A logic firmware loading device, characterized in that, The device includes: The device information query module is used to query the device information of the programmable logic devices in the daughter card to be processed connected to the motherboard; wherein the device information includes the device identifier, or the device identifier and the serial connection information of D flip-flops on the JTAG chain; The daughter card type determination module is used to determine the daughter card type of the daughter card to be processed based on the device identifier information of the programmable logic device; wherein, the daughter card type is distinguished by the different device identifiers of the programmable logic devices integrated in different daughter cards, or by the device identifier of the programmable logic device integrated in the daughter card and the number of D flip-flops connected in series on the interface data output signal TDO of the JTAG chain of the programmable logic device. The logic firmware loading module is used to load the logic firmware of the programmable logic devices in the sub-card to be processed according to the sub-card type. The query of device information for programmable logic devices in the daughter card to be processed connected to the motherboard includes: Send at least one target value for one cycle of an interface clock signal to the programmable logic device in the daughter card to be processed connected to the motherboard, so as to read the device identifier of the programmable logic device; Based on the device identifier reading results corresponding to each cycle of the at least one target value, the device information of the programmable logic device in the sub-card to be processed is determined; Wherein, the target value is greater than or equal to the value of the preset number of device identifier bits, and the JTAG chain D flip-flop cascade information includes the number of D flip-flops pre-cascaded on the interface data output signal TDO of the JTAG chain of the programmable logic device.

7. An electronic device, characterized in that, include: One or more processors; Storage device for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the logical firmware loading method according to any one of claims 1-5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the logical firmware loading method as described in any one of claims 1-5.

Images