Memory fault handling methods, devices and storage media

Abstract

This application discloses a memory fault handling method, apparatus, and storage medium, relating to the field of memory technology, for improving the efficiency of memory fault repair. The method includes: an out-of-band controller acquiring memory fault information, the fault information indicating that at least one cache block has failed; the out-of-band controller determining the fault severity of a target cache block based on the fault information, the target cache block being one of at least one cache blocks; the out-of-band controller determining a target replacement cache block based on the fault severity of the target cache block; the target replacement cache block being a cache block that has currently replaced a historically failed cache block, the fault severity of the target cache block being greater than or equal to the fault severity of the historically failed cache block; and the out-of-band controller sending a repair request to a central processing unit (CPU); the repair request requesting the CPU to repair the fault in the target cache block, the repair request carrying marking information of the target replacement cache block.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a memory fault handling method, apparatus and storage medium. Background Technology

[0002] Memory, as a crucial storage module in computer devices, is used to retrieve and store data. Therefore, memory failure can significantly impact the operation of the entire computer. Currently, to repair faulty cache blocks in memory, a method called Partial Cache Line Sparing (PCLS) is used, where faulty cache blocks are replaced. However, considering memory costs, the number of replaceable cache blocks is limited. Therefore, efficiently utilizing these limited replacement cache blocks to repair memory faults is a pressing issue that needs to be addressed. Summary of the Invention

[0003] This application provides a memory fault handling method, apparatus, and storage medium to improve the efficiency of memory fault repair.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] Firstly, a memory fault handling method is provided, comprising: an out-of-band controller acquiring memory fault information, the fault information indicating that at least one cache block has failed; the out-of-band controller determining the fault severity of a target cache block based on the fault information, the target cache block being one of the at least one cache blocks; the out-of-band controller determining a target replacement cache block based on the fault severity of the target cache block; the target replacement cache block being a cache block that has currently replaced a historically failed cache block, the fault severity of the target cache block being greater than or equal to the fault severity of the historically failed cache block; and the out-of-band controller sending a repair request to a central processing unit (CPU); the repair request requesting the CPU to repair the fault in the target cache block, the repair request carrying marking information of the target replacement cache block.

[0006] When current memory faults are repaired using PCLS technology, the number of cache blocks that can be replaced is limited. In response, this application proposes to determine the repair strategy based on the severity of the fault in the target cache block. When the limited number of replacement cache blocks are all occupied by historical faulty cache blocks, the repair resources of historical faulty cache blocks with a fault severity lower than that of the target cache block are used to repair the target cache block. This helps to use the limited repair resources to repair faults that are more likely to affect the system, thereby improving the efficiency of memory fault repair.

[0007] In one possible implementation, the out-of-band controller determines the severity of the target cache block's fault based on fault information, including: counting the number of times the target cache block's fault occurs within a preset time period; wherein, the number of fault occurrences is used to characterize the severity of the target cache block's fault, and the preset time period refers to the time period from the time the server where the memory is located to the present.

[0008] One possible implementation provides a specific method for obtaining the fault severity of a target cache block. By statistically analyzing the number of faults occurring in the target cache block within a preset time period, the fault severity of the target cache block is characterized based on the number of faults, which helps to evaluate each faulty cache block and identify cache blocks that are more likely to have an impact on the system.

[0009] In one possible implementation, the out-of-band controller determines the severity of a target cache block's fault based on fault information, including: inputting the fault information of the target cache block into a fault model and outputting the severity of the target cache block's fault; wherein the fault information includes at least one of location information, fault occurrence time, and fault occurrence count.

[0010] One possible implementation provides a specific method for obtaining the fault severity of a target cache block. By using a fault model to output the fault severity of the cache block that has failed based on the fault information, it helps to avoid user involvement in calculations and data processing, avoid human errors caused by user operations, and thus improve the accuracy of fault prediction results.

[0011] In one possible implementation, the fault information includes location information of at least one cache block where a fault occurred. Before the out-of-band controller determines the severity of the fault of the target cache block based on the fault information, the method further includes: determining the fault type of at least one cache block based on the location information of the at least one cache block where a fault occurred; determining the cache block with the fault type of single point of failure as the target cache block, wherein the row address of the target cache block is different from the row addresses of other cache blocks that have failed, and the column address of the target cache block is different from the column addresses of other cache blocks that have failed.

[0012] This possible implementation provides a specific method for determining the target cache block. It determines whether the cache block is the target cache block by judging whether the fault type of the cache block is a single point of failure. That is, for cache blocks with a single point of failure, the fault can be repaired by replacing the cache block.

[0013] In one possible implementation, the target replacement cache block is the cache block that has currently replaced the historical faulty cache block with the least fault severity.

[0014] In this possible implementation, by identifying the replacement cache block corresponding to the historical fault cache block with the lowest fault severity as the target replacement cache block, it is helpful to use the replacement cache block to repair faults with higher fault severity, thereby reducing the risk of higher fault severity affecting the system.

[0015] In one possible implementation, the method further includes: receiving the fault repair result of the target cache block sent by the CPU; when the fault repair result indicates successful repair, the out-of-band controller saves the correspondence between the target cache block and the replacement cache block that replaces the target cache block; when the fault repair result carries the tag information of the target replacement cache block and indicates successful repair, the out-of-band controller updates the correspondence between the target replacement cache block and the historical faulty cache block to the correspondence between the target replacement cache block and the target cache block.

[0016] In this possible implementation, the correspondence between the faulty cache block and the repaired resources is updated by receiving the fault repair results from the CPU. This helps determine whether the target cache block occupies a limited number of replacement cache blocks based on the fault repair results. Consequently, when a fault occurs again, the severity of the fault between the next faulty cache block and the target cache block is determined, thus identifying a target replacement cache block for the next faulty cache block.

[0017] Secondly, a memory fault handling apparatus is provided, comprising: functional units for executing any of the methods provided in the first aspect, wherein the actions performed by each functional unit are implemented in hardware or by hardware executing corresponding software. For example, the apparatus may include: an acquisition unit, a processing unit, and a sending unit; the acquisition unit is used to acquire memory fault information, the fault information indicating that at least one cache block has failed; the processing unit is used to determine the fault severity of a target cache block based on the fault information, the target cache block being one of at least one cache block; the processing unit is further used to determine a target replacement cache block based on the fault severity of the target cache block; the target replacement cache block is used to replace the target cache block, the target replacement cache block being a cache block that has currently replaced a historically failed cache block, and the fault severity of the target cache block is greater than or equal to the fault severity of the historically failed cache block; the sending unit is used to send a repair request to the CPU; the repair request is used to request the CPU to repair the fault of the target cache block, and the repair request carries marking information of the target replacement cache block.

[0018] Thirdly, a computer device is provided, comprising: a processor and a memory. The processor is connected to the memory, the memory being used to store computer execution instructions, and the processor executing the computer execution instructions stored in the memory, thereby implementing any of the methods provided in the first aspect.

[0019] Fourthly, a chip is provided, comprising: a processor and an interface circuit; the interface circuit for receiving code instructions and transmitting them to the processor; and the processor for executing the code instructions to perform any of the methods provided in the first aspect.

[0020] Fifthly, a computer-readable storage medium is provided, including computer-executable instructions that, when executed on a computer, cause the computer to perform any of the methods provided in the first aspect.

[0021] In a sixth aspect, a computer program product is provided, including computer execution instructions that, when executed on a computer, cause the computer to perform any of the methods provided in the first aspect.

[0022] The technical effects of any of the implementation methods in aspects two through six can be found in the technical effects of the corresponding implementation methods in aspect one, and will not be repeated here. Attached Figure Description

[0023] Figure 1 This application provides a schematic diagram of the composition of a computer device according to an embodiment of the present application.

[0024] Figure 2 This is a flowchart illustrating a memory fault repair method.

[0025] Figure 3 This is a flowchart illustrating a memory fault repair method.

[0026] Figure 4 A flowchart illustrating a memory fault repair method provided in an embodiment of this application;

[0027] Figure 5 A flowchart illustrating a memory fault repair method provided in an embodiment of this application;

[0028] Figure 6 This is an interactive schematic diagram of a memory fault repair system provided in an embodiment of this application;

[0029] Figure 7 This is a schematic diagram of the composition of a memory fault repair device provided in an embodiment of this application. Detailed Implementation

[0030] In the description of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B. The "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" means one or more, and "multiple" means two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.

[0031] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0032] like Figure 1 The diagram shown is a system architecture diagram provided in an embodiment of this application. This system architecture diagram is an architecture diagram of a computer device. (Reference) Figure 1 The hardware of this computer device includes a processor, an out-of-band controller, and memory. The software primarily includes an out-of-band management module, processor firmware, and an operating system (OS) management unit. The out-of-band management module is located within the out-of-band controller, the OS management unit is located within the processor, and the processor firmware can be located within the processor (e.g.,...). Figure 1 (as shown), or the processor firmware can also be located on a firmware chip outside the processor (as shown). Figure 1 (Not shown in the image). The out-of-band management module can be a management unit for non-business modules. For example, the out-of-band management module can remotely maintain and manage the server through a dedicated data channel. This out-of-band management module is completely independent of the server's operating system and can communicate with the basic input / output system (BIOS) and the OS (or OS management unit) through the server's out-of-band management interface.

[0033] For example, an out-of-band management module may include a management unit for the operating status of a computer device, a management system in a management chip outside the processor, a baseboard management controller (BMC), a system management mode (SMM), etc. It should be noted that the specific form of the out-of-band management module is not limited in the embodiments of this application; the above is merely an illustrative example. In the following embodiments, only a BMC is used as an example of an out-of-band management module for explanation.

[0034] The processor firmware can also be referred to as the processor firmware program. Specifically, processor firmware includes firmware, basic input / output system (BIOS), management engine (ME), microcode, or intelligent management unit (IMU), etc. It should be noted that the specific form of the processor firmware in this application is not limited; the above is merely illustrative. In the following embodiments, only the BIOS as the processor firmware is used as an example for explanation.

[0035] It should be noted that the management units or modules and firmware included in the out-of-band management modules and processor firmware mentioned above are only examples. In fact, some management units can also run as processor firmware programs in the computer. For example, the SMM can also provide business services to users and perform BIOS-related functions. Similarly, some processor firmware can also act as management units for non-business modules, such as the ME and IMU, and perform BMC-related functions.

[0036] Memory, also known as internal memory or main memory, is installed in memory slots on the motherboard of a computer device. Memory communicates with the memory controller via memory channels. Memory has at least one memory rank, each memory rank located on one face of the memory. Each memory rank includes at least one subrank. Each memory rank or subrank comprises multiple memory chips. Each memory chip is divided into multiple bankgroups. Each bankgroup comprises multiple banks. Each bank is divided into multiple cells. Each cell has a row address and a column address, and each cell includes one or more bits. That is, by specifying the row and column on the bankgroup, a cell can be located within the bankgroup. The smallest unit of memory failure is a cell within the bankgroup.

[0037] In this embodiment, a storage unit can be called a cache block. When a cache block occupies four bits, it can be called a half-byte entry; when it occupies eight bits, it can be called a byte entry. The row and column addresses of the storage unit indicate its location in memory. In one partitioning method, memory can be divided from upper to lower levels into memory chips, storage array groups, storage arrays, storage rows / columns, storage units (cache blocks), and bits. The addresses of memory chips, storage array groups, storage arrays, storage rows, storage columns, storage units (cache blocks), and bits in memory are the actual physical addresses. In another partitioning method, the central processing unit (CPU) divides the memory chip into multiple memory pages based on a paging mechanism. The addresses of these memory pages are virtual addresses, which need to be translated into actual physical addresses.

[0038] It should be noted that the system architecture and application scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0039] The method provided in this application embodiment can be applied to, but is not limited to, memory such as dynamic random access memory (DRAM) and static random access memory (SRAM). The method in this application embodiment does not limit the type of memory.

[0040] Currently, most computer processors support memory inspection and error correction, i.e., repairing memory faults. For example, each time a memory read / write task is performed, the processor uses error checking and correcting (ECC) methods to identify and repair memory faults. ECC is used to identify errors when a small number of bits in memory are faulty. Errors that can be corrected are called corrected errors (CE), or correctable faults. If the error exceeds the capability of the error correction algorithm, for example, when there are large areas of multi-bit faults in memory, error correction will fail, resulting in an uncorrected error (UCE), also known as an uncorrectable fault. When a UCE occurs, it can lead to serious system failures in the computer device, such as system crashes and data loss in memory.

[0041] To address this issue and repair faulty cache blocks in memory, this application provides a technique called PCLS (Computer-Generated Latent Memory Scrambling) that replaces faulty cache blocks. When the cache block is a nibble entry, the replacement cache block is called a nibble replacement entry. This replacement cache block is typically stored in the memory controller, and considering the cost of the memory controller, the number of replacement cache blocks is limited. For example, the number of replacement cache blocks for each memory channel is 16. Therefore, how to efficiently utilize the limited number of replacement cache blocks to repair memory faults is a pressing problem. It should be noted that this application does not limit the number of replacement cache blocks in the memory controller; the above is merely an illustrative example.

[0042] In some embodiments, such as Figure 2 As shown, follow the steps S201-S204 to repair memory faults using PCLS technology.

[0043] S201. When a fault occurs and the number of fault occurrences reaches a threshold, the fault repair process is triggered.

[0044] S202. Check if there are any free PCLS resources.

[0045] It is understood that the PCLS resource refers to the replacement cache block described above. An idle PCLS resource refers to a cache block that has not been used to repair faults.

[0046] S203. If there are idle PCLS resources, then execute the PCLS repair task.

[0047] Specifically, idle PCLS resources are used to replace faulty cache blocks.

[0048] If no free PCLS resources are available, the PCLS repair task will not be performed.

[0049] Understandably, when there are no free PCLS resources available to replace a faulty cache block, the faulty cache block cannot be repaired, which may then affect the system.

[0050] S204. Update the PCLS resource marker to indicate that it is in use.

[0051] The tag for a PCLS resource is used to indicate whether the resource has been used to repair a faulty cache block.

[0052] Steps S201-S204 above describe a basic scheme for repairing memory faults using PCLS technology. However, PCLS resources are usually limited. In the above scheme, once all PCLS resources are used, subsequent faulty cache blocks cannot be repaired. Obviously, the above method is not conducive to the rational use of repair resources.

[0053] In other embodiments, such as Figure 3 As shown, follow the steps S301-S306 to repair memory faults using PCLS technology.

[0054] S301. When a fault occurs and the number of fault occurrences reaches a threshold, the fault repair process is triggered.

[0055] S302. Check if there are any free PCLS resources.

[0056] S303. If there are idle PCLS resources, then execute the PCLS repair task.

[0057] S304. If there are no idle PCLS resources, reclaim the oldest PCLS resources and then perform the PCLS repair task.

[0058] The oldest PCLS resource refers to the earliest cache block used to repair faults among the occupied repair resources. For example, if replacement cache blocks a, b, and c are used to repair faults in chronological order, then replacement cache block a is the oldest PCLS resource.

[0059] In step S304 above, the oldest PCLS resource will be reclaimed to replace the currently faulty cache block.

[0060] S305. Update the PCLS resource marker to indicate that it is in use.

[0061] S306. Update the set of PCLS resources that have been used.

[0062] It is understandable that the used PCLS resource set includes multiple replacement cache blocks, each corresponding to a time of use, or arranged in the order of their use. When other cache blocks in memory fail subsequently, resources are reclaimed and repaired from the used PCLS resource set.

[0063] Steps S301-S306 above describe a scheme for memory fault repair by reclaiming PCLS resources using PCLS technology. However, the strategy for reclaiming PCLS resources in this scheme is determined based on the time order in which PCLS resources are used, and the method of using the cache block that was repaired first to repair the cache block that is currently faulty is also not conducive to the rational utilization of repair resources.

[0064] In view of this, in the following examples, embodiments of this application provide a memory fault handling method, which determines the fault severity of a target cache block based on fault information, and uses the fault severity to reclaim available repair resources from the used repair resources for the target cache block. This helps to solve the problem in the prior art that PCLS resources cannot be reclaimed to repair subsequent faulty cache blocks, and also helps to improve the utilization rate of PCLS resources and avoid the impact of cache blocks with high fault severity on the system.

[0065] like Figure 4 The diagram shown is a flowchart of a memory fault handling method provided in an embodiment of this application, including steps S401-S404.

[0066] S401, the out-of-band controller obtains memory fault information.

[0067] This fault information indicates that at least one cache block has failed. The fault information includes the location of the cache block in memory where the failure occurred. For example, the address information in memory used to indicate the storage unit.

[0068] Optionally, the fault information includes the fault occurrence time of the cache block. This fault occurrence time is used by the out-of-band controller to determine the frequency of the cache block's occurrence within a preset time period. For example, if the fault occurrence time is within the preset time period, the faults that occurred in the cache block at that time will be counted; if the fault occurrence time is not within the preset time period, the fault will not be counted.

[0069] It is understood that fault information is used to indicate basic information about the occurrence of a fault. The information contained in the above fault information is only an example and may include more or less information. This application does not limit this.

[0070] In the aforementioned related technologies, each time the memory performs a read / write task, the CPU performs fault detection on the memory based on the ECC method. If a fault is detected, the CPU corrects the detected error. In some embodiments, when the CPU detects a fault, it sends fault information of the faulty cache block to the out-of-band controller. Alternatively, when the CPU detects a fault, it reports the fault information of the faulty cache block to the processor firmware, which then forwards the fault information to the out-of-band controller. That is, the entity sending fault information to the out-of-band controller can be the CPU or the processor firmware; this application embodiment does not limit this. The following schemes are described using the CPU as an example.

[0071] In some embodiments, the out-of-band controller can periodically acquire memory fault information. This periodic acquisition of memory fault information can be achieved either by the out-of-band controller actively acquiring it from the CPU or processor firmware, or by the CPU or processor firmware periodically collecting memory fault information and then actively sending it to the out-of-band controller.

[0072] S402. The out-of-band controller determines whether the cache block is a single point of failure.

[0073] Optionally, the out-of-band controller determines whether the fault type of the cache block is a single point of failure based on the location information of the failure of at least one cache block. The out-of-band controller determines the fault type of at least one cache block based on the location information of the failure of at least one cache block, and identifies the cache block with the fault type of single point of failure as the target cache block.

[0074] Specifically, the out-of-band controller determines whether the target cache block is a single point of failure by checking whether its address information differs from that of other failed cache blocks. These other failed cache blocks include at least one cache block indicated in the fault information and historically failed cache blocks. Historically failed cache blocks refer to cache blocks that failed and were repaired before the target cache block failed. Determining whether the address information differs includes checking whether the row address of the target cache block differs from the row addresses of other failed cache blocks, and whether the column address of the target cache block differs from the column addresses of other failed cache blocks. If both the row address and column address of the target cache block differ from the row addresses of other failed cache blocks, the target cache block is determined to be a single point of failure.

[0075] Understandably, when multiple (e.g., two) cache blocks fail in the same row or column of memory, the out-of-band controller can diagnose that the storage row or column is likely to fail. In such cases, other technologies are needed to repair the storage row or column instead of using PCLS technology to replace the failed cache block.

[0076] In some embodiments, when the CPU sends fault information to the out-of-band controller, and the out-of-band management module determines that the fault type of the cache block is not a single point of failure based on the fault information, it can return the cache block fault information to the CPU. Alternatively, the out-of-band controller can feed back information that the cache block fault type is not a single point of failure to the CPU, so that the CPU can determine the repair method for the target cache block through other means.

[0077] Specifically, when the out-of-band controller determines that the cache block is a single point of failure, the cache block is the target cache block. The out-of-band controller determines to repair the target cache block based on PCLS technology and executes the following steps S403.

[0078] Step S402 is an optional step.

[0079] S403, The out-of-band controller determines the severity of the fault in the target cache block.

[0080] Optionally, the failure severity of the target cache block is used to indicate the probability that the failure of the target cache block will transition to a UCE.

[0081] In one example, the out-of-band controller can determine the severity of a target cache block's failure by counting the number of failures that occur. The number of failures is used to characterize the severity of the target cache block's failure.

[0082] Understandably, memory typically repairs a target cache block. If the repair is successful, the fault is marked as CE. If the cache block repeatedly fails and is repaired multiple times, in order to prevent the fault of the cache block from changing from CE to UCE, memory can consider using PCLS technology to replace the faulty cache block with a replacement cache block to solve the problem of repeated failures of the cache block.

[0083] Optionally, the out-of-band controller counts the number of failures within a preset time period based on the failure time of the target cache block; further, it determines the occurrence frequency of the target cache block based on the number of failures within the preset time period. Calculating the failure occurrence frequency helps identify failures that occur frequently within the preset time period, indicating higher severity within that period. For example, the preset time period refers to the time from startup of the server hosting the memory until it obtains fault information.

[0084] In one example, the out-of-band controller inputs fault information of the target cache block into the fault model and outputs the fault severity of the target cache block. This fault information includes one or more of the following: location information, fault occurrence time, and fault occurrence count.

[0085] The fault model is a pre-trained machine learning model. The training process involves iterative training using training samples and sample labels. The training samples include fault information from multiple memory locations, and the sample labels indicate the severity of the fault for each training sample. This fault training model can be an artificial intelligence (AI) fault training model.

[0086] In this embodiment, since the fault model is pre-trained, the severity of the fault in the target memory can be obtained by inputting the fault information of the target memory into the fault model. No user participation in calculation and data processing is required. This not only helps to improve the speed of fault prediction, but also avoids human error caused by user operation, thereby improving the accuracy of fault prediction results.

[0087] In some embodiments, the machine learning model may be a hierarchical thresholding algorithm, or one or more of the following machine learning algorithms: random forest, gradient boosting decision tree (GBDT), extreme gradient boosting (XGBoost), Naive Bayes, support vector machine (SVM); or one or more of the following deep learning algorithms: convolutional neural network (CNN), long short-term memory (LSTM); or one or more of the following federated learning optimization algorithms: federated averaging (FedAvg), FedProx, FedCS.

[0088] S404. The out-of-band controller determines the target replacement cache block based on the severity of the fault in the target cache block.

[0089] The target replacement cache block is used to replace the target cache block, which is the cache block that currently replaces the historical faulty cache block. The fault severity of the target cache block is greater than or equal to the fault severity of the historical faulty cache block.

[0090] Understandably, step S403 above is used to determine the severity of the faulty cache block before using PCLS technology to repair the fault. To this end, the severity of the target cache block's fault is compared with the severity of historical faulty cache blocks. If there exists a historical faulty cache block with a severity lower than that of the target cache block, the replacement cache block used to repair the historical faulty cache block with the lower severity can be reclaimed, and a target replacement cache block is determined to replace the target cache block. There may be multiple historical faulty cache blocks with a severity lower than that of the target cache block, and correspondingly, there may also be multiple reclaimable repair resources.

[0091] In one example, the out-of-band controller determines a priority sequence based on the severity of historical faulty cache blocks. Historical faulty cache blocks with higher fault severity have higher priority, and those with lower fault severity have lower priority. Further, the out-of-band controller compares the fault severity of a target cache block with this priority sequence to determine the target cache block's position within the priority sequence. A higher priority for the target cache block indicates a greater likelihood of it impacting the system, while a lower priority indicates a less likely impact.

[0092] Understandably, given the limited number of cache blocks that can be replaced, comparing the severity of the target cache block's failure with that of historically failed cache blocks helps to flexibly allocate the limited number of replacement cache blocks to repair cache blocks with higher failure severity, thereby minimizing the impact of the cache block on the system.

[0093] In one example, the out-of-band controller determines one or more historically failed cache blocks with a lower priority than the target cache block based on the severity of the target cache block's failure. Further, it determines the replacement cache block used by the one or more historically failed cache blocks. The out-of-band controller then determines a target replacement cache block from among the replacement cache blocks used by the one or more historically failed cache blocks. This target replacement cache block is used to repair the target cache block when no free replacement cache block is available.

[0094] In one example, the out-of-band controller identifies the historical fault cache block with the lowest fault severity among one or more historical fault cache blocks and uses the replacement cache block used by that historical fault cache block as the target replacement cache block.

[0095] Understandably, for a target cache block, the out-of-band controller determines a priority sequence by judging the severity of its fault and the severity of faults in historical faulty cache blocks. If the fault severity of the target cache block is high and all replacement cache blocks have been used to repair the faults of historical faulty cache blocks, the out-of-band controller reclaims the replacement cache block corresponding to the historical faulty cache block with the lowest fault severity in the priority sequence. The reclaimed replacement cache block becomes the target replacement cache block. If there are no free replacement cache blocks during the repair process, the target replacement cache block is used to repair the target cache block.

[0096] In one example, the out-of-band controller determines a recyclable identifier for a reclaimed replacement cache block, indicating that the replacement cache block is the target replacement cache block. Specifically, the recyclable identifier includes reclaimable and non-reclaimable, for example, represented by 0 and 1 respectively. Alternatively, the out-of-band controller determines a range of recyclable identifiers to indicate the number of replacement cache blocks in the repair resource. For example, if there are 16 replacement cache blocks, the range of recyclable identifiers is 0-15. When multiple reclaimable repair resources exist, the recyclable identifiers are determined as 0, 1, ..., n, where n ≤ 15, in ascending order of the severity of the faults corresponding to the multiple reclaimable repair resources.

[0097] By determining the available resources for the target cache block in the replacement cache block used by the historical faulty cache block, it is possible to repair the faulty cache block according to the severity of the fault. This helps to make reasonable use of limited repair resources to repair more serious faults and improve the utilization rate of memory fault repair resources.

[0098] Optionally, after step S404 above, the method further includes: S405, the out-of-band controller sends a repair request to the CPU, the repair request being used to request the CPU to perform fault repair on the target cache block.

[0099] The repair request carries the tag information of the target cache block to be replaced.

[0100] Optionally, the target replaces the tagging information of the cache block with the aforementioned recyclable identifier.

[0101] Optionally, the repair request may include the location of the fault in the target cache block, so that the CPU can be aware of the fault and perform repair.

[0102] It is understandable that the marking information of the target replacement cache block can be used by the CPU to determine the target replacement cache block based on the marking information when there are no free repair resources after receiving a repair request, and then use the target replacement cache block to repair the target cache block.

[0103] Accordingly, the CPU executes as follows Figure 5 The repair process shown includes:

[0104] S501, CPU receives repair request.

[0105] S502. The CPU checks if there are any idle repair resources. If yes, proceed to step S504; otherwise, proceed to step S503.

[0106] S503. The CPU determines whether there are recyclable and repairable resources; if yes, proceed to step S504; if no, proceed to step S505. Do not perform the PCLS repair task.

[0107] It is understandable that the above-mentioned recyclable repair resources are determined based on the comparison of the fault severity of the target cache block and the historical faulty cache block. When the fault severity of the target cache block is not greater than or equal to that of the historical faulty cache block, the out-of-band controller will not determine the recyclable repair resources. This indicates that the fault severity of the historical faulty cache block is high and is more likely to affect the system. Correspondingly, the fault severity of the target cache block is low, so PCLS repair can be temporarily suspended.

[0108] S504, the CPU repairs the target cache block.

[0109] Specifically, the CPU determines whether there is a free replacement cache block. If it does, it uses the free replacement cache block to repair the target cache block. If it does not, the CPU determines whether there is a reclaimable repair resource. If it does, it uses the replacement cache block corresponding to the reclaimable repair resource to repair the target cache block. If it does not, PCLS repair is not performed.

[0110] Understandably, a memory cache block failure prevents the CPU from reading or writing data to that cache block. The repair method involves replacing the target cache block with a replacement cache block. Specifically, this means adjusting the CPU's mapping relationship for processing the target cache block to the mapping relationship for processing the replacement cache block. This allows the CPU to subsequently read and write to the replacement cache block, thus repairing the memory failure. Specifically, this mapping relationship can be the location information of the cache block corresponding to the data read or written by the CPU.

[0111] Optionally, after the fault repair is completed as described above, the CPU sends the fault repair result back to the out-of-band controller. This fault repair result may indicate successful or unsuccessful repair.

[0112] It is understandable that during the repair process in step S504, there is a possibility of repair failure. The CPU feeds back the fault repair result to the out-of-band controller for the out-of-band controller to know. The out-of-band controller updates the correspondence between the replacement cache block and the faulty cache block according to the fault repair result.

[0113] In the first possible implementation, the CPU uses an idle replacement cache block to repair the target cache block. In this case, when the fault repair result indicates successful repair, the out-of-band controller saves the correspondence between the target cache block and the replacement cache block that replaced it. The fault repair result may also include the aforementioned fault information, such as location information, fault occurrence time, and fault severity.

[0114] It is understandable that the out-of-band controller saves the above correspondence so that when other cache blocks fail, if the severity of the failure is higher than that of the target cache block, the replacement cache block used to repair the target cache block can be used to repair the cache blocks that fail subsequently, that is, the correspondence will be modified accordingly.

[0115] In the second possible implementation, the CPU repairs the target cache block using the target replacement cache block. In this case, the repair result carries the tagging information of the target replacement cache block, and upon successful repair, the out-of-band controller updates the mapping between the target replacement cache block and the historical faulty cache block to a mapping between the target replacement cache block and the target cache block. The tagging information of the target replacement cache block can be the aforementioned recyclable identifier.

[0116] Understandably, when the repair result carries the tagging information of the target replacement cache block, it helps the out-of-band controller determine that the repair method for the target cache block uses that target replacement cache block. Accordingly, in the first possible implementation, although the out-of-band controller may send the tagging information (such as a recyclable flag) of the target replacement cache block to the CPU, since the CPU uses idle repair resources when repairing the target cache block, the repair result does not contain the tagging information of the target replacement cache block. Consequently, the correspondence between the target replacement cache block and the historically faulty cache block does not need to be modified.

[0117] The third possible implementation involves the CPU sending a fault repair result to the out-of-band controller. This fault repair result includes indication information, which indicates whether to use an idle replacement cache block for repair or to use reclaimable repair resources for repair.

[0118] Understandably, in this implementation, by instructing the out-of-band controller on the specific repair method, the out-of-band controller can update the correspondence between the used replacement cache block and the faulty cache block according to the repair method.

[0119] All three implementation methods described above help the out-of-band controller determine whether the target replacement cache block has been used to repair the target cache block and determine the update method.

[0120] Optionally, when the fault repair result indicates that the repair has failed, the out-of-band controller does not save the correspondence between the new replacement cache block and the target cache block or update the correspondence between the target replacement cache block and the historical fault cache block.

[0121] Optionally, the above fault repair result can also be sent by the CPU to the out-of-band controller after step S505 to indicate that the fault repair failed.

[0122] The above Figure 4 and Figure 5 The method performed can be applied to, for example Figure 6 The memory fault repair system shown includes at least an out-of-band controller and a CPU. It includes steps S601-S612.

[0123] S601, The processor reports fault information to the out-of-band controller.

[0124] Accordingly, the out-of-band controller receives the fault information, as described in step S401 above.

[0125] S602. Diagnose whether the out-of-band controller is a single point of failure.

[0126] As described in step S402 above.

[0127] S603. When the out-of-band controller is determined to be a single point of failure, determine the severity of the failure in the target cache block.

[0128] As described in step S403 above.

[0129] S604, out-of-band controller compares the severity of historical cache block faults.

[0130] As described in step S404 above.

[0131] S605. The out-of-band controller determines whether there is a historical faulty cache block whose fault severity is less than the current cache block's fault severity.

[0132] S606. When there is a historical faulty cache block with a fault severity less than the target cache block, determine the reclaimable and repairable resources.

[0133] The recyclable repair resource is the target replacement cache block described in step S404 above.

[0134] S607, the out-of-band controller sends a repair request to the CPU.

[0135] As described in step S405 above.

[0136] S608: The CPU checks whether there are any available repair resources based on the repair request.

[0137] As described in step S502 above.

[0138] S609. When there are available repair resources, execute the PCLS repair task.

[0139] As described in step S504 above.

[0140] S610. When there are no idle repair resources, determine whether there are recyclable repair resources.

[0141] As described in step S503 above.

[0142] If recyclable repair resources exist, perform the PCLS repair task.

[0143] S611. When there are no recyclable repair resources, the PCLS repair task is not executed.

[0144] S612, CPU reports fault repair results.

[0145] In the above scheme, the CPU is used to execute the repair action logic and the recycling action logic, while the out-of-band controller is used to execute the fault diagnosis logic and the recycling decision logic. Specifically, the repair action logic responds to hardware faults, reports fault information to the fault diagnosis logic, and processes the fault repair tasks issued by the diagnosis logic. The recycling action logic reclaims specified repair resources to complete subsequent repair tasks. The fault diagnosis logic receives reported fault information and identifies fault characteristics. The recycling decision logic calculates the fault severity based on the fault characteristics, sorts the resources according to severity to determine reclaimable repair resources, and issues fault repair tasks to the fault repair action logic.

[0146] By executing the above methods, the memory fault system allows the CPU and out-of-band controller to perform fault diagnosis and fault repair respectively. It determines available resources for the target cache block from the replacement cache blocks occupied by the historical faulty cache blocks. This helps to repair the cache blocks according to the severity of the faults, thereby helping to make reasonable use of limited repair resources to repair more serious faults and improve the utilization rate of memory fault repair resources.

[0147] The foregoing mainly describes the solutions of the embodiments of this application from a methodological perspective. It is understood that, in order to achieve the above-mentioned functions, the memory fault handling apparatus includes at least one of the hardware structures and software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0148] This application embodiment can divide the memory fault handling device into functional units according to the above method example. For example, each function can be divided into separate functional units, or two or more functions can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software functional unit. It should be noted that the unit division in this application embodiment is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods.

[0149] When dividing each function into modules according to its corresponding function. Figure 7 This diagram illustrates a possible structure of the memory fault handling device involved in the above embodiments. For example... Figure 7 As shown, the memory fault handling device 70 includes an acquisition unit 701, a processing unit 702, and a sending unit 703.

[0150] The acquisition unit 701 is used to acquire memory fault information, which indicates that at least one cache block has failed.

[0151] Processing unit 702 is used to determine the severity of a fault in a target cache block based on fault information, wherein the target cache block is one of at least one cache block.

[0152] The processing unit 702 is further configured to determine a target replacement cache block based on the fault severity of the target cache block; the target replacement cache block is used to replace the target cache block, and the target replacement cache block is the cache block that has currently replaced the historical faulty cache block, and the fault severity of the target cache block is greater than or equal to the fault severity of the historical faulty cache block.

[0153] The sending unit 703 is used to send a repair request to the CPU; the repair request is used to request the CPU to repair the target cache block, and the repair request carries the marking information of the target replacement cache block.

[0154] In one example, the processing unit 702 is specifically used to count the number of times a target cache block fails within a preset time period; wherein, the number of failures is used to characterize the severity of the failure of the target cache block, and the preset time period refers to the time period from the time the server where the memory is located to the time period since startup.

[0155] In one example, the processing unit 702 is specifically used to input the fault information of the target cache block into the fault model and output the fault severity of the target cache block; wherein, the fault model is used to determine the fault severity of the cache block based on the fault information of the cache block in memory.

[0156] In one example, the fault information includes location information of at least one cache block failing. The processing unit 702 is further configured to determine the fault type of at least one cache block based on the location information of at least one cache block failing; and to determine the cache block whose fault type is a single point of failure as the target cache block, wherein the row address of the target cache block is different from the row addresses of other cache blocks that have failed, and the column address of the target cache block is different from the column addresses of other cache blocks that have failed.

[0157] In one example, the target replacement cache block is the cache block that has currently replaced the historical faulty cache block with the least fault severity.

[0158] In one example, the acquisition unit 701 is further configured to receive the fault repair result of the target cache block sent by the CPU; when the fault repair result indicates successful repair, the processing unit 702 is further configured to save the correspondence between the target cache block and the replacement cache block that replaces the target cache block; when the fault repair result carries the marking information of the target replacement cache block and indicates successful repair, the processing unit is further configured to update the correspondence between the target replacement cache block and the historical faulty cache block to the correspondence between the target replacement cache block and the target cache block.

[0159] All relevant content of each step involved in the above method embodiments can be referenced from the functional description of the corresponding functional module, and will not be repeated here.

[0160] Of course, the memory fault handling device provided in this application embodiment includes, but is not limited to, the above-mentioned units, for example, it may also include storage unit 704.

[0161] Storage unit 704 can be used to store program code and data of the memory fault handling device.

[0162] This application also provides a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the methods executed by any of the computer devices described above.

[0163] For explanations of the relevant content and descriptions of the beneficial effects in any of the computer-readable storage media provided above, please refer to the corresponding embodiments described above, which will not be repeated here.

[0164] This application also provides a chip. This chip integrates a control circuit for implementing the functions of the aforementioned memory fault handling device and one or more ports. Optionally, the functions supported by this chip can be referred to above, and will not be repeated here. Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium. The aforementioned storage medium can be a read-only memory, random access memory, etc. The aforementioned processing unit or processor can be a central processing unit, a general-purpose processor, an application-specific integrated circuit (ASIC), a microprocessor (digital signal processor, DSP), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0165] This application also provides a computer program product containing instructions that, when executed on a computer, cause the computer to perform any of the methods described in the above embodiments. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions may be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access or may include one or more data storage devices such as servers or data centers that can be integrated with the medium. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., SSD), etc.

[0166] It should be noted that the devices for storing computer instructions or computer programs provided in the embodiments of this application, such as but not limited to the memory, computer-readable storage medium and communication chip, are all non-transitory.

[0167] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state disks, SSDs).

[0168] Although this application has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the accompanying drawings, the disclosure, and the appended claims, will understand and implement other variations of the disclosed embodiments in carrying out the claimed application. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0169] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. A memory fault handling method, characterized in that, The method includes: The out-of-band controller acquires memory fault information, which indicates that at least one cache block has failed; The out-of-band controller determines the severity of the fault in the target cache block based on the fault information, wherein the target cache block is one of the at least one cache blocks; The out-of-band controller determines a target replacement cache block based on the severity of the fault in the target cache block; the target replacement cache block is used to replace the target cache block, and the target replacement cache block is a cache block that has currently replaced a historically faulty cache block. The severity of the fault in the target cache block is greater than or equal to the severity of the fault in the historically faulty cache block; the historically faulty cache block refers to a cache block that failed and was repaired before the target cache block failed. The out-of-band controller sends a repair request to the central processing unit (CPU); the repair request is used to request the CPU to perform fault repair on the target cache block, and the repair request carries the marking information of the target replacement cache block.

2. The method according to claim 1, characterized in that, The out-of-band controller determines the severity of the fault in the target cache block based on the fault information, including: The number of failures of the target cache block within a preset time period is counted; wherein, the number of failures is used to characterize the severity of the failure of the target cache block, and the preset time period refers to the time period from the start of the server where the memory is located to the present.

3. The method according to claim 1 or 2, characterized in that, The out-of-band controller determines the severity of the fault in the target cache block based on the fault information, including: The fault information of the target cache block is input into the fault model, and the fault severity of the target cache block is output; wherein, the fault information includes at least one of location information, fault occurrence time, and fault occurrence number.

4. The method according to claim 1 or 2, characterized in that, The fault information includes location information of at least one cache block failure. Before the out-of-band controller determines the severity of the target cache block failure based on the fault information, the method further includes: Based on the location information of the failure of the at least one cache block, determine the failure type of the at least one cache block; The cache block whose fault type is a single point of failure is identified as the target cache block, wherein the row address of the target cache block is different from the row address of the other cache blocks that have failed, and the column address of the target cache block is different from the column address of the other cache blocks that have failed.

5. The method according to claim 1 or 2, characterized in that, The target replacement cache block is the cache block that has currently replaced the historical faulty cache block with the lowest fault severity.

6. The method according to claim 1 or 2, characterized in that, The method further includes: Receive the fault repair result of the target cache block sent by the CPU; When the fault repair result indicates successful repair, the out-of-band controller saves the correspondence between the target cache block and the replacement cache block that replaces the target cache block; When the fault repair result carries the tag information of the target replacement cache block and indicates that the repair was successful, the out-of-band controller updates the correspondence between the target replacement cache block and the historical fault cache block to the correspondence between the target replacement cache block and the target cache block.

7. A memory fault handling method, characterized in that, The method includes: The central processing unit (CPU) receives a repair request from the out-of-band controller. The repair request requests fault repair on a target cache block. The repair request carries a marker information for a target replacement cache block, which is a cache block that has currently replaced a historically faulty cache block. The fault severity of the target cache block is greater than or equal to the fault severity of the historically faulty cache block. The historically faulty cache block refers to a cache block that failed and was repaired before the target cache block failed. When a free replacement cache block exists, the CPU replaces the target cache block with the free replacement cache block based on the repair request; When no free replacement cache block exists, the CPU replaces the target cache block with the target replacement cache block based on the repair request.

8. The method according to claim 7, characterized in that, The method further includes: The CPU sends the fault repair result of the target cache block to the out-of-band controller; When the target cache block is replaced with an idle replacement cache block and the repair is successful, the information of the target cache block and the idle replacement cache block is sent to the out-of-band controller. When the target cache block is replaced with the target replacement cache block and the repair is successful, the tag information of the target replacement cache block is sent to the out-of-band controller.

9. A memory fault handling device, characterized in that, It includes a memory and a processor; the memory is used to store program code; the processor is used to invoke the program code to perform the method as described in any one of claims 1-8.

10. A memory fault handling device, characterized in that, It includes a memory and a processor; the memory is used to store program code; the processor is used to invoke the program code to perform the method as described in any one of claims 1-8.

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