Process method for ldmos devices

Abstract

The application discloses a process method of an LDMOS device, which comprises the following steps: first, forming a buried layer; etching and filling to form an STI; ion implantation to form a first deep well; forming a second well region in the active region by photoresist definition; forming a gate dielectric layer and a polysilicon layer; second, etching the polysilicon layer after photoresist definition to form a gate of the switch LDMOS device; third, re-coating photoresist to define a body region, opening a body region implantation window, and forming a body region of the switch LDMOS device by high-energy ion implantation; fourth, performing a modifying etching on the photoresist of the body region implantation window to expose the polysilicon gate; fifth, performing a low-energy ion implantation on the body region implantation window again, and then performing a thermal annealing activation; and sixth, depositing a dielectric layer and etching to form a side wall of the polysilicon gate. The body region is directly etched out, the problem of photoresist alignment is solved, and the influence of low photoresist data rate on etching effect is solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing, and in particular to a process method for an LDMOS device. Background Technology

[0002] LDMOS combines the high-voltage, high-current characteristics of discrete devices with the advantages of high-density intelligent logic control found in low-voltage integrated circuits. A single chip can accomplish functions that previously required multiple chips, significantly reducing area, lowering cost, and improving energy efficiency, aligning with the miniaturization, intelligence, and low-energy consumption trends of modern power electronic devices. Breakdown voltage and on-resistance are key parameters for evaluating high-voltage LDMOS devices. Therefore, to achieve the same breakdown voltage, R should be minimized. SP To enhance the competitiveness of the products.

[0003] In an existing LDMOS structure, such as Figure 1 As shown, the isolation region includes a buried layer and an N-type deep well. In this LDMOS structure, the P-type body region is formed using a self-aligned process, with the channel formed by self-alignment after etching polysilicon. The manufacturing process generally includes the following steps: forming an epitaxial layer on the substrate, followed by an N-type deep well; forming the active region, including the formation of the N-well and P-well and the implantation of the drift region; depositing the gate dielectric layer and polysilicon layer to complete the body region implantation activation; then etching to form the polysilicon gate structure; forming the gate sidewalls; completing the ion implantation of the source and drain regions; and completing the downstream processes, including contact holes and metal.

[0004] In actual production, it was found that when the clear ratio of the P-type body region is too small, the threshold voltage VT of the switching LDMOS device will fluctuate. Analysis suggests that the VT fluctuation may be related to polysilicon residue after etching the P-type body region, resulting in a failure to implant a large dose of low-energy aspartic acid (As). Several possible solutions are as follows:

[0005] 1. The module solves the etching process problem.

[0006] 2. Add dummy patterns to the P-type body region to increase the data ratio of the P-type body region and solve the problem of polysilicon etching residue.

[0007] 3. Increase the energy of As ion implantation. Summary of the Invention

[0008] The technical problem to be solved by this invention is to provide a process method for LDMOS devices to solve the problem of excessive threshold voltage fluctuation.

[0009] To solve the above problems, the present invention provides a process method for an LDMOS device, comprising:

[0010] The first step is to provide a semiconductor substrate, form an epitaxial layer on the semiconductor substrate, form a buried layer of the second conductive type in the epitaxial layer by ion implantation, etch the surface of the epitaxial layer and fill to form STI;

[0011] Form a first deep well of the second conductive type by ion implantation, and then perform thermal annealing to activate;

[0012] Form an active region in the epitaxial layer;

[0013] Form a second well region of the second conductive type in the active region by ion implantation through photoresist definition;

[0014] Form a gate dielectric layer on the surface of the epitaxial layer, and then deposit a polysilicon layer on the surface of the gate dielectric layer;

[0015] The second step is to etch the polysilicon layer after photoresist definition to form a gate of the switching LDMOS device;

[0016] The third step is to re-coat photoresist to define a body region, open a body region implantation window, and form a body region of the switching LDMOS device by high-energy ion implantation;

[0017] The fourth step is to perform a modified etching on the photoresist of the body region implantation window to expose the polysilicon gate;

[0018] The fifth step is to perform a low-energy ion implantation on the body region implantation window, and then perform thermal annealing to activate;

[0019] The sixth step is to deposit a dielectric layer and etch to form a side wall of the polysilicon gate.

[0020] Subsequently, perform a heavily doped ion implantation to form a source region, a drain region, a body region lead-out region and other structures of the LDMOS device, make a contact hole, and complete the device fabrication.

[0021] Further, in the first step, the first deep well is located below the STI and connected with the buried layer to form a basin-type isolation region.

[0022] Further, in the first step, for the switching LDMOS device, a step of forming a drift region of the second conductive type by ion implantation is further included in the epitaxial layer.

[0023] Further, in the fifth step, for the switching LDMOS device, a step of forming an LDD region by low-energy ion implantation can be further added.

[0024] Further, in the third step, the photoresist covering the polysilicon gate during body region implantation is not less than 0.1 um in range to prevent high-energy ion implantation from penetrating the polysilicon layer.

[0025] Further, in the fourth step, the photoresist covering the polysilicon gate in the body region implantation window is removed further by the modified etching, so that the polysilicon gate in the body region implantation window is exposed completely.

[0026] Further, in the fifth step, the low-energy implantation depth is less than the body region implantation depth, but the implantation range is greater than the body region, and the shielding area caused by the original photoresist covering the polysilicon gate is re-implanted in the low-energy implantation step.

[0027] Further, in the sixth step, the deposited dielectric layer is a silicon oxide layer or a silicon nitride layer, and the side wall is formed on both sides of the polysilicon gate after etching.

[0028] The process method of the LDMOS device provided by the application directly etches the body region, solves the problem of photoetching alignment, and solves the influence of low photoetching data rate on etching effect. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 is a cross-sectional structure diagram of an existing LDMOS device.

[0030] Figures 2-7 is a process step diagram of the application.

[0031] Figure 8 is a process flow diagram of the application.

[0032] BRIEF DESCRIPTION OF DRAWINGS

[0033] 1 is epitaxy, 2 is buried layer, 3 is first deep well, 4 is second well region, 5 is STI, 6 is drift region, 7 is polysilicon (gate), 8 is photoresist, 9 is body region, and 10 is side wall. DETAILED DESCRIPTION

[0034] The specific embodiments of the application are described below with reference to the accompanying drawings, which clearly and completely describe the technical solutions in the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments. The advantages and characteristics of the application will be more apparent according to the following description and claims. It should be noted that the drawings are very simplified and use non-precise ratios, which are only used for the purpose of conveniently and clearly assisting the description of the embodiments of the application. All other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0035] The application can be implemented in different forms and should not be interpreted as being limited to the embodiments presented herein. On the contrary, the embodiments are presented in order to make the disclosure complete and fully comprehensive and to convey the scope of the application to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions can be exaggerated for clarity, and the same reference numerals are used throughout the drawings to indicate the same elements. In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0036] In the conventional LDMOS device manufacturing process, when the body region clear ratio is too small, the threshold voltage VT of the switch LDMOS device will fluctuate. The VT fluctuation can be related to the polysilicon residue after body region etching, resulting in a large dose of As not being injected at low energy. Therefore, by accurately etching the body region and solving the problem of polysilicon residue, the stability of VT fluctuation is improved.

[0037] The present application relates to a process method of an LDMOS device, as shown in the figure, comprising the following steps: Figures 2-7

[0038] First, a semiconductor substrate is provided, and an epitaxial layer 1 is formed on the semiconductor substrate. The embodiments of the present application take a switch N-type LDMOS device as an example for illustration. An N-type buried layer 2 is formed in the epitaxial layer by ion implantation; then etching is performed on the surface of the epitaxial layer and filling is performed to form an STI. An N-type first deep well 3 is formed by ion implantation, and then heat annealing is performed for activation; the boundary of the first deep well is located below the STI and encloses the area between the two STIs, and the bottom is connected with the N-type buried layer, forming a basin-like isolation region.

[0039] An active region is formed in the epitaxial layer.

[0040] An N-type second well region 4 is formed in the active region by ion implantation through photoresist definition; the second well region 4 is located in the first deep well 3, and the range and junction depth thereof do not exceed those of the first deep well.

[0041] For a switch type device, N-type ion implantation can be performed in the isolation region formed by the first deep well and the buried layer to form a drift region 6.

[0042] ​A gate dielectric layer is formed on the epitaxial surface, and then a polysilicon layer 7 is deposited on the surface of the gate dielectric layer.

[0043] In the second step, the polysilicon layer 7 is etched after the photoresist is defined, and the gate of the switch LDMOS device is formed.

[0044] In the third step, the photoresist 8 is re-coated to define the body region, the body region implantation window is opened, and the body region 9 of the switch LDMOS device is formed by high-energy ion implantation. In the window of the body region, the photoresist needs to cover an area of about 0.1 um of the polysilicon gate, and the polysilicon gate is covered and wrapped. Therefore, the actually formed body region implantation window is smaller than the window defined by the polysilicon gate. The wrapping and protection of the photoresist on the polysilicon gate can prevent the high-energy implantation of the body region from penetrating the polysilicon gate.

[0045] In the fourth step, the photoresist of the body region implantation window is modified and etched, the photoresist wrapping the polysilicon gate in the edge area of the body region implantation window is removed, the polysilicon gate is exposed, and the body region implantation window is further expanded.

[0046] In the fifth step, low-energy ion implantation is performed on the body region implantation window, and then thermal annealing is performed for activation. The low-energy ion implantation can form a channel region along the boundary of the polysilicon gate. For the switch LDMOS device, an additional step of ion implantation can be added to form an LDD region.

[0047] In the sixth step, a dielectric layer such as a silicon oxide layer or a silicon nitride layer is deposited, and a side wall 10 of the polysilicon gate is etched.

[0048] Subsequent processes include heavy doping ion implantation and annealing activation to form source and drain contact regions, body region lead-out regions, and contact holes and front metal, which are conventional processes and are the same as existing processes, and thus will not be described in detail.

[0049] Compared with the traditional process, the body region etching is removed in the present application, the body region is etched directly when the polysilicon is etched, one step of photoresist stripping process is added after the high-energy implantation of the body region, and low-energy implantation is performed. The added step of photoresist stripping process can remove the etching residues and eliminate the influence of the non-straight photoresist topography. The polysilicon etching etches the body region, solves the alignment problem of photoetching, and solves the influence of the small data rate on etching. The large-dose non-implantation of N-type As does not occur, and the VT fluctuation is controlled.

[0050] The above is only a preferred embodiment of the present application and is not used to limit the present application. The present application can have various changes and variations for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A fabrication method for an LDMOS device, characterized in that: The first step involves providing a semiconductor substrate and forming an epitaxial layer on the semiconductor substrate; forming a buried layer of a second conductivity type in the epitaxial layer by ion implantation; and then etching and filling the surface of the epitaxial layer to form STI. A first deep well of the second conductivity type is formed by ion implantation; then it is activated by thermal annealing. An active region is formed in the epitaxial layer; A second well region of a second conductivity type is formed in the active region by ion implantation defined by photoresist; A gate dielectric layer is formed on the surface of the epitaxial layer, and then a polysilicon layer is deposited on the surface of the gate dielectric layer; The second step is to etch the polysilicon layer after the photoresist is defined to form the gate of the LDMOS device. The third step is to recoat the photoresist, define the body region, open the body region implantation window, and form the body region of the LDMOS device through high-energy ion implantation. When performing body region implantation, the photoresist should cover an area of ​​not less than 0.1um around the polysilicon gate to prevent high-energy ion implantation from penetrating the polysilicon layer. The fourth step is to perform a modifying etching on the photoresist of the injection window in the body region to expose the polysilicon gate. Modification etching further removes the photoresist covering the polysilicon gate within the body injection window, exposing the entire polysilicon gate within the body injection window. The fifth step is to perform low-energy ion implantation on the implantation window of the body region, followed by thermal annealing activation. The low-energy implantation depth is less than the implantation depth of the body region, but the implantation range is greater than that of the body region. The masking area caused by the original photoresist covering the polysilicon gate is re-implanted in the low-energy implantation step. Step 6: Deposit a dielectric layer and etch to form the sidewalls of the polysilicon gate; The seventh step is to perform heavily doped ion implantation to form the source region, drain region, and body lead-out region of the LDMOS device. Contact holes and metal interconnects are formed to create the final MOS device.

2. The process method for the LDMOS device as described in claim 1, characterized in that: In the first step, the first deep pit is located below the STI and is connected to the buried layer to form a basin-shaped isolation area.

3. The process method for the LDMOS device as described in claim 1, characterized in that: In the first step, for a switching LDMOS device, the epitaxial layer further includes a step of forming a drift region of a second conductivity type by ion implantation.

4. The process method for the LDMOS device as described in claim 1, characterized in that: In the fifth step, for switching LDMOS devices, an additional low-energy ion implantation step can be performed to form the LDD region.

5. The process method for the LDMOS device as described in claim 1, characterized in that: In the sixth step, the deposited dielectric layer is a silicon oxide layer or a silicon nitride layer, and after etching, sidewalls are formed on both sides of the polysilicon gate.

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