A process improvement technology for compound semiconductor wafers

Abstract

The present invention relates to the field of wafer processing technology, and discloses an improved process for manufacturing compound semiconductor wafers. The process comprises the following steps: S1, completing a front-end crystallization process of the wafer; S2, temporarily bonding the wafer to a glass carrier; S3, thinning the back surface and manufacturing a back component process; S4, placing the back surface on a first carrier and removing the glass carrier; S5, completing the fixation of the wafer edge with a deposit and performing a high-temperature tempering process to activate ions and a front surface process; S6, bonding the front surface of the wafer to a second carrier and removing the first carrier on the front surface; S7, continuing the process on the back surface of the wafer; S8, performing a cutting process; S9, attaching the cut crystals to a cutting mold frame, removing the third carrier, and completing the wafer processing. The present invention adopts a four-step bonding technology, and after passing through a temporarily bonded glass carrier, the front and back surface processes are performed simultaneously, simplifying the operation steps and reducing the operational difficulty.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer processing, in particular to an improved processing technology for compound semiconductor wafers. Background Art

[0002] Semiconductor materials are categorized into two types: elemental semiconductors, such as silicon (Si) and germanium (Ge), and compound semiconductors, which are formed from compounds like gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC). Semiconductors have undergone three generations of evolution, with gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC) representing the second and third generations, respectively.

[0003] The prior art discloses CN202110284168.X, a processing technology for compound semiconductor wafers, which utilizes bonding (double) technology to fully utilize various small-sized compound semiconductor substrates to integrate large-sized silicon-based carriers and back-end processes, greatly improving production efficiency, and can utilize existing Si (silicon-based) production lines for small-sized compound semiconductor substrates.

[0004] However, the back of the wafer that has completed all the back processes is bonded to a glass carrier for subsequent front processes. The permanent bonding operation on the front is complicated and the removal operation is troublesome. In addition, the back operation is completed before the front process, resulting in the need to protect the components on the back during the front process, which makes subsequent operations inconvenient. Summary of the Invention

[0005] The object of the present invention is to provide an improved process for manufacturing compound semiconductor wafers to solve the problems in the prior art.

[0006] The purpose of the present invention can be achieved through the following technical solutions:

[0007] A process improvement technology for compound semiconductor wafers, the process comprising the following steps:

[0008] S1. Complete the front-end crystal process of small-sized compound semiconductor substrates, including gate, oxide layer and gate, ion implantation and tempering processes;

[0009] S2, depositing an ILD layer on the front side of the compound semiconductor substrate and temporarily bonding it to a glass carrier;

[0010] S3, flipping the glass carrier, grinding and etching the back side of the compound semiconductor substrate to thin it, and making the back side component process;

[0011] S4, turning over the compound semiconductor substrate, placing the back side on the first carrier, and then removing the glass carrier;

[0012] S5. Filling the front surface of the compound semiconductor substrate with deposits using a CVD process, partially removing the deposits on the compound semiconductor substrate, then performing a high-temperature annealing process to activate ions, and then performing a front surface process;

[0013] S6, bonding the front side of the compound semiconductor substrate in S5 to the second carrier, flipping the compound semiconductor substrate over, and removing the first carrier on the front side;

[0014] S7, continuing the process on the back side of the wafer;

[0015] S8, performing a cutting process to form grains;

[0016] S9. Attach the cut crystals to the cutting mold frame and lift up the metal in the gaps to complete the processing of the compound semiconductor substrate for subsequent packaging and testing support.

[0017] Furthermore, the ion implantation temperature in S1 is 400-800°C, and the tempering process temperature is 1200-1600°C.

[0018] Furthermore, the back surface component process in S3 includes photoresist coating, exposure, development, ion implantation, and photoresist removal.

[0019] Furthermore, the deposit includes silicon dioxide and silicon oxynitride.

[0020] Furthermore, in S5 , the deposits at the edge of the wafer are retained to fix the compound semiconductor substrate on the first carrier.

[0021] Furthermore, the first carrier plate, the second carrier plate, and the third carrier plate are all high-temperature resistant and transparent carrier plates.

[0022] Furthermore, the front process in S5 includes manufacturing front contact windows, metal wiring, passivation layers and chemical plating and electroplating processes.

[0023] Furthermore, the process technology in S7 includes: first coating polyimide on the compound semiconductor substrate, then removing the polyimide above the compound semiconductor substrate to leak out above the wafer, leaving the polyimide at the edge to fix the wafer, and then performing metal deposition, chemical plating and electroplating processes on the back of the compound semiconductor substrate, and completing the heating process to form an alloy of metal and compound semiconductor.

[0024] Furthermore, the cutting process in S8 is performed as follows:

[0025] The back of the wafer is attached to the cutting template, the second carrier on the front is flipped over and removed, and the metal in the gap is lifted up. Then, a diamond wheel, laser or plasma etching is used to cut the compound semiconductor wafer to form grains, ensuring that there is no metal connection between the edge of the compound semiconductor substrate and the metal in the gap area.

[0026] Beneficial effects of the present invention:

[0027] 1. The present invention improves the processing technology and adopts a four-step bonding technology to promptly remove the glass carrier plate of the first temporary bonding, and then performs the front process and the high-temperature tempering process on the back, thereby avoiding damage to the glass carrier plate. In addition, only the wafer needs to be cut during cutting, which is easy to operate and can directly obtain the grains.

[0028] 2. The present invention improves the processing technology and adopts the method of simultaneous front and back processing to improve the processing stability, protect the process components of the wafer, and facilitate the temporary bonding and removal of the glass carrier. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present invention will be further described below with reference to the accompanying drawings.

[0030] Figure 1 It is a schematic diagram of the process flow of S1 and S2 of the present invention;

[0031] Figure 2 It is a schematic diagram of the process flow of S3 and S4 of the present invention;

[0032] Figure 3 Schematic diagram of the process flow of S5 of the present invention;

[0033] Figure 4 It is a schematic diagram of the process flow of S6 and S7 of the present invention;

[0034] Figure 5 It is a schematic diagram of the process flow of S8 and S9 of the present invention.

[0035] The reference numerals are as follows:

[0036] 1. Compound semiconductor substrate; 2. Glass carrier; 3. First carrier; 4. Sediment; 5. Second carrier; 6. Cutting mold frame; 7. Polyimide. DETAILED DESCRIPTION

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0038] Example 1

[0039] A process improvement technology for compound semiconductor wafers, the process comprising the following steps:

[0040] S1, such as Figure 1 As shown, the front-end crystal process of the small-sized compound semiconductor substrate 1 is completed, including the gate, oxide layer and gate, ion implantation and tempering process, the ion implantation temperature is 400°C, and the tempering process temperature is 1600°C.

[0041] S2 , depositing an ILD layer 11 on the front side of the compound semiconductor substrate 1 and then temporarily bonding the substrate to the glass carrier 2 .

[0042] S3, such as Figure 2 As shown, the glass carrier 2 is flipped over so that the back side of the small-sized compound semiconductor substrate 1 faces upward, and the wafer is ground and etched to be thinned, and the back-side component manufacturing process includes photoresist coating, exposure, development, ion implantation, and photoresist removal.

[0043] S4, turning over the compound semiconductor substrate 1, placing the back side on the first high-temperature resistant and transparent carrier plate 3, then debonding and peeling off the glass carrier plate 2 on the front side, and removing the adhesive on the front side.

[0044] S5, such as Figure 3 As shown, a CVD process is used to fill a deposit 4 on the front side of a compound semiconductor substrate 1. The deposit 4 includes silicon dioxide and silicon oxynitride. The deposit 4 on the compound semiconductor substrate 1 is partially removed, leaving the deposit 4 located at the edge of the compound semiconductor substrate 1. The compound semiconductor substrate 1 is fixed on a first carrier 3, and a high-temperature annealing process is performed to activate ions. Then, a front process is performed, including the production of a front contact window, metal wiring, a passivation layer, and a chemical plating and electroplating process.

[0045] In this embodiment, the carrier plate is replaced in S4 and S5 because the glass carrier plate cannot withstand the high temperature of the high temperature tempering process.

[0046] S6, such as Figure 4 As shown, after completing the high-temperature tempering process and the front process, the front side of the compound semiconductor substrate 1 is adsorbed on the high-temperature resistant and transparent second carrier 5, the back side of the compound semiconductor substrate 1 is turned over to face up, and the first carrier 3 on the back side is debonded and removed.

[0047] In this embodiment, laser is emitted from below the second carrier 5 to perform circular cutting on the edge of the compound semiconductor substrate 1 to remove the wafer edge and the deposits 4 on the edge, and then the first carrier 3 is removed.

[0048] S7. Coat polyimide 7 on the compound semiconductor substrate 1, then remove the polyimide 7 above the compound semiconductor substrate 1 until it leaks out above the wafer, leaving the polyimide 7 at the edge to fix the wafer, and then perform back metal deposition and electroless plating processes on the compound semiconductor substrate 1, and complete the heating process to form an alloy of metal and compound semiconductor.

[0049] S8, such as Figure 5 As shown, the back of the wafer is attached to the cutting mold frame 6, the second carrier 5 and polyimide 7 on the front are turned over and removed, and the metal in the gap is lifted up together, and then the cutting process is performed to form grains, ensuring that there is no metal at the edge of the compound semiconductor substrate 1 connected to the metal in the gap area.

[0050] The cutting process described in this embodiment uses a diamond wheel, laser or plasma etching to cut the compound semiconductor wafer.

[0051] S9 , attaching the cut dies to the cutting mold frame 6 , completing the processing of the compound semiconductor substrate 1 , and performing subsequent packaging and test support.

[0052] Example 2

[0053] A process improvement technology for compound semiconductor wafers, the process comprising the following steps:

[0054] S1, such as Figure 1 As shown, the front-end crystal process of a small-sized compound semiconductor substrate 1 is completed, including the gate, oxide layer and gate, ion implantation and tempering process. The ion implantation temperature is 800°C and the tempering process temperature is 1200°C.

[0055] S2 , depositing an ILD layer 11 on the front side of the compound semiconductor substrate 1 and then temporarily bonding the substrate to the glass carrier 2 .

[0056] S3, such as Figure 2 As shown, the glass carrier 2 is flipped over so that the back side of the small-sized compound semiconductor substrate 1 faces upward, and the wafer is ground and etched to be thinned, and the back-side component manufacturing process includes photoresist coating, exposure, development, ion implantation, and photoresist removal.

[0057] S4, turning over the compound semiconductor substrate 1, placing the back side on the first high-temperature resistant and transparent carrier plate 3, then debonding and peeling off the glass carrier plate 2 on the front side, and removing the adhesive on the front side.

[0058] S5, such as Figure 3As shown, a CVD process is used to fill a deposit 4 on the front side of a compound semiconductor substrate 1. The deposit 4 includes silicon dioxide and silicon oxynitride. The deposit 4 on the compound semiconductor substrate 1 is partially removed, leaving the deposit 4 located at the edge of the compound semiconductor substrate 1. The compound semiconductor substrate 1 is fixed on a first carrier 3, and a high-temperature annealing process is performed to activate ions. Then, a front process is performed, including the production of a front contact window, metal wiring, a passivation layer, and a chemical plating and electroplating process.

[0059] In this embodiment, the carrier plate is replaced in S4 and S5 because the glass carrier plate cannot withstand the high temperature of the high temperature tempering process.

[0060] S6, such as Figure 4 As shown, after completing the high-temperature tempering process and the front process, the front side of the compound semiconductor substrate 1 is adsorbed on the high-temperature resistant and transparent second carrier 5, the back side of the compound semiconductor substrate 1 is turned over to face up, and the first carrier 3 on the back side is debonded and removed.

[0061] In this embodiment, laser is emitted from below the second carrier 5 to perform circular cutting on the edge of the compound semiconductor substrate 1 to remove the wafer edge and the deposits 4 on the edge, and then the first carrier 3 is removed.

[0062] S7. Coat polyimide 7 on the compound semiconductor substrate 1, then remove the polyimide 7 above the compound semiconductor substrate 1 until it leaks out above the wafer, leaving the polyimide 7 at the edge to fix the wafer, and then perform back metal deposition and electroless plating processes on the compound semiconductor substrate 1, and complete the heating process to form an alloy of metal and compound semiconductor.

[0063] S8, such as Figure 5 As shown, the back of the wafer is attached to the cutting mold frame 6, the second carrier 5 and polyimide 7 on the front are turned over and removed, and the metal in the gap is lifted up together, and then the cutting process is performed to form grains, ensuring that there is no metal at the edge of the compound semiconductor substrate 1 connected to the metal in the gap area.

[0064] The cutting process described in this embodiment uses a diamond wheel, laser or plasma etching to cut the compound semiconductor wafer.

[0065] S9 , attaching the cut dies to the cutting mold frame 6 , completing the processing of the compound semiconductor substrate 1 , and performing subsequent packaging and test support.

[0066] Example 3

[0067] A process improvement technology for compound semiconductor wafers, the process comprising the following steps:

[0068] S1, such as Figure 1As shown, the front-end crystal process of the small-sized compound semiconductor substrate 1 is completed, including the gate, oxide layer and gate, ion implantation and tempering process, the ion implantation temperature is 600°C, and the tempering process temperature is 1400°C.

[0069] S2 , depositing an ILD layer 11 on the front side of the compound semiconductor substrate 1 and then temporarily bonding the substrate to the glass carrier 2 .

[0070] S3, such as Figure 2 As shown, the glass carrier 2 is flipped over so that the back side of the small-sized compound semiconductor substrate 1 faces upward, and the wafer is ground and etched to be thinned, and the back-side component manufacturing process includes photoresist coating, exposure, development, ion implantation, and photoresist removal.

[0071] S4, turning over the compound semiconductor substrate 1, placing the back side on the first high-temperature resistant and transparent carrier plate 3, then debonding and peeling off the glass carrier plate 2 on the front side, and removing the adhesive on the front side.

[0072] S5, such as Figure 3 As shown, a CVD process is used to fill a deposit 4 on the front side of a compound semiconductor substrate 1. The deposit 4 includes silicon dioxide and silicon oxynitride. The deposit 4 on the compound semiconductor substrate 1 is partially removed, leaving the deposit 4 located at the edge of the compound semiconductor substrate 1. The compound semiconductor substrate 1 is fixed on a first carrier 3, and a high-temperature annealing process is performed to activate ions. Then, a front process is performed, including the production of a front contact window, metal wiring, a passivation layer, and a chemical plating and electroplating process.

[0073] In this embodiment, the carrier plate is replaced in S4 and S5 because the glass carrier plate cannot withstand the high temperature of the high temperature tempering process.

[0074] S6, such as Figure 4 As shown, after completing the high-temperature tempering process and the front process, the front side of the compound semiconductor substrate 1 is adsorbed on the high-temperature resistant and transparent second carrier 5, the back side of the compound semiconductor substrate 1 is turned over to face up, and the first carrier 3 on the back side is debonded and removed.

[0075] In this embodiment, laser is emitted from below the second carrier 5 to perform circular cutting on the edge of the compound semiconductor substrate 1 to remove the wafer edge and the deposits 4 on the edge, and then the first carrier 3 is removed.

[0076] S7. Coat polyimide 7 on the compound semiconductor substrate 1, then remove the polyimide 7 above the compound semiconductor substrate 1 until it leaks out above the wafer, leaving the polyimide 7 at the edge to fix the wafer, and then perform back metal deposition and electroless plating processes on the compound semiconductor substrate 1, and complete the heating process to form an alloy of metal and compound semiconductor.

[0077] S8, such as Figure 5As shown, the back of the wafer is attached to the cutting mold frame 6, the second carrier 5 and polyimide 7 on the front are turned over and removed, and the metal in the gap is lifted up together, and then the cutting process is performed to form grains, ensuring that there is no metal at the edge of the compound semiconductor substrate 1 connected to the metal in the gap area.

[0078] The cutting process described in this embodiment uses a diamond wheel, laser or plasma etching to cut the compound semiconductor wafer.

[0079] S9 , attaching the cut dies to the cutting mold frame 6 , completing the processing of the compound semiconductor substrate 1 , and performing subsequent packaging and test support.

[0080] In the improved processing technology of this embodiment, S2 does not need to permanently bond the compound semiconductor substrate 1 to the glass carrier 2, which simplifies the subsequent operation of removing the glass carrier 2; at the same time, the glass carrier 2 is removed in S4, and the compound semiconductor substrate 1 is bonded to a high-temperature resistant and transparent carrier, avoiding the temperature of the high-temperature tempering activation ion process to melt the glass carrier 2, thereby improving production safety.

[0081] Throughout this specification, references to terms such as "one embodiment," "example," or "specific example" indicate that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, schematic representations of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0082] The basic principles, main features, and advantages of the present invention are shown and described above. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely illustrative of the principles of the present invention. Various changes and modifications may be made to the present invention without departing from the spirit and scope of the present invention, and such changes and modifications fall within the scope of the invention as claimed.

Claims

1. A process improvement technology for compound semiconductor wafers, characterized in that: The processing technology comprises the following steps: S1. Complete the front-end crystal process of small-sized compound semiconductor substrate (1), including gate, oxide layer and gate, ion implantation and tempering process; S2, depositing an ILD layer (11) on the front side of the compound semiconductor substrate (1) and temporarily bonding the substrate to the glass carrier (2); S3, turning over the glass carrier (2), grinding, etching and thinning the back side of the compound semiconductor substrate (1), and manufacturing a back side component process; The backside component process in S3 includes photoresist coating, exposure, development, ion implantation, and photoresist removal; S4, turning over the compound semiconductor substrate (1), placing the back side on the first carrier (3), and then removing the glass carrier (2); S5, filling the deposit (4) on the front side of the compound semiconductor substrate (1) using a CVD process, partially removing the deposit (4) on the compound semiconductor substrate (1), then performing a high-temperature tempering process to activate ions, and then performing a front side process; S6, bonding the front side of the compound semiconductor substrate (1) in S5 to the second carrier (5), flipping the compound semiconductor substrate (1), and removing the first carrier (3) on the back side; S7, continuing the process on the back side of the wafer; The process in S7 includes: first coating polyimide (7) on the compound semiconductor substrate (1), then removing the polyimide (7) above the compound semiconductor substrate (1) until it leaks out above the wafer, leaving the polyimide (7) at the edge to fix the wafer, then performing metal deposition and electroless plating processes on the back of the compound semiconductor substrate (1), and completing a heating process to form an alloy of the metal and the compound semiconductor; S8, performing a cutting process to form grains; The cutting process is performed as follows: The back of the wafer is attached to the cutting mold frame (6), the second carrier (5) on the front is turned over and removed, and the metal in the gap is lifted up, and then the compound semiconductor wafer is cut using a diamond wheel, laser or plasma etching to form grains, ensuring that no metal at the edge of the compound semiconductor substrate (1) is connected to the metal in the gap area; S9, completing the processing of the compound semiconductor substrate (1) and providing subsequent packaging and testing support; The first carrier plate (3) and the second carrier plate (5) are both high-temperature resistant and transparent carrier plates.

2. The process improvement process for compound semiconductor wafers according to claim 1, characterized in that: In the S1, the ion implantation temperature is 400-800°C, and the tempering process temperature is 1200-1600°C.

3. The process improvement technology for compound semiconductor wafer according to claim 1, characterized in that: The sediment (4) includes silicon dioxide and silicon oxynitride.

4. The process improvement process for compound semiconductor wafers according to claim 1, characterized in that: In the step S5, the deposit (4) at the edge of the wafer is retained to fix the compound semiconductor substrate (1) on the first carrier (3).

5. The process improvement technology for compound semiconductor wafer according to claim 1, characterized in that: The front side process in S5 includes manufacturing the front side contact window, metal wiring, passivation layer and chemical plating and electroplating process.

Images