Stacked package structure and method for manufacturing stacked package structure

Abstract

The embodiment of the present disclosure provides a kind of stacked package structure and the manufacturing method of stacked package structure, stacked package structure includes: substrate and the multiple chips of being stacked on substrate arrangement, wherein, chip includes opposite first face and second face, second face is provided with device layer, and there is conductive via in chip through chip;First conductive part and second conductive part, first conductive part and second conductive part are all set to first face, and first conductive part contacts conductive via;Thermal conductive part, thermal conductive part is set to first face, and contacts second conductive part;First solder part, between adjacent chip, and with first conductive part contact, to electrically connect adjacent chip;Second solder part, between adjacent chip, and with second conductive part contact;Wherein, first solder part, second solder part is located on the device layer surface of second face.This embodiment of the present disclosure is at least advantageous to improve the bonding success rate of second solder part, to improve the reliability of stacked package structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a stacked packaging structure and a method for manufacturing the stacked packaging structure. Background Technology

[0002] With the development of semiconductor technology, semiconductor devices are becoming increasingly integrated and multifunctional. Existing 2D packaging can hardly meet the technical requirements, while 3D packaging, with its small size and light weight, can meet the needs of semiconductor technology development and is widely used. Bonding is a key process for realizing 3D packaging. Among the bonding technologies currently used in 3D packaging, thermal compression bonding (TCB) is one of them. When using thermal compression bonding to stack semiconductor device layers, when the number of stacked layers is relatively low, the temperature conduction of thermal compression bonding is more uniform, and the bonding effect is relatively good. When the number of stacked layers is relatively high, the temperature conduction of thermal compression bonding is uneven, and the bonding effect is poor.

[0003] Therefore, the performance of stacked packaging structures still needs improvement. Summary of the Invention

[0004] This disclosure provides a stacked packaging structure and a method for manufacturing the stacked packaging structure, which at least helps to solve the problem of partial chip bonding failure when bonding multilayer chips.

[0005] According to some embodiments of this disclosure, one aspect of this disclosure provides a stacked packaging structure, including: a substrate and a plurality of chips stacked on the substrate, wherein each chip includes a first side and a second side facing each other, the second side having a device layer, and the chip having a conductive via penetrating the chip; a first conductive portion and a second conductive portion, both the first conductive portion and the second conductive portion being disposed on the first side, and the first conductive portion contacting the conductive via; a heat-conducting portion, the heat-conducting portion being disposed on the first side and contacting the second conductive portion; a first solder portion, located between adjacent chips, and the first solder portion contacting the first conductive portion to electrically connect the adjacent chips; a second solder portion, located between adjacent chips, and the second solder portion contacting the second conductive portion; wherein the first solder portion and the second solder portion are located on the surface of the device layer on the second side of the chip.

[0006] In some embodiments, the heat-conducting portion is disposed around the edge of the first surface, and the heat-conducting portion includes a first end and a second end located at both ends, with the first end adjacent to the second end.

[0007] In some embodiments, the heat-conducting portion includes: a plurality of straight portions arranged at intervals; a plurality of bent portions, each of the bent portions being connected between adjacent straight portions, and the bent portions being bent toward an edge closer to the first surface.

[0008] In some embodiments, the bending shape of the bent portion includes a zigzag shape or an arc shape.

[0009] In some embodiments, the first surface of the same chip has a plurality of second conductive portions, and the same heat-conducting portion is in contact with the plurality of second conductive portions.

[0010] In some embodiments, the material of the heat-conducting part includes a metallic material that provides resistance heating.

[0011] In some embodiments, the material of the first conductive portion is the same as the material of the second conductive portion.

[0012] In some embodiments, the device layer is disposed on the surface of the substrate facing the chip, and the first conductive portion and the second conductive portion are also located on the surface of the substrate facing the chip; the thermally conductive portion is also located on the surface of the substrate facing the chip and contacts the second conductive portion on the substrate; the first solder portion is also located between the substrate and the chip adjacent to the substrate, and contacts the first conductive portion on the substrate and the device layer adjacent to the substrate to electrically connect the substrate and the chip; the second initial solder portion is also located between the substrate and the chip adjacent to the substrate, and contacts the second conductive portion on the substrate and the device layer adjacent to the substrate.

[0013] In some embodiments, the material of the first solder portion is the same as the material of the second solder portion.

[0014] In some embodiments, the substrate and the chip are provided with a plurality of through holes, which penetrate the substrate, the chip and the device layer.

[0015] In some embodiments, the second side of each chip is provided with a plurality of device layers.

[0016] According to some embodiments of this disclosure, another aspect of this disclosure provides a method for manufacturing a stacked package structure, comprising: providing a substrate and a plurality of chips stacked on the substrate, wherein the chips have opposing first and second surfaces, a device layer is formed on the second surface, and conductive vias penetrating the chips are formed within the chips; forming a first conductive portion and a second conductive portion on the first surface, wherein the first conductive portion is in contact with the conductive vias; forming a thermally conductive portion located on the first surface and in contact with the second conductive portion; forming a first initial solder portion and a second initial solder portion between adjacent chips, wherein the first initial solder portion is in contact with the first conductive portion and the device layer, and the second initial solder portion is in contact with the second conductive portion and the device layer; performing a bonding process to transform the first initial solder portion into a first solder portion fixed to the first conductive portion and the device layer, and to transform the second initial solder portion into a second solder portion fixed to the second conductive portion and the device layer, wherein in the bonding process step, current is supplied to the thermally conductive portion to generate heat in the thermally conductive portion.

[0017] In some embodiments, the process for forming the thermally conductive portion is the same as the process for forming the first conductive portion and the second conductive portion.

[0018] In some embodiments, the method further includes: forming a first conductive portion and a second conductive portion on the surface of the substrate facing the chip; forming a thermally conductive portion on the surface of the substrate facing the chip, wherein the thermally conductive portion contacts the second conductive portion on the substrate; forming a first initial solder portion and a second initial solder portion between the substrate and the chip adjacent to the substrate, wherein the first initial solder portion contacts the first conductive portion on the substrate and the device layer adjacent to the substrate, and the second solder portion contacts the second conductive portion on the substrate and the device layer adjacent to the substrate.

[0019] In some embodiments, a first chip, a second chip, a third chip, and a fourth chip are sequentially stacked on the substrate, wherein, in the bonding process, the heat generated by the heat-conducting portion on the first chip is greater than the heat generated by the heat-conducting portion on the second chip, and the heat generated by the heat-conducting portion on the second chip is greater than the heat generated by the heat-conducting portion on the third chip.

[0020] The technical solutions provided in this disclosure have at least the following advantages:

[0021] In the stacked packaging structure provided in this embodiment, multiple chips are stacked on a substrate. The multiple chips have opposing first and second surfaces. A device layer is provided on the second surface, and a first conductive portion and a second conductive portion are provided on the first surface. The chip also has a conductive via penetrating the chip. A first solder portion contacts the conductive via, and the first conductive portion contacts the first solder portion to electrically connect adjacent chips. The second conductive portion contacts the second solder portion. Therefore, when the semiconductor structure is bonded, the conductive via allows the bonding heat to be conducted to the first solder bonding portion relatively quickly compared to the second solder portion. A heat-conducting portion is also provided on the first surface, and the heat-conducting portion contacts the second conductive portion to generate heat and conduct it to the second conductive portion. This balances the heat difference between the first and second solder portions, increases the bonding power of the solder portions, reduces the bonding morphology difference between the first and second solder portions, and improves the performance and yield of the formed semiconductor structure. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A cross-sectional schematic diagram of a stacked packaging structure;

[0024] Figure 2 This is a cross-sectional view of a stacked packaging structure provided in an embodiment of the present disclosure;

[0025] Figure 3 This is a top view of a chip in a stacked packaging structure according to an embodiment of the present disclosure;

[0026] Figure 4 This is a top view of a chip in another stacked packaging structure provided in an embodiment of the present disclosure;

[0027] Figure 5 This is a top view of a chip in another stacked packaging structure provided in an embodiment of the present disclosure;

[0028] Figure 6 This is a top view of a chip in another stacked packaging structure provided in an embodiment of the present disclosure;

[0029] Figure 7A top view of a chip in a stacked packaging structure provided in an embodiment of this disclosure;

[0030] Figure 8 and Figure 9 This is a cross-sectional view of each step in a method for manufacturing a stacked packaging structure according to another embodiment of this disclosure. Detailed Implementation

[0031] As can be seen from the background technology, the performance of stacked packaging structures still needs to be improved.

[0032] The performance of stacked packaging structures is closely related to their structure. (Reference) Figure 1 , Figure 1 This is a cross-sectional view of a stacked packaging structure 100. The stacked packaging structure 100 includes: a substrate 101, and a plurality of chips 102 stacked on the substrate 101. Each chip 102 includes a first surface 102a and a second surface 102b, the second surface 102b having a device layer 103, and each chip 102 having a conductive via 104 penetrating the chip 102; a first connection portion 105 located between adjacent chips 102, and the first connection portion 105 contacting the conductive via 104 to electrically connect the adjacent chips 102; and a second connection portion 106 located between adjacent chips 102.

[0033] During the formation of the stacked package structure 100, bonding heads (not shown) are positioned above all chips 102. Bonding heat is conducted from the chip 102 closest to the bonding head to the substrate 101. When the first connection portion 105 is bonded, heat is directly conducted to the first connection portion 105 through the conductive via 104. When the second connection portion 106 is bonded, heat is conducted sequentially through the adjacent chip 102 and the device layer 103 on the adjacent chip 102 to the second connection portion 106. Thus, the thermal resistance of the heat transfer path of the first connection portion 105 is less than that of the heat transfer path of the second connection portion 106, and the heat conduction speed of the first connection portion 105 is higher than that of the second connection portion 106. Therefore, in the same bonding time, the first connection portion 105 receives more heat than the second connection portion 106. For example, when the number of stacked layers of chip 102 is small, the difference between the heat obtained by the first connection portion 105 and the heat obtained by the second connection portion 106 is relatively small, and the difference between the heat obtained by the connection portion adjacent to the substrate 101 and the heat obtained by the connection portion far from the substrate 101 is relatively small. As a result, the bonding effect between adjacent chips 102 and the bonding effect between chip 102 and substrate 101 is relatively good. When the number of stacked layers of chip 102 is large, the difference between the heat obtained by the first connection portion 105 and the heat obtained by the second connection portion 106 is relatively large, and the difference between the heat obtained by the connection portion adjacent to the substrate 101 and the heat obtained by the connection portion far from the substrate 102 is relatively large. This can easily lead to the problem that the first connection portion 105 and the second connection portion 106 in the chip 102 adjacent to the substrate 101 fail to bond, or the first connection portion 105 bonds successfully while the second connection portion 106 fails to bond.

[0034] This disclosure provides a stacked packaging structure, which includes a substrate and a plurality of chips disposed on the substrate. Each chip has a conductive via penetrating the chip. Each chip includes a first side and a second side facing each other. A device layer is disposed on the second side. A first solder portion and a second solder portion are disposed between adjacent chips. A first conductive portion, a second conductive portion, and a heat-conducting portion are disposed on the first side. The first conductive portion and the first solder portion are electrically connected to the adjacent chips. The second conductive portion is in contact with the second solder portion, and the heat-conducting portion is in contact with the second conductive portion. The heat-conducting portion is used to generate heat and conduct it to the second conductive portion. As a result, during the bonding process, the temperature difference between the first solder portion and the second solder portion is small, the contact between the bonded second solder portion and the second conductive portion is stronger, and the morphological difference between the bonded first solder portion and the second solder portion is smaller, thereby improving the performance of the stacked packaging structure.

[0035] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0036] Figure 2 This is a cross-sectional view of a stacked packaging structure provided in one embodiment of the present disclosure. Figure 3 This is a top view of a chip in a stacked packaging structure according to an embodiment of the present disclosure. Figure 4 This is a top view of a chip in another stacked packaging structure provided in an embodiment of the present disclosure. Figure 5 This is a top view of a chip in another stacked packaging structure provided in an embodiment of the present disclosure. Figure 6 This is a top view of a chip in another stacked packaging structure provided in an embodiment of the present disclosure. Figure 7 This is a top view of a chip in another stacked packaging structure provided in an embodiment of the present disclosure.

[0037] refer to Figure 2 The stacked package structure 200 includes: a substrate 201 and a plurality of chips 202 stacked on the substrate 201, wherein each chip 202 includes a first surface 202a and a second surface 202b opposite to each other, the second surface 202b is provided with a device layer 203, and each chip 202 has a conductive via 204 penetrating the chip 202; a first conductive portion 205 and a second conductive portion 206, both the first conductive portion 205 and the second conductive portion 206 are disposed on the first surface 202a, and the first conductive portion 205 is connected to the conductive via 204. The device layer 205 is located on the first surface 202a and contacts the second conductive part 206. A first solder part 208 is located between adjacent chips 202 and contacts the first conductive part 205 to electrically connect the adjacent chips 202. A second solder part 209 is located between adjacent chips 202 and contacts the second conductive part 206. The first solder part 208 and the second solder part 209 are located on the surface of the device layer 203 on the second surface 202b.

[0038] It is understandable that, since the bonding head (not shown) is located above all chips 202 and contacts the chip 202 furthest from the substrate 201, during the formation of the stacked package structure 200, the heat generated by the bonding head is conducted from the chip 202 furthest from the substrate 201 toward the substrate 201. Because the two ends of the conductive via 204 are in contact with the first solder portion 208 and the first conductive portion 205 respectively, heat is directly conducted to the first solder portion 208 through adjacent conductive vias 204 and adjacent first conductive portions 205. The second solder portion 209 receives heat through the conduction of adjacent chips 202, adjacent device layers 203, and the second conductive portion 206. The thermal resistance of the thermal conduction path of the first solder portion 208 is less than the thermal resistance of the thermal conduction path of the second solder portion 209. Within the same bonding time, the heat provided by the bonding head is greater for the first solder section 208 than for the second solder section 209. Since the heat-conducting section 207 is in contact with the second conductive section 206, and the second conductive section 206 is in contact with the second solder section 209, the heat generated by the heat-conducting section 207 is sequentially conducted to the second conductive section 206 and the second solder section 209 during the bonding process. In this way, the heat generated by the heat-conducting section 207 can compensate for the heat difference between the second solder section 209 and the first solder section 208 during bonding. As a result, the contact between the second solder section 209 and the adjacent chip 202 and the second conductive section 206 is more stable, and the morphological difference between the first solder section 208 and the second solder section 209 is smaller. The performance and yield of the stacked package structure 200 are improved.

[0039] The stacked package structure 200 may include a memory package structure, which may be a dynamic random access memory (DRAM) package structure, a static random access memory (SRAM) package structure, or a magnetoresistive random access memory (MRAM) package structure.

[0040] The substrate 201 can be a printed circuit board (PCB), a flexible substrate, or a strip substrate, etc. In some embodiments, the substrate 201 can also be a multi-circuit board having through holes and various circuit elements. In other embodiments, the substrate 201 can also be a carrier board for carrying the chip 202 and the solder section.

[0041] In some embodiments, the plurality of chips 202 may be chips 201 of the same type, and each chip 202 may be a memory chip, such as a dynamic random access memory (DRAM), static random access memory (SRAM), or magnetoresistive random access memory (MRAM). In other embodiments, the plurality of chips 202 may include chips 201 of different types. For example, some of the plurality of chips 202 may be logic chips, while others may be memory chips. For example, each of the logic chips may be a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP). In other embodiments, the substrate 201 and the chips 202 may each have a plurality of vias, which penetrate the substrate 201, the chips 202, and the device layer 203. The device layer 203 may be a redistribution layer, and the vias may be filled with conductive material. The vias can electrically connect each chip 202 and the substrate 201 through wires.

[0042] The conductive via 204 can penetrate the device layer 203 located on the chip 202 and the second surface 202b, and the conductive via 204 contacts the first conductive part 205, which in turn contacts the first solder part 208, so as to electrically connect each chip 202.

[0043] The material of the first conductive part 205 and the material of the second conductive part 206 can be the same. The materials of both the first conductive part 205 and the second conductive part 206 can be metals such as copper, gold, or aluminum. It is understood that in other embodiments, the materials of the first conductive part 205 and the second conductive part 206 can be different.

[0044] The material of the first solder section 208 and the material of the second solder section 209 can be the same, so that the melting temperature of the first solder section 208 and the melting temperature of the second solder section 209 are the same. The material type of the first solder section 208 and the material type of the second solder section 209 can be tin-copper, lead-copper, tin-silver-copper, tin-silver-copper, tin-lead-copper, or tin-bismuth-copper, etc.

[0045] It is understood that in some other embodiments, the materials of the first solder portion 208 and the second solder portion 209 may also be different. The first solder portion 208 may be made of a material with a melting temperature greater than that of the second solder connection portion 209. This is to accommodate the phenomenon that the heat conducted from the bonding head to the first solder portion 208 is greater than the heat conducted to the second solder portion 209 during the formation of the first solder portion 208 and the second solder portion 209. This reduces the morphological difference between the formed first solder portion 208 and the second solder portion 209 and reduces the amount of heat that the heat-conducting part 207 needs to supply to form the second solder portion 209 during the formation of the stacked package structure 200, thus saving costs.

[0046] The first solder section 208 may include a first solder 210 and a first conductive bump 211. The first solder 210 is disposed between the first conductive bump 211 and the first conductive portion 205. The first conductive bump 211 is disposed on the surface of the device layer 203 located on the second surface 202b. The first solder 210 connects the first conductive portion 205 and the first conductive bump 211. The material of the first solder 210 may be tin, lead, tin-silver, tin-silver-copper, tin-lead, or tin-bismuth, etc., and the material of the first conductive bump 211 may be copper.

[0047] The second solder portion 209 may include a second solder 212 and a second conductive bump 213. The second solder 212 is disposed between the second conductive portion 206 and the second conductive bump 213, and the second conductive bump 213 is disposed on the surface of the device layer 203 located on the second surface 202b. The material of the second solder 212 may be tin, lead, tin-silver, tin-silver-copper, tin-lead, or tin-bismuth, etc., and the material of the second conductive bump 213 may be copper.

[0048] In some embodiments, the material of the first solder 210 and the material of the second solder 212 may be the same, such as tin, lead, tin-silver, tin-silver-copper, tin-lead or tin-bismuth, etc.

[0049] In some embodiments, the material of the first conductive bump 211 and the material of the second conductive bump 213 may be the same, for example, copper.

[0050] refer to Figures 3 to 6 The heat-conducting part 207 is disposed around the edge of the first surface 202a. The heat-conducting part 207 may include a first end 207a and a second end 207b located at the beginning and end ends, and the first end 207a and the second end 207b are adjacent to each other.

[0051] Specifically, refer to Figure 3The heat-conducting portion 207 of the same layer can be disposed around all solder portions of the same layer. Compared to the solder portions of the same layer, the heat-conducting portion 207 is located at the edge of the first surface 202a to avoid the heat-conducting portion 207 affecting the arrangement of the solder portions. On the other hand, the heat-conducting portion 207 of the same layer can be square, having length and width, and the two ends of the heat-conducting portion 207 can have opposing first ends 207a and second ends 207b. During the formation of the stacked package structure 200, the first ends 207a and second ends 207b can contact the probes of the current source device (not shown) so that the heat-conducting portion 207 can obtain current and generate resistance heat, assisting the bonding of the second solder portion 209 and the second conductive portion 206, thereby improving the bonding power of the second solder portion 209 and the second conductive portion 206 and improving the reliability of the formed stacked package structure 200. The material of the heat-conducting portion 207 can include a metal material that provides resistance heat, and the metal material can be at least one of silver, copper, nickel, aluminum or cobalt.

[0052] It is understandable that the heat-conducting part 207 in the same layer can also be segmented, with each segment of the heat-conducting part 207 having a first end 207a and a second end 207b, as shown in the reference. Figure 4 In some specific embodiments, the heat-conducting portion 207 of the same layer may have a first heat-conducting portion 217 and a second heat-conducting portion 218, wherein the first heat-conducting portion 217 and the second heat-conducting portion 218 have relative openings, and both the first heat-conducting portion 217 and the second heat-conducting portion 218 have a first end 207a and a second end 207b, and the first ends 207a of the first heat-conducting portion 217 and the second heat-conducting portion 218 are adjacent, and the second ends 207b of the first heat-conducting portion 217 and the second heat-conducting portion 218 are adjacent, so that during the formation of the stacked package structure 200, for the solder portion of the same layer, the heat difference obtained by the second solder portion 209 in different regions by the heat-conducting portion 207 is small, thereby reducing the morphological differences of the multiple second solder portions 209 formed.

[0053] refer to Figure 5 The heat-conducting part 207 may also include a plurality of straight sections 214 spaced apart and a plurality of bent sections 215, wherein each bent section 215 is connected between adjacent straight sections 214 and the bent section 215 bends toward the edge near the first surface 202a. With this arrangement, the heat-conducting part 207 has a larger resistance value, so that the heat-conducting part 207 can generate more heat.

[0054] The bending shape of the bending portion 215 can be a zigzag shape to give the heat-conducting portion 207 a higher resistance value, thereby allowing the heat-conducting portion 207 to provide more heat. (Reference) Figure 5 In some embodiments, the bending shape of the bend 215 can be a zigzag shape with square protrusions; see reference. Figure 6In other embodiments, the bending shape of the bending portion 215 can be a zigzag shape with a "V" shaped protrusion.

[0055] Referring to 7, the bending shape of the bending portion 215 can also be arc-shaped, so that the heat-conducting portion 207 has a larger resistance value, thereby the heat-conducting portion 207 can generate more heat.

[0056] In some embodiments, the heat-conducting part 207 may further include a connecting part 216, through which the heat-conducting part 207 contacts the second conductive part 206.

[0057] The first surface 202a of the same chip 202 may have multiple second conductive parts 206, and the same heat-conducting part 207 is in contact with multiple second conductive parts 206.

[0058] In some embodiments, the first conductive part 205 may be disposed in the middle region of the first surface 202a, and the second conductive part 206 may be disposed in the edge region of the first surface 202a, with the second conductive part 206 disposed adjacent to the heat-conducting part 207. In some embodiments, the first conductive part 205 may be disposed in the middle region of the first surface 202a, and the second conductive part 206 may be located in the edge region of the first surface 202a relative to the position of the first conductive part 205. All second conductive parts 206 may be disposed between the heat-conducting part 207 and the first conductive part 205, with the second conductive part 206 close to the heat-conducting part 207.

[0059] In some specific embodiments, on the first surface 202a of the same chip 202, the second conductive part 206 may include a plurality of third conductive parts 206a and a plurality of fourth conductive parts 206b. The third conductive parts 206a are all disposed between the first conductive part 205 and the fourth conductive parts 206b. The third conductive parts 206a are in contact with the conductive part 207 through the connecting part 216, and the fourth conductive parts 206b are in contact with the third conductive parts 206a through the connecting part 216.

[0060] It is understandable that on the first surface 202a of the same chip 202, the heat-conducting part 207 can also directly contact all the second conductive parts 206.

[0061] In some specific embodiments, the first conductive part 205 can be disposed in the middle region of the first surface 202a3, and the second conductive part 206 is disposed in the edge region of the first surface 202a, relative to the position of the first conductive part 205. Some of the second conductive parts 206 can be disposed on the side of the heat-conducting part 207 close to the first conductive part 205, and the remaining second conductive parts 206 can be disposed on the side of the heat-conducting part 207 away from the first conductive part 205. All the second conductive parts 206 are disposed close to the heat-conducting part 207. In this way, the material used for the contact part between the second conductive part 206 and the heat-conducting part 207 can be reduced, thus saving costs.

[0062] It is also understood that the first conductive part 205 may not be provided in the middle region of the first surface 202a, and the second conductive part 206 may not be provided in the edge region of the first surface 202a. Each pair of conductive parts provided on the device layer 203 may include one first conductive part 205 and one second conductive part 206, and the heat-conducting part 207 contacts the second conductive part 206.

[0063] In some embodiments, the second surface 202b of each chip 202 may be provided with multiple device layers 203, wherein the multiple device layers 203, the first solder part 208 and the second solder part 209 on the same chip 202 may be located on the surface of the device layer 203 farthest from the second surface 202b.

[0064] The first conductive portion 205 and the second conductive portion 206 may also be located on the surface of the substrate 201 facing the chip 202; the heat-conducting portion 207 may also be located on the surface of the substrate 201 facing the chip 202 and contact the second conductive portion 206 on the substrate 201; the first solder portion 208 may also be located between the substrate 201 and the chip 202 adjacent to the substrate 201, and contact the first conductive portion 205 on the substrate 201 and the device layer 203 adjacent to the substrate 201 to electrically connect the substrate 201 and the chip 202; the second solder portion 209 may also be located between the substrate 201 and the chip 202 adjacent to the substrate 201, and contact the second conductive portion 206 on the substrate 201 and the device layer 203 adjacent to the substrate 201. This configuration allows the substrate 201 and the chip 202 to be connected via a solder section. Due to the presence of the heat-conducting section 207, the heat generated by the heat-conducting section 207 participates in the bonding process of the second solder section 209 during bonding, thereby making the contact between the second solder section 209 and the second conductive section 206 more stable and improving the reliability of the stacked package structure 200.

[0065] The stacked packaging structure 200 provided in this embodiment includes a first solder portion 208 and a second solder portion 209 disposed between a substrate 201 and a chip 202. The chip 202 has a conductive via 204 penetrating the chip 202. A device layer 203 is disposed on the second surface 202b of the chip 202. A first conductive portion 205, a second conductive portion 206, and a heat-conducting portion 207 are disposed on the first surface 202a. The first conductive portion 205 is connected to the first solder portion 208, and the first solder portion 208 is connected to the conductive via 204 to electrically connect adjacent chips 202. The second solder portion 209 is in contact with the heat-conducting portion 207. During the bonding process, the heat-conducting portion 207 generates heat and conducts it to the second conductive portion 206, assisting the second conductive portion 206 and the second solder portion 209 in bonding. As a result, the second solder portion 209 and the second conductive portion 206 have good bonding stability, which is beneficial to improving the reliability of the stacked packaging structure 200.

[0066] Accordingly, another embodiment of this disclosure also provides a method for manufacturing a stacked packaging structure. This method can be used to form the stacked packaging structure provided in the foregoing embodiment. The semiconductor structure provided in another embodiment of this disclosure will be described in detail below with reference to the accompanying drawings. For the parts that are the same as or corresponding to the previous embodiment, please refer to the corresponding description of the foregoing embodiment. They will not be described in detail below. Figure 8 and Figure 9 This is a cross-sectional view of each step in a method for manufacturing a stacked packaging structure according to another embodiment of this disclosure.

[0067] refer to Figure 8 A substrate 201 is provided on which a plurality of chips 202 are stacked. Each chip 202 may have a first surface 202a and a second surface 202b opposite to each other. A device layer 203 is formed on the second surface 202b. A conductive via 204 is formed in the chip 202.

[0068] Multiple through holes can be formed in the substrate 201 and the chip 202, and the through holes penetrate the substrate 201, the chip 202 and the device layer 203 on the chip 202.

[0069] A first conductive portion 205 and a second conductive portion 206 may be formed on the first surface 202a, and the first conductive portion 205 is in contact with the conductive through hole 204; a heat-conducting portion 207 is formed, which is located on the first surface 202a and is in contact with the second conductive portion 206.

[0070] Specifically, the process for forming the heat-conducting part 207 is the same as the process for forming the first conductive part 205 and the second conductive part 206. That is, the heat-conducting part 207, the first conductive part 205 and the second conductive part 206 are formed in the same process. The process for forming the first conductive part 205 and the second conductive part 206 can be a plasma sputtering process, a vapor deposition process or an electroplating process.

[0071] A first initial solder portion 301 and a second initial solder portion 302 can be formed between adjacent chips 202. The first initial solder portion 301 is in contact with the first conductive portion 205 and the device layer 203, and the second initial solder portion 302 is in contact with the second conductive portion 206 and the device layer 203.

[0072] Specifically, the first initial solder portion 301 may include a first initial solder 303 and a first conductive bump 211. The first initial solder 303 is formed between the first conductive portion 205 and the first conductive bump 211. The first conductive bump 211 is formed on the surface of the device layer 203 on the second surface 202b and contacts the conductive via 204. The second initial solder portion 302 may include a second initial solder 304 and a second conductive bump 213. The second initial solder 304 is formed between the second conductive portion 206 and the second initial conductive bump 213. The second conductive bump 213 is formed on the surface of the device layer 203 on the second surface 202b.

[0073] In some embodiments, a first conductive portion 205 and a second conductive portion 206 are formed on the surface of the device layer 203 on the substrate 201; a thermally conductive portion 207 is formed on the surface of the substrate 201 facing the chip 202, and the thermally conductive portion 207 contacts the second conductive portion 206 on the substrate 201; a first initial solder portion 301 and a second initial solder portion 302 are formed between the substrate 201 and the chip 202 adjacent to the substrate 201. The first initial solder portion 301 contacts the first conductive portion 205 on the substrate 201 and the device layer 203 adjacent to the substrate 201, and the second initial solder portion 302 contacts the second conductive portion 206 on the substrate 201 and the device layer 203 adjacent to the substrate 201, so that after subsequent bonding processing, the substrate 201 and the chip 202 can be fixedly connected, increasing the reliability of the formed stacked package structure 200.

[0074] refer to Figure 9A bonding process 11 is performed to transform the first initial solder portion 301 into a first solder portion 208 fixed to the first conductive portion 205 and the device layer 203, and to transform the second initial solder portion 302 into a second solder portion 209 fixed to the second conductive portion 206 and the device layer 203. During the bonding process 11, current is supplied to the heat-conducting portion 207 to generate heat. Thus, the heat generated by the heat-conducting portion 207 assists in the bonding of the second initial solder portion 302 to the second conductive portion 206 and the device layer 203, thereby improving the bonding success rate of the second initial solder portion 302 and reducing the morphological difference between the formed second solder portion 209 and the first solder portion 208, which is beneficial for improving the performance of the stacked package structure.

[0075] A bonding head 305 can be disposed above all the chips 202. The bonding head 305 is connected to the chips 202 through a first conductive part 205 and a second conductive part 206. Thus, in the bonding process 11 steps, the heat generated by the bonding head 305 is conducted from the chip 202 adjacent to the bonding head 305 to the substrate 201. Some heat is lost during the conduction process. Thus, the heat generated by the bonding head 305 gradually decreases from the heat obtained by the chip 202 adjacent to the bonding head 305 to the heat obtained by the substrate 201 during the conduction process.

[0076] It is understandable that, since the first initial solder section 301 is in contact with the conductive via 204, during the bonding process 11, the first initial solder section 301 directly receives heat from the bonding head 305 through the adjacent first conductive section 205 and the adjacent conductive via 204, while the second initial solder section 302 receives heat from the bonding head 305 through conduction through the adjacent chip 202, the adjacent device layer 203, and the adjacent second conductive section 206. The thermal resistance of the heat transfer path of the first initial solder section 301 is less than the thermal resistance of the heat transfer path of the second initial solder section 302. Therefore, in the same bonding time, the heat received by the first initial solder section 301 is greater than the heat received by the second initial solder section 302 from the heat provided by the bonding head 305.

[0077] A heat-conducting portion 207 is disposed around the edge of the first surface 202a of the chip 202. The heat-conducting portion 207 may include a first end 207a and a second end 207b at its two ends, with the first end 207a and the second end 207b adjacent to each other. During the bonding process 11, a current source device (not shown) is provided to conduct current to the heat-conducting portion 207. The current source device has a first type of probe (not shown) and a second type of probe (not shown). The first type of probe is connected to the positive terminal of the current source device, and the second type of probe is connected to the negative terminal of the current source device. The first end 207a and the second end 207b contact the first type of probe and the second type of probe, respectively, so that the heat-conducting part 207 obtains current through the probe and generates resistance heat. The resistance heat generated by the heat-conducting part 207 is conducted to the second initial solder part 302 to reduce the portion of the heat provided by the bonding head 305 where the heat obtained by the second initial solder part 302 is less than the heat obtained by the first initial solder part 301. This increases the success rate of the second initial solder part 302 converting into the second solder part 209, thereby improving the reliability and yield of the stacked package structure.

[0078] In some embodiments, a first chip, a second chip, a third chip, and a fourth chip may be sequentially stacked on the substrate 201. During the bonding process 11, the heat generated by the heat-conducting portion 207 on the first chip is greater than the heat generated by the heat-conducting portion 207 on the second chip, and the heat generated by the heat-conducting portion 207 on the second chip is greater than the heat generated by the heat-conducting portion 207 on the third chip. This arrangement accommodates the phenomenon that the heat provided by the bonding head 305 is lost during conduction. Depending on the different amounts of heat received by the solder portions in different layers, the heat-conducting portion 207 provides different amounts of heat. This ensures that the second initial solder portion 302, which receives less heat from the bonding head 305, receives relatively more heat, while the second initial solder portion 302, which receives more heat from the bonding head 305, receives relatively less heat. This not only improves the bonding success rate of all second initial solder joints 302 but also ensures that the morphological differences among all formed solder portions are not significant.

[0079] This disclosure provides a method for manufacturing a stacked package structure 200. A heat-conducting portion 207 is formed on a first surface 202a, and the heat-conducting portion 207 contacts a second conductive portion 206. During the bonding process 11, the heat-conducting portion 207 generates heat and conducts it to the second conductive portion 206, assisting the second conductive portion 206 in bonding with the second initial solder portion 302 and the device layer 203. This reduces the difference between the heat conducted to the second initial solder portion 302 and the first initial solder portion 301 within the same bonding time provided by the bonding head 303, thereby improving the bonding success rate of the second initial solder portion 302 and reducing the morphological difference between the formed first solder portion 205 and the second solder portion 206, which is beneficial to improving the reliability of the stacked package structure 200.

[0080] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A stacked packaging structure, characterized in that, include: A substrate and a plurality of chips stacked on the substrate, wherein the chips include opposing first and second surfaces, the second surface is provided with a device layer, and the chips have conductive vias penetrating the chips. A first conductive part and a second conductive part are both disposed on the surface of the first surface, and the first conductive part is in contact with the conductive through hole; A heat-conducting part is disposed on the first surface and contacts the second conductive part; the heat-conducting part is used to provide resistance heat. A first solder section is located between adjacent chips, and the first solder section is in contact with the first conductive section to electrically connect the adjacent chips. The second solder section is located between adjacent chips and is in contact with the second conductive section; The first solder portion and the second solder portion are located on the surface of the device layer on the second surface.

2. The stacked packaging structure as described in claim 1, characterized in that, The heat-conducting part is disposed around the edge of the first surface, and the heat-conducting part includes a first end and a second end located at both ends, with the first end and the second end being adjacent to each other.

3. The stacked packaging structure as described in claim 1, characterized in that, The heat-conducting part includes: a plurality of straight sections arranged at intervals; a plurality of bent sections, each of the bent sections being connected between adjacent straight sections, and the bent sections being bent toward the edge of the first surface.

4. The stacked packaging structure as described in claim 3, characterized in that, The bending shape of the bending portion includes a broken line or an arc.

5. The stacked packaging structure as described in claim 1, characterized in that, The first surface of the same chip has a plurality of second conductive portions, and the same heat-conducting portion is in contact with the plurality of second conductive portions.

6. The stacked packaging structure as described in claim 1, characterized in that, The material of the heat-conducting part includes a metallic material that provides resistance heating.

7. The stacked packaging structure as described in claim 1, characterized in that, The material of the first conductive part is the same as the material of the second conductive part.

8. The stacked packaging structure as described in claim 1, characterized in that, The first conductive portion and the second conductive portion are also located on the surface of the substrate facing the chip; the thermally conductive portion is also located on the surface of the substrate facing the chip and contacts the second conductive portion on the substrate; the first solder portion is also located between the substrate and the chip adjacent to the substrate, and contacts the first conductive portion on the substrate and the device layer adjacent to the substrate to electrically connect the substrate and the chip; the second solder portion is also located between the substrate and the chip adjacent to the substrate, and contacts the second conductive portion on the substrate and the device layer adjacent to the substrate.

9. The stacked packaging structure as described in claim 1, characterized in that, The material of the first solder part is the same as the material of the second solder part.

10. The stacked packaging structure as described in claim 1, characterized in that, The substrate and the chip are provided with a plurality of through holes, which penetrate the substrate, the chip and the device layer.

11. The stacked packaging structure as described in claim 1, characterized in that, Each of the chips has a plurality of device layers on its second side, wherein the plurality of device layers, the first solder portion and the second solder portion on the same chip are located on the surface of the device layer furthest from the second side.

12. A method for manufacturing a stacked packaging structure, characterized in that, include: A substrate and a plurality of chips stacked on the substrate are provided, wherein the chips have opposing first and second surfaces, a device layer is formed on the second surface, and conductive vias are formed through the chips. A first conductive portion and a second conductive portion are formed on the first surface, and the first conductive portion is in contact with the conductive through hole; A heat-conducting portion is formed, the heat-conducting portion being located on the first surface and in contact with the second conductive portion; the heat-conducting portion is used to provide resistance heat. A first initial solder portion and a second initial solder portion are formed between adjacent chips. The first initial solder portion is in contact with the first conductive portion and the device layer, and the second initial solder portion is in contact with the second conductive portion and the device layer. A bonding process is performed to transform the first initial solder portion into a first solder portion fixed to the first conductive portion and the device layer, and to transform the second initial solder portion into a second solder portion fixed to the second conductive portion and the device layer. In the bonding process step, current is supplied to the heat-conducting portion to generate heat.

13. The method for manufacturing the stacked packaging structure as described in claim 12, characterized in that, The process for forming the heat-conducting part is the same as the process for forming the first conductive part and the second conductive part.

14. The method for manufacturing the stacked packaging structure as described in claim 12, characterized in that, Also includes: The first conductive portion and the second conductive portion are formed on the surface of the substrate facing the chip; The thermally conductive portion is formed on the surface of the substrate facing the chip, and the thermally conductive portion contacts the second conductive portion on the substrate; A first initial solder portion and a second initial solder portion are formed between the substrate and the chip adjacent to the substrate. The first initial solder portion contacts the first conductive portion on the substrate and the device layer adjacent to the substrate. The second initial solder portion contacts the second conductive portion on the substrate and the device layer adjacent to the substrate.

15. The method for manufacturing the stacked packaging structure as described in claim 12, characterized in that, A first chip, a second chip, a third chip, and a fourth chip are sequentially stacked on the substrate. In the bonding process, the heat generated by the heat-conducting part on the first chip is greater than the heat generated by the heat-conducting part on the second chip, and the heat generated by the heat-conducting part on the second chip is greater than the heat generated by the heat-conducting part on the third chip.

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