A lateral low-power device

Abstract

The present invention belongs to the field of power semiconductor technology, and specifically relates to a lateral low-power power device. Based on a traditional device, the present invention arranges a polysilicon resistor on the upper surface of a field oxide layer. One end of the polysilicon resistor is connected to the N+ anode region through a first layer of metal, and the other end is connected to the P+ anode region through a first layer of metal, thereby regulating the anode end potential distribution when the device is turned on, so that the device can be converted to a bipolar working mode more quickly to suppress the snapback phenomenon. When the device is turned off, the polysilicon resistor provides an additional electron extraction path to speed up the device shutdown speed and reduce the shutdown loss. The present invention limits the snapback phenomenon in the device mechanism and reduces the shutdown loss; reduces the chip area in the layout and improves the chip area utilization; and is compatible with the traditional CMOS process in the process manufacturing.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductors, and in particular relates to a lateral low-power consumption power device. Background Art

[0002] Thanks to the conductivity modulation effect, lateral insulated gate bipolar transistors (LIGBTs) achieve a high breakdown voltage (BV) while also achieving a much lower forward voltage drop (Von) than power MOSFETs. Because they are easily integrated into silicon- and silicon-on-insulator (SOI)-based intelligent power integrated circuits, they are widely used in industrial, consumer power electronics, and military applications. However, during the LIGBT's turn-off process, the unbalanced carriers stored in the drift region generate a long tail current, resulting in significant turn-off losses (Eoff). This leads to a trade-off between low Von and low Eoff.

[0003] Shorted-anode (SA) LIGBT can optimize V on and E off There is a compromise between the two, but the snapback phenomenon can lead to uneven current distribution when the device is turned on, seriously affecting the stability and reliability of the power electronics system. To suppress the snapback phenomenon, researchers at home and abroad have proposed new devices such as the segmented short-anode (SSA) LIGBT and the segmented trench anode (STA) LIGBT. However, these devices suffer from low chip area utilization and complex manufacturing processes. Summary of the Invention

[0004] In response to the above problems, the present invention proposes a lateral low-power power device.

[0005] The technical solution of the present invention is:

[0006] A lateral low-power device comprises a substrate layer 1, an insulating layer 2 located on the upper surface of the substrate layer 1, and an active layer 3 located on the upper surface of the insulating layer 2. The upper ends of the active layer 3 are provided with a P-well 4 and an N-type buffer layer 5, respectively. The upper layer of the P-well 4 has a P+ cathode region 9 and an N+ cathode region 10 arranged in parallel. The upper layer of the N-type buffer layer 5 has a P+ anode region 11 and an N+ anode region 12, with a gap between the P+ anode region 11 and the N+ anode region 12. A gate oxide layer 7 is provided on a portion of the upper surface of the N+ cathode region 10 and on the upper surface of the P-well 4 between the N+ cathode region 10 and the active layer 3, and the gate oxide layer 7 extends to the upper surface of the active layer 3. A field oxide layer 6 is provided on the upper surface of the active layer 3 between the gate oxide layer 7 and the N-type buffer layer 5. A polysilicon gate 8 is provided on the upper surface of the gate oxide layer 7. The polysilicon gate 8 also has a gate oxide layer 7. Extending to cover part of the upper surface of the field oxide layer 6; a polysilicon resistor is provided on the upper surface of the field oxide layer 6 near the N-type buffer layer 5, and there is a distance between the polysilicon resistor and the N-type buffer layer 5; a dielectric layer is provided on the upper surface of the N-type buffer layer 5, and the dielectric layer extends along the upper surface of the field oxide layer 6 to completely cover the polysilicon resistor and also extends to the side close to the P well 4; a first metal layer and a second metal layer are provided on the dielectric layer, the first metal layer and the second metal layer are isolated from each other and the second metal layer is located directly above the N+ anode region 12; the first metal layer is connected to the polysilicon resistor and the P+ anode region 11 through a through hole; the second metal layer has a branch structure, the branch structure of the second metal layer extends along the lateral direction of the device to above the polysilicon resistor, and the second metal layer is connected to the polysilicon resistor and the N+ anode region 12 respectively through through holes.

[0007] Furthermore, the polysilicon resistor is divided into multiple segments along the longitudinal direction of the device, and the longitudinal direction of the device is the third direction perpendicular to the lateral direction and the vertical direction of the device; each segment of the polysilicon resistor is simultaneously connected to the P+ anode area 11 through the first metal layer and to the N+ anode area 12 through the second metal layer, and the corresponding first metal layer is also divided into multiple segments along the longitudinal direction of the device and corresponds one-to-one to the polysilicon resistor.

[0008] Furthermore, adjacent polysilicon resistors are connected via high-resistance polysilicon, where the high-resistance polysilicon means that the resistance of the high-resistance polysilicon is greater than the resistance of the polysilicon resistor.

[0009] The beneficial effects of the present invention are as follows: the present invention limits the snapback phenomenon in the device mechanism and reduces the turn-off loss; reduces the chip area in the layout and improves the utilization rate of the chip area; and is compatible with the traditional CMOS process in the process manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 Schematic diagram of the structure of a LIGBT device with a polysilicon resistor;

[0011] Figure 2 Schematic diagram of the structure of a LIGBT device with discontinuous distribution of polysilicon resistance

[0012] Figure 3 for Figure 2 Structural schematic diagram, two-dimensional plan view of the anode area and the corresponding layout diagram;

[0013] Figure 4 A schematic diagram of the layout of the upper surface of the device in Example 1 and the steps of covering the first layer of metal;

[0014] Figure 5 A schematic diagram of the layout of the upper surface of the device in Example 2 and the steps of covering the first layer of metal;

[0015] Figure 6 Schematic diagram of the layout of the upper surface of the device in Example 3 and the steps of covering the first layer of metal. DETAILED DESCRIPTION

[0016] The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments:

[0017] Example 1

[0018] like Figure 2 and Figure 4As shown, the lateral low-power device of this example includes a substrate layer 1, an insulating layer 2 located on the upper surface of the substrate layer 1, and an active layer 3 located on the upper surface of the insulating layer 2. The upper ends of the active layer 3 are respectively provided with a P-well 4 and an N-type buffer layer 5. The upper layer of the P-well 4 has a P+ cathode region 9 and an N+ cathode region 10 arranged in parallel. The upper layer of the N-type buffer layer 5 has a P+ anode region 11 and an N+ anode region 12. There is a gap between the P+ anode region 11 and the N+ anode region 12. Part of the upper surface of the N+ cathode region 10 is provided with a gap. A gate oxide layer 7 is provided on the surface of the P-well 4 between the N+ cathode region 10 and the active layer 3, and the gate oxide layer 7 extends to the upper surface of the active layer 3; a field oxide layer 6 is provided on the upper surface of the active layer 3 between the gate oxide layer 7 and the N-type buffer layer 5; a polysilicon gate 8 is provided on the upper surface of the gate oxide layer 7, and the polysilicon gate 8 also extends to cover a portion of the upper surface of the field oxide layer 6; a polysilicon resistor is provided on the upper surface of the field oxide layer 6 near the N-type buffer layer 5, and a distance is provided between the polysilicon resistor and the N-type buffer layer 5; The upper surface of the N-type buffer layer 5 has a dielectric layer, which extends along the upper surface of the field oxide layer 6 to completely cover the polysilicon resistor and then extends toward the side close to the P-well 4; the dielectric layer has a first metal layer and a second metal layer, which are isolated from each other and the second metal layer is located directly above the N+ anode region 12; the first metal layer is connected to the polysilicon resistor and the P+ anode region 11 through a through hole; the second metal layer has a branched structure, the branched structure of the second metal layer extends above the polysilicon resistor along the lateral direction of the device, and the second metal layer is respectively connected to the polysilicon resistor and the N+ anode region 12 through through holes; along the longitudinal direction of the device, the polysilicon resistor is divided into multiple sections, and the longitudinal direction of the device is the third direction perpendicular to the lateral direction and the vertical direction of the device; each section of the polysilicon resistor is simultaneously connected to the P+ anode region 11 through the first metal layer and to the N+ anode region 12 through the second metal layer, and the corresponding first metal layer is also divided into multiple sections along the longitudinal direction of the device and corresponds to the polysilicon resistor one by one.

[0019] The working principle of this example is as follows: in terms of device mechanism, by arranging polysilicon resistors connecting the N+ anode region and the P+ anode region, the anode terminal potential distribution is regulated when the device is turned on, so that the device can be converted to bipolar operation mode more quickly to suppress the snapback phenomenon; when the device is turned off, the polysilicon resistors provide additional electron extraction paths to speed up the device shutdown speed and reduce the turn-off loss. In terms of layout, this layout is suitable for circular layout, racetrack layout and interdigitated layout. By evenly placing the polysilicon resistors on the upper surface of the field oxide layer, the distance between the N+ anode region and the P+ anode region is shortened, reducing the chip area while acting as an anode field plate. In terms of manufacturing process, the process of this invention is compatible with traditional CMOS process.

[0020] Example 2

[0021] like Figure 2 and Figure 5 As shown, the difference between this example and Example 1 is that the polysilicon resistors R are connected via high-resistance polysilicon 14.

[0022] Compared with Example 1, the high-resistance polysilicon provides the function of the anode field plate, and the polysilicon is uninterrupted, thereby reducing the probability of defects in the manufacturing process.

[0023] Example 3

[0024] like Figure 2 and Figure 6 As shown, the difference between this example and Example 1 is that the polysilicon resistor R is continuous and uninterrupted, and is segmented and connected in parallel through the first metal layer 131 and the through hole 111.

[0025] Compared with Example 1, the polysilicon is uninterrupted, which reduces the probability of defects in the manufacturing process, and the resistance size and distribution of the polysilicon can be adjusted by the length of the first layer of metal.

[0026] The following is the preparation method of the present invention:

[0027] Step 1: preparing semiconductor materials, wherein the semiconductor materials include a substrate layer 1, an insulating layer 2, and an active layer 3 stacked in sequence from bottom to top, wherein the active layer 3 is of N-type conductivity;

[0028] Step 2: Through ion implantation and a certain period of high-temperature push-in, a P-well 4 is formed at one end of the active layer 3, and an N-buffer layer 5 is formed at the other end of the active layer 3;

[0029] Step 3: Nitride is deposited on the upper surface of the P-well 4 and the N-buffer layer 5, and then a field oxide layer 6 is formed through a long high-temperature thermal process. The nitride is then removed, and a high-quality gate oxide layer 7 is formed on the upper surface where the P-well 4 and the active layer 3 meet using dry oxygen oxidation.

[0030] Step 4: Deposit polysilicon on the surface of the oxide layer, and use general implantation to meet the doping concentration requirements of the polysilicon resistor. Then, perform a second implantation of local polysilicon to form a high-concentration polysilicon gate 8.

[0031] Step 5: Etching polysilicon to form polysilicon gate 8 and polysilicon resistor R;

[0032] Step 6: Ion implantation is performed on the upper surface of the P well 4 to form a P+ cathode region 9 and an N+ cathode region 10, and ion implantation is performed on the upper surface of the N buffer layer 5 near the field oxide layer 6 to form a P+ anode region 11 and an N+ anode region 12;

[0033] Step 7: deposit silicon dioxide, etch through holes 111 , 112 , 121 , 122 and deposit a first metal layer 131 and a second metal layer 132 .

Claims

1. A lateral low-power device, comprising a substrate layer (1), an insulating layer (2) located on the upper surface of the substrate layer (1), and an active layer (3) located on the upper surface of the insulating layer (2), wherein the upper ends of the active layer (3) are provided with a P-type well (4) and an N-type buffer layer (5), respectively; the upper layer of the P-type well (4) is provided with a P+ cathode region (9) and an N+ cathode region (10) arranged in parallel; the upper layer of the N-type buffer layer (5) is provided with a P+ anode region (11) and an N+ anode region (12), and the P+ anode region (11) and the N+ anode region (12) are provided with a P+ cathode region (9) and an N+ cathode region (10) arranged in parallel. ) have a spacing between them; a gate oxide layer (7) is provided on a portion of the upper surface of the N+ cathode region (10) and the upper surface of the P well (4) between the N+ cathode region (10) and the active layer (3), and the gate oxide layer (7) extends to the upper surface of the active layer (3); a field oxide layer (6) is provided on the upper surface of the active layer (3) between the gate oxide layer (7) and the N-type buffer layer (5); a polysilicon gate (8) is provided on the upper surface of the gate oxide layer (7), and the polysilicon gate (8) further extends to cover a portion of the upper surface of the field oxide layer (6); and the invention is characterized in that: A polysilicon resistor is provided on the upper surface of the field oxide layer (6) near the N-type buffer layer (5), and a distance is provided between the polysilicon resistor and the N-type buffer layer (5); a dielectric layer is provided on the upper surface of the N-type buffer layer (5), and the dielectric layer extends along the upper surface of the field oxide layer (6) until it completely covers the polysilicon resistor and then extends toward a side near the P-well (4); a first metal layer and a second metal layer are provided on the dielectric layer, the first metal layer and the second metal layer are isolated from each other, and the second metal layer is located directly above the N+ anode region (12); The first metal layer is connected to the polysilicon resistor and the P+ anode region (11) through a through hole; the second metal layer has a branch structure, the branch structure of the second metal layer extends above the polysilicon resistor along the lateral direction of the device, and the second metal layer is respectively connected to the polysilicon resistor and the N+ anode region (12) through the through hole.

2. A lateral low-power device according to claim 1, characterized in that: The polysilicon resistor is divided into multiple sections along the longitudinal direction of the device, and the longitudinal direction of the device is a third direction perpendicular to the lateral direction and the vertical direction of the device; each section of the polysilicon resistor is simultaneously connected to the P+ anode region (11) through the first metal layer and to the N+ anode region (12) through the second metal layer, and the corresponding first metal layer is also divided into multiple sections along the longitudinal direction of the device and corresponds one-to-one to the polysilicon resistor, and similarly, the second metal layer has multiple corresponding branches.

3. A lateral low-power device according to claim 2, characterized in that: Adjacent polysilicon resistors are connected via high-resistance polysilicon, where the resistance of the high-resistance polysilicon is greater than the resistance of the polysilicon resistors.

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