Display panel and manufacturing method thereof

Abstract

The present application provides a display panel and a preparation method thereof; the display panel sets an undercut portion in a transition area so that the undercut portion includes a metal layer and an organic layer, and the organic layer is located between the substrate and the metal layer. When forming the undercut portion, the organic layer can be etched by physical etching. Since physical etching only etches the inner wall of the organic layer and does not etch away the metal layer, an undercut portion can be obtained, and the common layer can be broken at the undercut portion, thereby improving the water and oxygen barrier capability of the display panel without the need for deep hole etching, thereby improving the performance of the thin film transistor.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same. Background Art

[0002] Low-temperature polycrystalline oxide (LTPO) thin-film transistors are widely used because they have the high mobility of low-temperature polycrystalline silicon (LTPS) thin-film transistors and the low leakage current and high refresh rate characteristics of oxide thin-film transistors. During the preparation of display devices, an undercut structure is provided to disconnect the common layer to prevent water and oxygen intrusion. However, in display devices using low-temperature polycrystalline silicon oxide thin-film transistors, due to the large number of film layers in the display devices, deep hole etching is required to prepare the undercut structure, which is a difficult process and can easily affect the performance of the thin-film transistor, thereby affecting the display.

[0003] Therefore, existing display devices using low-temperature polysilicon oxide thin film transistors have a technical problem in that the performance of the thin film transistors is poor due to the high difficulty of the deep hole etching process of the undercut structure. Summary of the Invention

[0004] The embodiments of the present application provide a display panel and a method for preparing the same, which are used to alleviate the technical problem of poor performance of thin film transistors caused by the high difficulty of deep hole etching process of the undercut structure in existing display devices using low-temperature polysilicon oxide thin film transistors.

[0005] An embodiment of the present application provides a display panel, comprising a function-added area, a main display area, and a transition area between the function-added area and the main display area; wherein the display panel comprises:

[0006] substrate;

[0007] A driving circuit layer is provided on one side of the substrate;

[0008] a light-emitting functional layer, comprising a common layer and a pixel electrode layer, wherein the common layer is arranged on a side of the pixel electrode layer away from the driving circuit layer;

[0009] In which, the driving circuit layer includes a bottom cut portion arranged in the transition zone, the bottom cut portion includes a metal layer and an organic layer, the organic layer is located between the substrate and the metal layer, the lateral end of the metal layer extends farther in the lateral direction than the lateral end of the organic layer, and the common layer is disconnected by the bottom cut portion.

[0010] In some embodiments, the driving circuit layer also includes a first source and drain layer, a second source and drain layer, a first planarization layer and a second planarization layer, the first source and drain layer is arranged between the first planarization layer and the substrate, the first planarization layer is arranged between the first source and drain layer and the second source and drain layer, the second source and drain layer is arranged between the first planarization layer and the second planarization layer, the second source and drain layer includes the metal layer, the first planarization layer includes the organic layer, and in the transition region, the lateral end of the second source and drain layer extends farther in the lateral direction than the lateral end of the first planarization layer.

[0011] In some embodiments, the driving circuit layer also includes an insulating layer, which is arranged on the side of the first source and drain layer away from the first planarization layer, and the thickness of the insulating layer in the area where the bottom cut portion is located is less than the thickness of the insulating layer in the display area.

[0012] In some embodiments, the driving circuit layer further includes:

[0013] A first semiconductor layer is provided on one side of the substrate;

[0014] a first gate insulating layer, disposed on a side of the first semiconductor layer away from the substrate;

[0015] a first gate layer, disposed on a side of the first gate insulating layer away from the first semiconductor layer;

[0016] a second gate insulating layer, disposed on a side of the first gate layer away from the first gate insulating layer;

[0017] a second gate layer, disposed on a side of the second gate insulating layer away from the first gate layer;

[0018] a first interlayer insulating layer, disposed on a side of the second gate layer away from the second gate insulating layer;

[0019] a second semiconductor layer, disposed on a side of the first interlayer insulating layer away from the second gate layer;

[0020] a third gate insulating layer, disposed on a side of the second semiconductor layer away from the first interlayer insulating layer;

[0021] a third gate layer, disposed on a side of the third gate insulating layer away from the second semiconductor layer;

[0022] a second interlayer insulating layer, disposed on a side of the third gate layer away from the third gate insulating layer;

[0023] The first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer extend from the display area to the transition area, and the bottom cut portion is arranged on a side of the second interlayer insulating layer away from the substrate.

[0024] In some embodiments, a thickness of the second interlayer insulating layer in the region where the undercut portion is located is smaller than a thickness of the second interlayer insulating layer in the display region.

[0025] In some embodiments, the driving circuit layer further includes a first source-drain layer, a second source-drain layer, a third source-drain layer, a first planarization layer, a second planarization layer and a third planarization layer, the first source-drain layer is arranged between the first planarization layer and the substrate, the first planarization layer is arranged between the first source-drain layer and the second source-drain layer, the second source-drain layer is arranged between the first planarization layer and the second planarization layer, the second planarization layer is arranged between the second source-drain layer and the third source-drain layer, the third source-drain layer is arranged between the second planarization layer and the third planarization layer, the third source-drain layer includes the metal layer, the second planarization layer includes the organic layer, and in the transition region, the lateral end of the third source-drain layer extends farther in the lateral direction than the lateral end of the second planarization layer.

[0026] In some embodiments, the driving circuit layer further includes a buffer layer, the organic layer is in contact with the buffer layer, and the metal layer is disposed on a side of the organic layer away from the buffer layer.

[0027] In some embodiments, the driving circuit layer includes a source-drain electrode layer and a planarization layer disposed on the source-drain electrode layer, the planarization layer includes the organic layer, and the metal layer is disposed on a side of the planarization layer away from the substrate.

[0028] In some embodiments, the undercut portion is arranged around the additional function area, and the undercut portion includes a plurality of undercut sub-portions, and adjacent undercut sub-portions are staggered along a circular direction.

[0029] At the same time, an embodiment of the present application provides a method for manufacturing a display panel, which includes:

[0030] Providing a substrate, and sequentially forming a first semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a first interlayer insulating layer, a second semiconductor layer, a third gate insulating layer, a third gate layer, a second interlayer insulating layer, a first source-drain electrode layer, a first planarization layer, and a second source-drain electrode layer on the substrate;

[0031] The second source and drain electrode layer is etched to form a metal layer; the metal layer is located in a transition area between the main display area and the additional function area;

[0032] forming a second planarization layer, a pixel electrode layer, a pixel definition layer and a support layer in sequence on the second source and drain electrode layer;

[0033] The first planarization layer is longitudinally etched by chemical etching, and then the first planarization layer is transversely etched by physical etching to form an organic layer, thereby obtaining an undercut portion; wherein a transverse end of the metal layer extends further in the transverse direction than a transverse end of the organic layer;

[0034] A common layer is formed on the support layer to obtain a display panel; the common layer is disconnected by the undercut portion.

[0035] Beneficial effects: The present application provides a display panel and a preparation method thereof; the display panel includes a function-added area, a main display area and a transition area located between the function-added area and the main display area; wherein, the display panel includes a substrate, a driving circuit layer and a light-emitting function layer, the driving circuit layer is arranged on one side of the substrate, the light-emitting function layer includes a common layer and a pixel electrode layer, the common layer is arranged on the side of the pixel electrode layer away from the driving circuit layer, wherein, the driving circuit layer includes a bottom cut portion arranged in the transition area, the bottom cut portion includes a metal layer and an organic layer, the organic layer is located between the substrate and the metal layer, the lateral end of the metal layer extends farther in the lateral direction than the lateral end of the organic layer, and the common layer is disconnected by the bottom cut portion. The present application provides an undercut portion in the transition zone, so that the undercut portion includes a metal layer and an organic layer, and the organic layer is located between the substrate and the metal layer. When the undercut portion is formed, the organic layer can be etched by physical etching. Since physical etching only etches the inner wall of the organic layer and does not etch the metal layer, an undercut portion can be obtained, and the common layer can be broken at the undercut portion, thereby improving the water and oxygen barrier capability of the display panel without the need for deep hole etching, thereby improving the performance of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0037] Figure 1 This is a first schematic diagram of an existing display device.

[0038] Figure 2 This is a second schematic diagram of an existing display device.

[0039] Figure 3 This is a first schematic diagram of a display panel provided in an embodiment of the present application.

[0040] Figure 4 This is a second schematic diagram of a display panel provided in an embodiment of the present application.

[0041] Figure 5 This is a flow chart of a method for manufacturing a display panel provided in an embodiment of the present application.

[0042] Figure 6 for Figure 5 A first structural schematic diagram of the transition area of ​​the display panel corresponding to each step of the display panel manufacturing method.

[0043] Figure 7 for Figure 5 A second structural schematic diagram of the transition area of ​​the display panel corresponding to each step of the display panel manufacturing method. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0045] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0046] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, electrical connections, or mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0047] In this application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0048] The disclosure below provides many different embodiments or examples for realizing different structures of the present application. In order to simplify the disclosure of the present application, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present application. In addition, the present application may repeat reference numbers and / or reference letters in different examples, and such repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present application provides examples of various specific processes and materials, but those of ordinary skill in the art will appreciate the application of other processes and / or the use of other materials.

[0049] like Figure 1 、 Figure 2 As shown, the existing display device includes an electronic component setting area 103, a display area 101 and a transition area 102 located between the electronic component setting area 103 and the display area 101. Figure 1 As can be seen in the figure, in the transition region 102, the portion of the display device is indicated by reference numeral 122, and the position of the undercut structure in the display device is indicated by reference numeral 121. Figure 2 As can be seen in the figure, the display device using the low-temperature polycrystalline oxide thin film transistor includes a substrate 11, a barrier layer 12, a buffer layer 13, a first insulating layer 141, a second insulating layer 142, a third insulating layer 143, a fourth insulating layer 144, a fifth insulating layer 145, a first source and drain layer 146, a first planarization layer 147, a second source and drain layer 148, and a second planarization layer 149 ( Figure 2 In order to improve the packaging performance of the display device, an undercut structure 111 is formed in the transition region 102. Figure 2As can be seen in the figure, to form the undercut structure 111, it is necessary to etch away the first insulating layer 141 to the second planarization layer 149, and then etch the substrate 11, barrier layer 12, and buffer layer 13. This etching process requires deep hole etching, which is a difficult process and can easily affect the performance of the thin film transistor. The etching process of the insulating layer may also affect the performance of the thin film structure, thereby affecting the display. Therefore, existing display devices using low-temperature polycrystalline silicon oxide thin film transistors have a technical problem of poor performance of the thin film transistor due to the high difficulty of the deep hole etching process for the undercut structure.

[0050] In response to the above technical problems, embodiments of the present application provide a display panel and a method for manufacturing the same to alleviate the above technical problems.

[0051] like Figure 3 、 Figure 4 As shown, an embodiment of the present application provides a display panel, wherein the display panel 2 includes a function-added area 203, a main display area 201, and a transition area 202 located between the function-added area 203 and the main display area 201; wherein the display panel 2 includes:

[0052] substrate 21;

[0053] A driving circuit layer is provided on one side of the substrate 21;

[0054] The light-emitting functional layer 25 includes a common layer 253 and a pixel electrode layer 251 , wherein the common layer 253 is provided on a side of the pixel electrode layer 251 away from the driving circuit layer;

[0055] In which, the driving circuit layer includes a bottom cut portion 27 arranged in the transition zone 202, the bottom cut portion 27 includes a metal layer 271 and an organic layer 272, the organic layer 272 is located between the substrate 21 and the metal layer 271, the lateral end of the metal layer 271 extends farther in the lateral direction than the lateral end of the organic layer 272, and the common layer 253 is disconnected by the bottom cut portion 27.

[0056] An embodiment of the present application provides a display panel, which provides an undercut portion in a transition region so that the undercut portion includes a metal layer and an organic layer. The organic layer is located between the substrate and the metal layer. When the undercut portion is formed, the organic layer can be etched by physical etching. Since physical etching only etches the inner wall of the organic layer and does not etch the metal layer, an undercut portion can be obtained. The common layer can be broken at the undercut portion, thereby improving the water and oxygen barrier capability of the display panel without the need for deep hole etching, thereby improving the performance of the thin film transistor.

[0057] It should be noted that in Figure 4In the figure, since the second source and drain electrode layer 244 includes a metal layer 271, for the same film layer, the second source and drain electrode layer is represented by reference numeral 244, and the metal layer located in the transition region 202 is represented by reference numeral 271; similarly, the first planarization layer 243 includes an organic layer 272. Figure 4 In the figure, the first planarization layer is indicated by reference numeral 243 , and the organic layer located in the transition region 202 is indicated by reference numeral 272 .

[0058] In order to solve the technical problem that adding a new film layer to the display panel will lead to more processes and increased thickness, in one embodiment, Figure 4 As shown, the driving circuit layer also includes a first source-drain layer 242, a second source-drain layer 244, a first planarization layer 243 and a second planarization layer 245, the first source-drain layer 242 is arranged between the first planarization layer 243 and the substrate 21, the first planarization layer 243 is arranged between the first source-drain layer 242 and the second source-drain layer 244, the second source-drain layer 244 is arranged between the first planarization layer 243 and the second planarization layer 245, the second source-drain layer 244 includes the metal layer 271, the first planarization layer 243 includes the organic layer 272, and in the transition region 202, the lateral end of the second source-drain layer 244 extends farther in the lateral direction than the lateral end of the first planarization layer 243. By forming the second source and drain layer into a metal layer and the first planarization layer into an organic layer, there is no need to set up additional metal layers and organic layers, which reduces the process steps and avoids deep hole etching. The metal layer is located in the second source and drain layer and the organic layer is located in the first planarization layer, avoiding the increase in the thickness of the display panel caused by the addition of new metal layers and organic layers.

[0059] Specifically, in Figure 4 In the embodiment, the display panel includes a low-temperature polycrystalline oxide thin film transistor, which is connected to the first source-drain layer through the second source-drain layer, so as to avoid the need for deep hole connection when the first source-drain layer is connected to the pixel electrode layer, resulting in breakage of the pixel electrode layer, thereby causing poor display, and the second source-drain layer reduces the impedance of the first source-drain layer; at this time, the metal layer and the organic layer can be formed respectively by the second source-drain layer and the first planarization layer located under the second source-drain layer, so as to avoid increasing the thickness of the display panel, reduce the process steps of separately forming the metal layer and the organic layer, avoid deep hole etching, and improve the preparation efficiency of the display panel.

[0060] Specifically, the above embodiments are described in detail using low-temperature polycrystalline oxide thin film transistors as an example, but the embodiments of the present application are not limited to this. For example, when the display panel includes a low-temperature polycrystalline silicon thin film transistor or an oxide thin film transistor, the display panel also includes a first source and drain electrode layer, a second source and drain electrode layer and a first planarization layer. The first source and drain electrode layer and the first planarization layer can also be used to form a metal layer and an organic layer, respectively, thereby avoiding increasing the thickness of the display panel, and can reduce the preparation process of the display panel and improve the preparation efficiency of the display panel.

[0061] In one embodiment, the driving circuit layer further includes an insulating layer, which is disposed on a side of the first source / drain electrode layer away from the first planarization layer. The thickness of the insulating layer in the region where the undercut portion is located is less than the thickness of the insulating layer in the display area. When the undercut portion is formed on the display panel, physical etching simultaneously etches the organic layer and the insulating layer, causing the organic layer to form a shape that is laterally concave relative to the metal layer, thereby forming the undercut portion. Due to the downward etching of the insulating layer, the thickness of the insulating layer in the undercut portion is less than the thickness of the insulating layer in the display area. The insulating layer can prevent water and oxygen from invading the organic layer, thereby improving the water and oxygen barrier capability of the display panel.

[0062] The existing display device needs to etch each insulating layer in the driving circuit layer, which leads to a technical problem of many process steps. In one embodiment, Figure 4 As shown, the driving circuit layer further includes:

[0063] A first semiconductor layer 231 is provided on one side of the substrate 21;

[0064] A first gate insulating layer 232 is provided on a side of the first semiconductor layer 231 away from the substrate 21;

[0065] A first gate layer 233 is disposed on a side of the first gate insulating layer 232 away from the first semiconductor layer 231 ;

[0066] A second gate insulating layer 234 is disposed on a side of the first gate layer 233 away from the first gate insulating layer 232 ;

[0067] A second gate layer 235 is disposed on a side of the second gate insulating layer 234 away from the first gate layer 233 ;

[0068] A first interlayer insulating layer 236 is provided on a side of the second gate layer 235 away from the second gate insulating layer 234 ;

[0069] A second semiconductor layer 237 is disposed on a side of the first interlayer insulating layer 236 away from the second gate layer 235 ;

[0070] a third gate insulating layer 238 , disposed on a side of the second semiconductor layer 237 away from the first interlayer insulating layer 236 ;

[0071] A third gate layer 239 is disposed on a side of the third gate insulating layer 238 away from the second semiconductor layer 237 ;

[0072] A second interlayer insulating layer 241 is disposed on a side of the third gate layer 239 away from the third gate insulating layer 238 ;

[0073] In which, the first gate insulating layer 232, the second gate insulating layer 234, the first interlayer insulating layer 236, the third gate insulating layer 238 and the second interlayer insulating layer 241 extend from the display area 201 to the transition area 202, and the bottom cut portion 27 is arranged on the side of the second interlayer insulating layer 241 away from the substrate 21.

[0074] Specifically, for a display panel provided with a low-temperature polycrystalline oxide thin film transistor, the existing display panel needs to etch the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer to form an undercut structure on the substrate, but this solution will result in more steps in preparing the display panel, and etching the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer will cause the display panel's ability to block water and oxygen to decrease, and the low-temperature polycrystalline oxide thin film transistor will be affected by the process during the etching process, resulting in poor performance. The embodiment of the present application can use the first planarization layer and the second source and drain layer to form the bottom cut portion. Except for necessary etching such as forming vias, there is no need to perform additional etching on the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer, thereby reducing the process steps of the display panel. The complete first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer, and the second interlayer insulating layer can increase the path for water and oxygen intrusion, and have a better water and oxygen barrier effect, thereby improving the ability of the display panel to block water and oxygen. In addition, since the etching steps are reduced and deep hole etching is avoided, the possibility of the low-temperature polycrystalline oxide thin film transistor being affected by etching is reduced, thereby improving the device stability of the thin film transistor in the display panel.

[0075] Specifically, such as Figure 4As shown, the display panel 2 also includes a buffer layer 22, and the substrate 21 and the buffer layer 22 extend from the display area 201 to the transition area 202. By extending the substrate and the buffer layer to the transition area, there is no need to etch the substrate and the buffer layer to form an undercut structure, which increases the path for water and oxygen intrusion, has a better water and oxygen barrier effect, and improves the ability of the display panel to block water and oxygen. It also reduces the number of etching steps, avoids deep hole etching, reduces the possibility of low-temperature polycrystalline oxide thin film transistors being affected by etching, and improves the device stability of the thin film transistors in the display panel.

[0076] In one embodiment, the thickness of the second interlayer insulating layer in the region where the undercut portion is located is less than the thickness of the second interlayer insulating layer in the display area. When the undercut portion is formed on the display panel, physical etching simultaneously etches the organic layer and the second interlayer insulating layer, causing the organic layer to form a shape that is laterally concave relative to the metal layer, thereby forming the undercut portion. Due to the downward etching of the second interlayer insulating layer, the thickness of the second interlayer insulating layer in the region where the undercut portion is located is less than the thickness of the second interlayer insulating layer in the display area. The second interlayer insulating layer can block the intrusion of water and oxygen from the organic layer, thereby improving the water and oxygen barrier capability of the display panel.

[0077] In one embodiment, the driving circuit layer further includes a first source-drain electrode layer, a second source-drain electrode layer, a third source-drain electrode layer, a first planarization layer, a second planarization layer and a third planarization layer, the first source-drain electrode layer is arranged between the first planarization layer and the substrate, the first planarization layer is arranged between the first source-drain electrode layer and the second source-drain electrode layer, the second source-drain electrode layer is arranged between the first planarization layer and the second planarization layer, the second planarization layer is arranged between the second source-drain electrode layer and the third source-drain electrode layer, the third source-drain electrode layer is arranged between the second planarization layer and the third planarization layer, the third source-drain electrode layer includes the metal layer, the second planarization layer includes the organic layer, and in the transition region, the lateral end of the third source-drain electrode layer extends farther in the lateral direction than the lateral end of the second planarization layer.

[0078] Specifically, for a display panel having a first source and drain layer, a second source and drain layer, and a third source and drain layer, the third source and drain layer can be used to form a metal layer, and the second planarization layer can be used to form an organic layer. In this way, there is no need to add new metal layers and organic layers, which reduces the process steps and avoids deep hole etching. The metal layer is located in the third source and drain layer, and the organic layer is located in the second planarization layer, which avoids the situation where the new metal layers and organic layers increase the thickness of the display panel.

[0079] In one embodiment, the driving circuit layer further comprises a buffer layer, the organic layer contacts the buffer layer, and the metal layer is disposed on a side of the organic layer away from the buffer layer. When providing the undercut portion, the organic layer and the metal layer can be formed on the buffer layer after etching the insulating layer, so that the metal layer and the organic layer form an undercut portion. This eliminates the need to etch the buffer layer and the substrate, reduces process steps, avoids deep hole etching, and improves the performance of the thin film transistor. Furthermore, because the metal layer and the organic layer are disposed on the buffer layer, the height of the other film layers is greater than that of the metal layer and the organic layer, and the thickness of the display panel is not increased.

[0080] Specifically, the above embodiments are described in detail using the example of an organic layer and a metal layer being arranged on a buffer layer, but the embodiments of the present application are not limited to this. For example, the bottom cut portion can be arranged on any one of the first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer, which will not be repeated here.

[0081] In one embodiment, the driving circuit layer includes a source / drain electrode layer and a planarization layer disposed on the source / drain electrode layer, the planarization layer includes the organic layer, and the metal layer is disposed on a side of the planarization layer away from the substrate. When the display panel includes the source / drain electrode layer and the planarization layer, the planarization layer can be formed as an organic layer, and then the metal layer can be formed on the organic layer. The planarization layer can then be etched to form an undercut. This eliminates the need to etch the buffer layer and substrate, reduces process steps, avoids deep hole etching, and improves the performance of the thin film transistor. Furthermore, since the organic layer uses the planarization layer, the thickness of the display panel can be reduced.

[0082] In one embodiment, the substrate includes a first flexible layer, a first inorganic layer, a second flexible layer, and a second inorganic layer.

[0083] In one embodiment, if Figure 4 As shown, the display panel 2 further includes a support layer 26 , the light-emitting functional layer 25 further includes a pixel definition layer 252 , and the second planarization layer 245 , the pixel definition layer 252 and the support layer 26 form a retaining wall.

[0084] In one embodiment, the undercut portion is disposed around the additional functional area and includes a plurality of undercut sub-portions, with adjacent undercut sub-portions staggered in a circular direction. By staggering the plurality of undercut sub-portions, during the manufacture and use of the display panel, the display panel in the area where the undercut portion is located is prevented from being partially thin, thereby preventing collapse of the display panel in the area where the undercut portion is located, thereby improving the yield of the display panel.

[0085] Specifically, such as Figure 3As shown, the portion of the display panel located in the transition region is indicated by reference numeral 211, and the position and shape of the undercut portion located in the transition region are indicated by reference numeral 212. Figure 3 It can be seen that the two adjacent undercut sub-portions in the undercut portion are staggered along the ring, which can avoid the undercut portion having a smaller thickness along the ring, avoid the display panel in the area where the undercut portion is located from collapsing, and improve the yield of the display panel.

[0086] In one embodiment, the display panel further includes an encapsulation layer, and the encapsulation layer is disposed on a side of the light-emitting functional layer away from the driving circuit layer.

[0087] At the same time, the present invention provides a method for manufacturing a display panel. Figure 5 As shown, the display panel manufacturing method includes the following steps:

[0088] S1, providing a substrate, and sequentially forming a first semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a first interlayer insulating layer, a second semiconductor layer, a third gate insulating layer, a third gate layer, a second interlayer insulating layer, a first source-drain electrode layer, a first planarization layer, and a second source-drain electrode layer on the substrate; the structure of the transition region of the display panel corresponding to this step is as follows Figure 6 As shown in (a);

[0089] S2, etching the second source and drain electrode layer to form a metal layer; the metal layer is located in the transition area between the main display area and the additional function area; the structure of the transition area of ​​the display panel corresponding to this step is as follows Figure 6 As shown in (b);

[0090] S3, forming a second planarization layer, a pixel electrode layer, a pixel definition layer and a support layer in sequence on the second source and drain electrode layer;

[0091] S4, using chemical etching to longitudinally etch the first planarization layer, and then using physical etching to transversely etch the first planarization layer to form an organic layer, thereby obtaining an undercut portion; the transverse end of the metal layer extends further in the transverse direction than the transverse end of the organic layer; wherein the structure of the transition region of the display panel after longitudinally etching the first planarization layer using chemical etching is as follows Figure 7 As shown in (a), the first planarization layer is laterally etched by physical etching to form an organic layer, and the structure of the transition area of ​​the display panel after the undercut portion is obtained is as shown in FIG. Figure 7 As shown in (b);

[0092] Specifically, physical etching includes plasma etching.

[0093] S5, forming a common layer on the support layer to obtain a display panel; the common layer is disconnected by the undercut portion.

[0094] An embodiment of the present application provides a method for preparing a display panel. When preparing the display panel, the method etches a first planarization layer by physical etching. Since the physical etching can be controlled to only etch the metal layer, an undercut portion can be obtained through the second source and drain layer and the first planarization layer. The common layer can be broken at the undercut portion, thereby improving the water and oxygen barrier capability of the display panel without the need for deep hole etching, thereby improving the performance of the thin film transistor.

[0095] It should be noted that, for the sake of convenience, Figure 6 and Figure 7 FIG. 1 is a schematic diagram showing only a portion of the transition region of the display panel.

[0096] Specifically, when etching the second source and drain electrode layer, a photoresist may be formed on the second source and drain electrode layer first, and the photoresist may be patterned. Then, the second source and drain electrode layer may be etched by plasma etching.

[0097] Specifically, when etching the first planarization layer, photoresist patterning may be performed on the first planarization layer, and a protective layer may be used to protect the display area, and then etching may be performed using plasma etching.

[0098] Specifically, after etching the first planarization layer, the photoresist may be washed away, and then the common layer may be formed.

[0099] According to the above embodiments, it can be seen that:

[0100] An embodiment of the present application provides a display panel and a preparation method thereof; the display panel includes a function-added area, a main display area and a transition area located between the function-added area and the main display area; wherein the display panel includes a substrate, a driving circuit layer and a light-emitting function layer, the driving circuit layer is arranged on one side of the substrate, the light-emitting function layer includes a common layer and a pixel electrode layer, the common layer is arranged on the side of the pixel electrode layer away from the driving circuit layer, wherein the driving circuit layer includes a bottom cut portion arranged in the transition area, the bottom cut portion includes a metal layer and an organic layer, the organic layer is located between the substrate and the metal layer, the lateral end of the metal layer extends farther in the lateral direction than the lateral end of the organic layer, and the common layer is disconnected by the bottom cut portion. The present application provides an undercut portion in the transition zone, so that the undercut portion includes a metal layer and an organic layer, and the organic layer is located between the substrate and the metal layer. When the undercut portion is formed, the organic layer can be etched by physical etching. Since physical etching only etches the inner wall of the organic layer and does not etch the metal layer, an undercut portion can be obtained, and the common layer can be broken at the undercut portion, thereby improving the water and oxygen barrier capability of the display panel without the need for deep hole etching, thereby improving the performance of the thin film transistor.

[0101] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0102] The above is a detailed introduction to a display panel and a preparation method thereof provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises a function-added area, a main display area, and a transition area between the function-added area and the main display area; wherein the display panel comprises: substrate; A driving circuit layer is provided on one side of the substrate; a light-emitting functional layer, comprising a common layer and a pixel electrode layer, wherein the common layer is arranged on a side of the pixel electrode layer away from the driving circuit layer; The driving circuit layer includes an undercut portion provided in the transition region, the undercut portion includes a metal layer and an organic layer, the organic layer is located between the substrate and the metal layer, a lateral end of the metal layer extends further in a lateral direction than a lateral end of the organic layer, and the common layer is disconnected by the undercut portion; The common layer is disconnected by the undercut portion on both sides of the undercut portion, the undercut portion is arranged around the additional function area, and the undercut portion includes a plurality of undercut sub-portions, and adjacent undercut sub-portions are staggered along the annular direction.

2. The display panel according to claim 1, wherein The driving circuit layer also includes a first source-drain layer, a second source-drain layer, a first planarization layer and a second planarization layer, the first source-drain layer is arranged between the first planarization layer and the substrate, the first planarization layer is arranged between the first source-drain layer and the second source-drain layer, the second source-drain layer is arranged between the first planarization layer and the second planarization layer, the second source-drain layer includes the metal layer, the first planarization layer includes the organic layer, and in the transition region, the lateral end of the second source-drain layer extends farther in the lateral direction than the lateral end of the first planarization layer.

3. The display panel according to claim 2, wherein: The driving circuit layer further includes an insulating layer, which is disposed on a side of the first source and drain layer away from the first planarization layer. The thickness of the insulating layer in the area where the bottom cut portion is located is less than the thickness of the insulating layer in the display area.

4. The display panel according to claim 2, wherein: The driving circuit layer further includes: A first semiconductor layer is provided on one side of the substrate; a first gate insulating layer, disposed on a side of the first semiconductor layer away from the substrate; a first gate layer, disposed on a side of the first gate insulating layer away from the first semiconductor layer; a second gate insulating layer, disposed on a side of the first gate layer away from the first gate insulating layer; a second gate layer, disposed on a side of the second gate insulating layer away from the first gate layer; a first interlayer insulating layer, disposed on a side of the second gate layer away from the second gate insulating layer; a second semiconductor layer, disposed on a side of the first interlayer insulating layer away from the second gate layer; a third gate insulating layer, disposed on a side of the second semiconductor layer away from the first interlayer insulating layer; a third gate layer, disposed on a side of the third gate insulating layer away from the second semiconductor layer; a second interlayer insulating layer, disposed on a side of the third gate layer away from the third gate insulating layer; The first gate insulating layer, the second gate insulating layer, the first interlayer insulating layer, the third gate insulating layer and the second interlayer insulating layer extend from the display area to the transition area, and the bottom cut portion is arranged on a side of the second interlayer insulating layer away from the substrate.

5. The display panel according to claim 4, wherein: The thickness of the second interlayer insulating layer in the region where the undercut portion is located is smaller than the thickness of the second interlayer insulating layer in the display region.

6. The display panel according to claim 1, wherein: The driving circuit layer also includes a first source-drain electrode layer, a second source-drain electrode layer, a third source-drain electrode layer, a first planarization layer, a second planarization layer and a third planarization layer, the first source-drain electrode layer is arranged between the first planarization layer and the substrate, the first planarization layer is arranged between the first source-drain electrode layer and the second source-drain electrode layer, the second source-drain electrode layer is arranged between the first planarization layer and the second planarization layer, the second planarization layer is arranged between the second source-drain electrode layer and the third source-drain electrode layer, the third source-drain electrode layer is arranged between the second planarization layer and the third planarization layer, the third source-drain electrode layer includes the metal layer, the second planarization layer includes the organic layer, and in the transition region, the lateral end of the third source-drain electrode layer extends farther in the lateral direction than the lateral end of the second planarization layer.

7. The display panel according to claim 1, wherein: The driving circuit layer further includes a buffer layer, the organic layer is in contact with the buffer layer, and the metal layer is arranged on a side of the organic layer away from the buffer layer.

8. The display panel according to claim 1, wherein: The driving circuit layer includes a source-drain electrode layer and a planarization layer disposed on the source-drain electrode layer. The planarization layer includes the organic layer. The metal layer is disposed on a side of the planarization layer away from the substrate.

9. A method for preparing a display panel, characterized in that: A method for preparing a display panel according to any one of claims 1 to 8, wherein the method comprises: Providing a substrate, and sequentially forming a first semiconductor layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a first interlayer insulating layer, a second semiconductor layer, a third gate insulating layer, a third gate layer, a second interlayer insulating layer, a first source-drain electrode layer, a first planarization layer, and a second source-drain electrode layer on the substrate; The second source and drain electrode layer is etched to form a metal layer; the metal layer is located in a transition area between the main display area and the additional function area; forming a second planarization layer, a pixel electrode layer, a pixel definition layer and a support layer in sequence on the second source and drain electrode layer; The first planarization layer is longitudinally etched by chemical etching, and then the first planarization layer is transversely etched by physical etching to form an organic layer, thereby obtaining an undercut portion; wherein a transverse end of the metal layer extends further in the transverse direction than a transverse end of the organic layer; A common layer is formed on the support layer to obtain a display panel; the common layer is disconnected by the undercut portion.

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