Method for manufacturing semiconductor element

Abstract

The purpose of the present disclosure is to provide a method for manufacturing a semiconductor element with a low defect rate and a thin film. In the method for manufacturing a semiconductor element involved in the present disclosure, a circuit element substrate (7) having a semiconductor substrate (1) and a circuit element (2) on the semiconductor substrate (1) is prepared, an electrode protection layer (3) is formed on the circuit element (2), a support substrate (8) is prepared, a metal film (6) is formed on the electrode protection layer (3) of the circuit element substrate (7) and on the support substrate (8) in a vacuum, the circuit element substrate and the metal film (6) of the support substrate are adhered to each other by an atomic diffusion bonding method, thereby bonding the circuit element substrate (7) and the support substrate (8), the semiconductor substrate (1) is polished and removed to expose the circuit element (2), a transfer substrate (10) is bonded to the exposed surface of the circuit element (2), and after bonding the transfer substrate (10), the support substrate (8) is peeled off from the circuit element (2).

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor element. Background Art

[0002] In the past, semiconductor modules were miniaturized by high-density packaging of semiconductor elements, or high performance was achieved by bonding semiconductor elements to heat dissipation substrates, so it was required to reduce the thickness of semiconductor elements (hereinafter also referred to as "thinning"). Thinning of semiconductor elements is carried out through the following steps. First, the circuit element surface of the semiconductor element is bonded to the supporting substrate, and the surface on the opposite side is mechanically and chemically polished. Next, the supporting substrate is peeled off from the semiconductor element. In these steps, it is necessary to prevent cracks or breakage from occurring in the thinned semiconductor elements.

[0003] Patent Document 1 discloses a method in which a semiconductor substrate having a thickness of 1130 μm is bonded to a support substrate using electronic wax, the back surface of the semiconductor substrate is polished, a transfer substrate is bonded to the back surface of the semiconductor substrate, and the support substrate is peeled off by heating.

[0004] Patent Document 2 discloses a method of removing a substrate by etching instead of grinding. Specifically, an organic insulating film is applied to a semiconductor layer on a Si substrate except for the end of a wafer composed of the Si substrate and the semiconductor layer. Next, an inorganic insulating film is formed in a manner covering the organic insulating film. After that, the surfaces of the wafer and the supporting substrate are activated in a vacuum, and the wafer is attached to the supporting substrate. After that, the Si substrate is removed by etching.

[0005] Patent document 3 describes a method for manufacturing a semiconductor element with a chip-on-chip structure. In the manufacturing method of patent document 3, a semiconductor wafer has a Si substrate and an element layer on the Si substrate. A through electrode spanning the Si substrate and the element layer is formed. After an insulating film and a metal layer are sequentially formed on the element layer, the metal layer of the semiconductor wafer is attached to the metal layer of the support substrate. After grinding the back of the wafer until the through electrode is exposed from the back, the support substrate is removed by grinding and etching.

[0006] Prior art literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2005-129825

[0008] Patent Document 2: Japanese Patent Application Publication No. 2012-028477

[0009] Patent Document 3: Japanese Patent Application Publication No. 2007-324406 Summary of the invention

[0010] In the conventional methods described in Patent Documents 1-3, etc., it is possible to slice a substrate including circuit elements to a certain thickness. However, when the substrate on the back is completely removed and the circuit elements are sliced ​​to less than 10 μm, the substrate supporting the circuit elements disappears, so the strength of the semiconductor element is weakened, and during grinding, cutting, or peeling of the supporting substrate, cracks, breakage, or film peeling may occur in the semiconductor element, resulting in an increase in the defect rate.

[0011] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a method for manufacturing a thin semiconductor element with a low defect rate.

[0012] In the manufacturing method of the semiconductor element disclosed in the present invention, a circuit element substrate having a semiconductor substrate and a circuit element on the semiconductor substrate is prepared, an electrode protection layer is formed on the circuit element, a supporting substrate is prepared, a metal film is formed on the electrode protection layer of the circuit element substrate and on the supporting substrate in a vacuum, the circuit element substrate and the metal film of the supporting substrate are adhered to each other by an atomic diffusion bonding method, thereby bonding the circuit element substrate and the supporting substrate, the semiconductor substrate is ground and removed to expose the circuit element, a transfer substrate is bonded to the exposed surface of the circuit element, and the supporting substrate is peeled off from the circuit element after the transfer substrate is bonded.

[0013] According to the method for manufacturing a semiconductor element disclosed in the present invention, even if the semiconductor substrate is ground and removed, cracks, peeling or damage are not likely to occur in the circuit element, and a thin semiconductor element with a low defect rate can be manufactured. The purpose, features, methods and advantages of the present invention will become clearer through the following detailed description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a cross-sectional view of the semiconductor element according to the first embodiment.

[0015] Figure 2 This is a flowchart showing the method for manufacturing the semiconductor element according to the first embodiment.

[0016] Figure 3 This is a cross-sectional view showing the method for manufacturing the semiconductor element according to the first embodiment.

[0017] Figure 4 This is a cross-sectional view showing the method for manufacturing the semiconductor element according to the first embodiment.

[0018] Figure 5 This is a cross-sectional view showing the method for manufacturing the semiconductor element according to the first embodiment.

[0019] Figure 6 This is a cross-sectional view showing the method for manufacturing the semiconductor element according to the first embodiment.

[0020] Figure 7 It is a cross-sectional view showing a method of manufacturing a semiconductor element of Embodiment 1.

[0021] Figure 8 It is a cross-sectional view showing a method of manufacturing a semiconductor element of Embodiment 1.

[0022] Fig. 9 It is a cross-sectional view showing a method of manufacturing a semiconductor element of Embodiment 1.

[0023] Fig.10 It is a cross-sectional view showing a method of manufacturing a semiconductor element of Embodiment 1.

[0024] Fig.11 It is a cross-sectional view showing a method of manufacturing a semiconductor element of Embodiment 1.

[0025] Fig.12 It is a cross-sectional view of a semiconductor element of Embodiment 2.

[0026] Fig.13 It is a cross-sectional view showing a method of manufacturing a semiconductor element of Embodiment 2.

[0027] Fig.14 It is a cross-sectional view showing a method of manufacturing a semiconductor element of Embodiment 2.

[0028] Fig.15 It is a cross-sectional view showing a method of manufacturing a semiconductor element of Embodiment 2.

[0029] (Reference Signs)

[0030] 1: Semiconductor substrate; 2: Circuit element; 3: Electrode protection layer; 4: Transparent substrate; 5: Release layer; 6: Metal thin film; 7: Circuit element substrate; 8: Support substrate; 9: Vacuum chamber; 10: Transfer substrate; 11: Inorganic insulating film; 12: Sputtering target; 101, 102: Semiconductor elements. Detailed Embodiments

[0031] <A. Embodiment 1>

[0032] <A-1. Structure>

[0033] Figure 1It is a cross-sectional view showing the structure of the semiconductor element 101 of Embodiment 1. The semiconductor element 101 includes a circuit element 2 and a transfer substrate 10. The transfer substrate 10 is bonded to the lower surface of the circuit element 2. In the following description, the circuit element 2 is a HEMT (high electron mobility transistor) having gallium nitride (GaN) as a semiconductor layer, but it may also be other circuit elements such as a MOSFET (metal-oxide-semiconductor field-effect transistor) or an IGBT (insulated gate bipolar transistor). The thickness of the circuit element 2 is, for example, 10 μm. The transfer substrate 10 is a substrate with high thermal conductivity, for example, a diamond substrate.

[0034] <A-2. Manufacturing process>

[0035] Figure 2 It is a flowchart showing the manufacturing method of the semiconductor element 101. Hereinafter, the manufacturing method of the semiconductor element 101 will be described according to the Figure 2 following process.

[0036] First, as Figure 3 shown, a circuit element substrate 7 is prepared. The circuit element substrate 7 includes a semiconductor substrate 1 and a circuit element 2 formed on the semiconductor substrate 1. The semiconductor substrate 1 is, for example, a Si wafer or a SiC (silicon carbide) wafer, etc.

[0037] The circuit element 2 includes a hollow bridge electrode that connects electrodes. Although not shown in Figure 3 , there are steps caused by the electrodes on the upper surface of the circuit element 2. In order to prevent damage to the electrodes in the subsequent grinding process, it is necessary to form a protective layer on the circuit element 2. Therefore, as Figure 4 shown, an electrode protective layer 3 is coated on the circuit element 2 (step S1). Regarding the electrode protective layer 3, in addition to protecting the electrodes of the circuit element 2 in the subsequent grinding process, by flattening the unevenness of the electrodes, it also has the effect of improving the bonding strength with the support substrate.

[0038] As the material of the electrode protection layer 3, an adhesive or photoresist material composed of an organic solvent and a thermosetting resin or a photocuring resin is selected, and a material that can be removed by chemical treatment or oxygen ashing in the final process is selected. Generally speaking, acrylic resin, olefin resin, phenolic resin, polypropylene resin or polyethylene resin is used for the electrode protection layer 3. In the electrode protection layer 3, a material with high substrate strength that integrates the circuit element substrate 7 and the support substrate and does not peel off or crack during the grinding process is effective. From this point of view, a material with high film strength such as acrylic resin or epoxy resin is preferred.

[0039] In coating the electrode protection layer 3, for example, a spin coating method is used in which an adhesive is dripped onto the main surface of the circuit element substrate 7 on which the circuit element 2 is formed, and the circuit element substrate 7 is rotated at high speed. However, other coating methods such as printing or spraying may also be used. The electrode protection layer 3 is formed in a thickness of not less than 5 μm and not more than 8 μm so as to cover the circuit element 2. After the electrode protection layer 3 is applied to the circuit element 2, the electrode protection layer 3 is hardened. In the case where a thermosetting resin is used as the material of the electrode protection layer 3, the electrode protection layer 3 is heated to not less than 90°C and not more than 120°C by a heating plate or the like, whereby the solvent component evaporates and hardens. In the case where a photocurable resin is used as the material of the electrode protection layer 3, the electrode protection layer 3 is hardened by irradiating the circuit element substrate 7 with light.

[0040] Next, if Figure 5 As shown, a peeling layer 5 is formed on the bonding surface of the transparent substrate 4 to prepare the support substrate 8 (step S2). That is, the support substrate 8 includes a transparent substrate 4 and a peeling layer 5 formed on the transparent substrate 4. The transparent substrate 4 has light transmittance and is composed of alkali-free glass or sapphire glass. When the support substrate 8 is peeled off from the circuit element substrate 7 in the subsequent process, it takes time if a method such as etching, grinding or immersion in a peeling liquid is used. Therefore, in this embodiment, a peeling layer 5 composed of a photodegradable material that decomposes when absorbing light such as laser or infrared rays is formed on the transparent substrate 4. For example, a paste composed of a resin and an organic solvent containing a carbon material that absorbs light and generates heat and performs thermal decomposition is applied to the transparent substrate 4 by a spin coating method, and heated and dried to form the peeling layer 5. Alternatively, a carbon film with a thickness of 1 μm or more and 2 μm or less can be formed on the transparent substrate 4 by a CVD sputtering device as the peeling layer 5. When a carbon film is used for the peeling layer 5, the support substrate 8 can be firmly bonded to the circuit element substrate 7.

[0041] The surface of the peeling layer 5 is preferably mirror-finished by polishing. The arithmetic mean roughness of the surface of the peeling layer 5 is preferably less than 0.5 nm, more preferably less than 0.2 nm. If the arithmetic mean roughness of the surface of the peeling layer 5 is less than 0.5 nm, the portion that is not bonded to the circuit element substrate 7 can be reduced in the subsequent process, and the bonding strength to the circuit element substrate 7 becomes higher.

[0042] Next, if Figure 6 As shown, a circuit element substrate 7 and a support substrate 8 are arranged in a vacuum chamber 9, and the vacuum chamber 9 is evacuated to an ultra-high vacuum 10. -6 Pa. In this ultra-high vacuum state, a metal thin film 6 is formed with a thickness of several nm to several tens of nm on the electrode protection layer 3 of the circuit element substrate 7 and the release layer 5 of the support substrate 8 by sputtering or evaporation (step S3). Figure 6 The figure shows a state where sputtered atoms are emitted from the sputtering target 12 onto the electrode protection layer 3. As a material of the metal thin film 6, aluminum, copper, silicon, titanium, gold, silver, iron, chromium, or the like is used.

[0043] Then, the metal film 6 is pasted to each other in the vacuum chamber 9 to join the circuit element substrate 7 and the support substrate 8 (step S4). In the same vacuum chamber 9, the formation of the metal film 6 (step S3) and the joining of the circuit element substrate 7 and the support substrate 8 (step S4) are continuously performed. When the circuit element substrate 7 and the support substrate 8 are taken out into the atmosphere after the metal film 6 is formed, moisture, natural oxide film or organic matter will adhere to the surface, and the metal films 6 will not join to each other. Therefore, in order to make the circuit element substrate 7 and the support substrate 8 stick together, it is necessary to irradiate the circuit element substrate 7 and the support substrate 8 with an ion beam or a neutral atom beam in a vacuum again to clean them. On the other hand, in the present embodiment, the metal film 6 is formed on the circuit element substrate 7 and the support substrate 8 in a vacuum, and then the atomic diffusion bonding method for pasting the metal film 6 to each other is used in the vacuum, so there is no need for surface activation implemented by atomic beams, etc. Therefore, there is no loss in the process, and the process time of the bonding process (steps S3 and S4) can be shortened by 10 minutes to 15 minutes. Therefore, if a cassette capable of arranging a plurality of wafers at a time is used and a loadlock chamber as a preliminary exhaust chamber is provided in the vacuum chamber 9, the processing time can be shortened compared to the substrate pasting process using a general adhesive.

[0044] In the prior art of using wax or thermosetting or photocurable resin in the bonding of the circuit element substrate 7 and the support substrate 8, the thickness of the resin film will be as thick as several hundred μm or more to several mm, and the elastic modulus of the resin film is small. Therefore, the strength of the substrate after bonding is low, and when the circuit element substrate 7 is polished and thinned, cracks may occur in the peripheral part of the circuit element substrate 7, or the circuit element substrate 7 may peel off from the support substrate 8. However, according to the atomic diffusion bonding method of this embodiment, the thickness of the bonding layer can be made very thin, about 0.2nm to 20nm per atomic weight. In addition, in the atomic diffusion bonding method, the atoms on the surfaces of the two substrates to be bonded will diffuse into each other, so the bonding force is strong and the mechanical strength of the bonded substrate becomes high. Therefore, defects such as cracks, peeling or breakage during grinding or cutting will be reduced. In addition, according to the atomic diffusion bonding method, bonding is performed at room temperature, so the substrate will not expand and deform due to heating. Therefore, the material of the substrate to be bonded can be arbitrary.

[0045] Next, if Figure 7 As shown, the surface of the circuit element substrate 7 side of the bonding substrate composed of the circuit element substrate 7 and the supporting substrate 8 is polished to remove the semiconductor substrate 1 (step S5). The reason for removing the semiconductor substrate 1 is to improve the heat dissipation efficiency of the circuit element 2 and achieve low power consumption and high output. In this step, the semiconductor substrate 1 with a thickness of 500μm is first polished to a thickness of 20μm. As a polishing method, mechanical polishing, chemical polishing or chemical mechanical polishing is used. Next, the remaining semiconductor substrate 1 with a thickness of 20μm is removed by dry etching such as reactive ion etching (Reactive Ion Etching: RIE). As a result, the semiconductor substrate 1 is completely removed to expose the lower surface of the circuit element 2. Thereafter, chemical mechanical polishing is performed to achieve the flatness of the lower surface of the circuit element 2. Considering the subsequent bonding with the transfer substrate 10, the arithmetic mean roughness Ra of the lower surface of the circuit element 2 is preferably less than 0.5nm.

[0046] As the semiconductor substrate 1 gradually becomes thinner due to grinding, the strength of the circuit element substrate 7 including the circuit element 2 decreases. As a result, the circuit element 2 is deformed due to the influence of the stress of the residual film, or cracks or peeling occur in the peripheral portion of the circuit element 2 due to uneven grinding. However, in this embodiment, since the semiconductor substrate 1 is ground while the circuit element substrate 7 is firmly bonded to the support substrate 8, the strength of the circuit element substrate 7 can be ensured even if the semiconductor substrate 1 is removed. Therefore, defects such as deformation, cracking, or peeling of the circuit element 2 are suppressed.

[0047] Next, if Figure 8As shown, the lower surface of the circuit element 2 is bonded to the transfer substrate 10 (step S6). As the transfer substrate 10, for example, a diamond substrate with excellent thermal conductivity is used. The thickness of the transfer substrate 10 is 100 μm, and the arithmetic mean roughness of the bonding surface is less than 0.5 nm by precision grinding. In the bonding of the transfer substrate 10, the same atomic diffusion bonding method as the bonding of the support substrate 8 described above is used. The thermal expansion coefficient of the diamond constituting the transfer substrate 10 is 2.3×10 -6 / K, the thermal expansion coefficient of gallium nitride constituting the circuit element 2 is 5.5×10 -6 / K and has a large difference. Therefore, it is difficult to heat and bond the transfer substrate 10 to the circuit element 2. On the other hand, by directly bonding the circuit element 2 and the transfer substrate 10 using a very thin metal film of a few nm, the thermal resistance of the bonding interface is small and a high heat dissipation effect can be obtained. Alternatively, after irradiating the bonding surface with a neutral atomic beam to remove the natural oxide film or organic substance, the circuit element 2 and the transfer substrate 10 can be bonded using a surface activation method that allows the adhesive to be attached. In this case, the bonding surface of the circuit element 2 and the transfer substrate 10 is polished to a surface with an arithmetic mean roughness of less than 0.5 nm.

[0048] Next, if Fig. 9 As shown, the support substrate 8 is peeled off from the circuit element substrate 7 (step S7). Specifically, laser is irradiated from the upper surface of the transparent substrate 4 to heat and decompose the peeling layer 5, thereby peeling off the support substrate 8. According to this method, compared with the method of removing the support substrate 8 by grinding or etching, the number of steps is reduced, the processing time is shortened, and the transparent substrate 4 can be reused, thereby improving productivity and reducing production costs.

[0049] Next, if Fig.10 as well as Fig.11 As shown, dicing is performed to separate the bonded substrate composed of the transfer substrate 10 and the circuit element substrate 7 into a plurality of chips (step S8). Fig.11 A chip after division is shown. A large number of components are formed as the circuit element 2, and each component is divided in this step. As a cutting method, laser cutting or plasma cutting can be used. In the past, due to the decrease in strength associated with thin filming, cracks, peeling or fragments occurred in the circuit element substrate 7 during the cutting process. However, in this embodiment, the strength is increased by directly bonding the circuit element substrate 7 to the support substrate 8, so that the above-mentioned defects are suppressed.

[0050] Next, the metal thin film 6 and the electrode protective layer 3 are peeled off from the individualized chip (step S9). In this step, the circuit element substrate 7 is immersed in an alkaline or acidic stripping solution, an organic solvent, or the like, and the metal thin film 6 and the electrode protective layer 3 are removed by dissolution. Then, the remaining organic matter is washed, and the circuit element substrate 7 is dried. Alternatively, the metal thin film 6 can be removed with an acidic stripping solution, and the electrode protective layer 3 can be removed by oxygen ashing. Thus, the Figure 1 semiconductor element 101 shown is completed.

[0051] <A-3. Effects>

[0052] As described above, according to the method for manufacturing a semiconductor element of Embodiment 1, a circuit element substrate 7 including a semiconductor substrate 1 and a circuit element 2 on the semiconductor substrate 1 is prepared. An electrode protective layer 3 is formed on the circuit element 2. A support substrate 8 is prepared. A metal thin film 6 is formed on the electrode protective layer 3 of the circuit element substrate 7 and on the support substrate 8 in a vacuum. The circuit element substrate 7 and the support substrate 8 are bonded to each other by the atomic diffusion bonding method so that the metal thin films 6 of the circuit element substrate 7 and the support substrate 8 are bonded to each other. Thus, the circuit element substrate 7 and the support substrate 8 are bonded. The semiconductor substrate 1 is polished and removed to expose the circuit element 2. A transfer substrate 10 is bonded to the exposed surface of the circuit element 2. After bonding the transfer substrate 10, the support substrate 8 is peeled off from the circuit element 2. Since the metal thin films 6 of the circuit element substrate 7 and the support substrate 8 are firmly bonded to each other by the atomic diffusion bonding method, the mechanical strength of the bonded substrate obtained by bonding the circuit element substrate 7 and the support substrate 8 is high. Therefore, even if the semiconductor substrate 1 is polished to thin the semiconductor element, the circuit element 2 is not likely to have defects such as cracks, peeling, or breakage, and the defect rate can be reduced.

[0053] <B. Embodiment 2>

[0054] <B-1. Structure>

[0055] Fig.12 is a cross-sectional view of a semiconductor element 102 according to Embodiment 2. The semiconductor element 102 includes a circuit element 2, an inorganic insulating film 11 formed on the upper surface of the circuit element 2, and a transfer substrate 10 formed on the lower surface of the circuit element 2. The circuit element 2 and the transfer substrate 10 are as described in Embodiment 1. The inorganic insulating film 11 is an electrode protective layer. However, a resin is used for the electrode protective layer 3 in Embodiment 1, whereas in Embodiment 2, an inorganic insulating film having high thermal conductivity is used as the electrode protective layer, and thus it is referred to as the inorganic insulating film 11.

[0056] When an inorganic insulating film is used in the electrode protective layer, compared with the case of using resin, the strength of the bonding substrate of the circuit element substrate 7 and the support substrate 8 is improved, and cracks or peeling after polishing of the semiconductor substrate 1 can be suppressed. However, it is difficult to remove the electrode protective layer in the final process, and the damage to the circuit element 2 during removal is also large. Therefore, in the semiconductor element 102, instead of removing the inorganic insulating film 11, it is used as a heat dissipation material on the upper surface side of the circuit element 2, thereby improving the heat dissipation performance of the semiconductor element 102 and omitting the removal process of the inorganic insulating film 11. In this way, since the inorganic insulating film 11 is used as a heat dissipation material, the inorganic insulating film 11 becomes an inorganic insulating film having high thermal conductivity.

[0057] <B-2. Manufacturing process>

[0058] Figures 13 to 15 It is a cross-sectional view showing a case where an inorganic insulating film 11 as an electrode protective layer is formed on the circuit element 2 of the circuit element substrate 7. Fig.13 It shows the circuit element substrate 7 including the semiconductor substrate 1 and the circuit element 2 on the semiconductor substrate 1. In the circuit element 2, there is a hollow bridge electrode for connecting electrodes, so as Fig.13 shown, a step is formed on the upper surface of the circuit element 2. The height of this step is on the order of several μm.

[0059] The circuit element substrate 7 is put into a film forming apparatus such as a CVD plasma apparatus, and as Fig.14 shown, an inorganic insulating film 11 having high thermal conductivity is formed on the circuit element 2 with a film thickness above the height of the electrodes in the circuit element 2. As the material of the inorganic insulating film 11, diamond, aluminum nitride, silicon nitride, beryllium oxide, etc. can be used. By using the inorganic insulating film 11 with high thermal conductivity as the electrode protective layer, the electrode protective layer can be used as a radiator on the upper surface side of the circuit element 2, so the removal process of the electrode protective layer is not required. Therefore, shortening of the process and improvement of equipment performance can be achieved.

[0060] In addition, even if it is an insulating film, silicon oxide etc. with low thermal conductivity is difficult to be used as the material of the inorganic insulating film 11 because of its low heat dissipation performance and its adverse effect on equipment performance, so it must be removed in the final process, and the circuit element 2 will be damaged during the removal process.

[0061] Since the electrode protective layer 3 of Embodiment 1 is resin, by using the spin coating method, the resin flows and the upper surface of the electrode protective layer 3 is formed flat. However, in the case of forming the inorganic insulating film 11 by the CVD method etc., as Fig.14A step is generated on the upper surface of the inorganic insulating film 11. In order to obtain a strong bonding strength between the circuit element substrate 7 and the support substrate 8, it is necessary to planarize the upper surface of the inorganic insulating film 11 and bond the entire upper surface of the inorganic insulating film 11 to the support substrate 8. Therefore, as Fig.15 shown, the high portion of the inorganic insulating film 11 is planarized to the same height as the electrode of the circuit element 2 by a grinding method. The arithmetic mean roughness of the upper surface of the inorganic insulating film 11 at this time is 1.0 nm or less.

[0062] Next, after washing the upper surface of the inorganic insulating film 11 to remove the grinding residue, the formation of the metal thin film 6 (step S3), the bonding of the circuit element substrate 7 (step S4) and the support substrate 8 (step S5), the grinding of the semiconductor substrate 1 (step S6), the bonding of the transfer substrate 10 (step S7), the peeling of the support substrate 8 (step S8), and the dicing of the circuit element 2 (step S9) are performed in the same manner as in the first embodiment. Then, the metal thin film 6 is removed from the upper surface of the inorganic insulating film 11 to complete Fig.12 the semiconductor element 102 shown. The inorganic insulating film 11 remains on the upper surface of the circuit element 2 and functions as a heat sink.

[0063] <B-3. Effects>

[0064] In the method for manufacturing a semiconductor element according to the second embodiment, the electrode protection layer formed on the upper surface of the circuit element 2 is the inorganic insulating film 11 made of an inorganic insulating material. Therefore, compared with the case where a resin is used for the electrode protection layer, the strength of the bonding substrate between the circuit element substrate 7 and the support substrate 8 is improved, and cracks or peeling after grinding of the semiconductor substrate 1 can be suppressed. In addition, when the inorganic insulating film 11 is an inorganic insulating film with a high thermal conductivity, not only can the inorganic insulating film 11 be used as an electrode protection layer, but also as a heat dissipation material on the upper surface side of the circuit element 2. Therefore, the heat dissipation performance of the semiconductor element 102 can be improved, and the removal process of the electrode protection layer can be omitted.

[0065] In addition, the respective embodiments can be freely combined, or the respective embodiments can be appropriately modified or omitted. The above description is only an example in all aspects. It should be understood that countless modification examples not illustrated can be conceived.

Claims

1. A method for manufacturing a semiconductor element, wherein: preparing a circuit element substrate including a semiconductor substrate and a circuit element on the semiconductor substrate, forming an electrode protection layer on the circuit element, Prepare the support substrate, forming a metal thin film on the electrode protection layer of the circuit element substrate and on a support substrate in a vacuum, The circuit element substrate and the support substrate are bonded together by bonding the metal thin films of the circuit element substrate and the support substrate by an atomic diffusion bonding method, The semiconductor substrate is removed by grinding to expose the circuit element. A transfer substrate is bonded to the exposed surface of the circuit element. After the transfer substrate is bonded, the support substrate is peeled off from the circuit element. The formation of the metal thin film and the bonding of the circuit element substrate and the support substrate are continuously performed in the same vacuum chamber.

2. The method for manufacturing a semiconductor element according to claim 1, wherein: The supporting substrate includes a transparent substrate and a peeling layer formed on the transparent substrate and made of a photodegradable material. The metal thin film is formed on the peeling layer of the supporting substrate, The support substrate is peeled off by photodecomposing the peeling layer.

3. The method for manufacturing a semiconductor element according to claim 2, wherein: The peeling layer is composed of a carbon film, The support substrate is peeled off by irradiating the release layer with laser light from the lower surface of the transparent substrate to thermally decompose the release layer.

4. The method for manufacturing a semiconductor element according to any one of claims 1 to 3, wherein: The electrode protection layer is made of acrylic resin or epoxy resin.

5. The method for manufacturing a semiconductor element according to any one of claims 1 to 3, wherein: The electrode protection layer is made of inorganic insulating material.

6. The method for manufacturing a semiconductor element according to claim 5, wherein: The inorganic insulating material is any material selected from the group consisting of diamond, aluminum nitride, silicon nitride and beryllium oxide.

7. The method for manufacturing a semiconductor element according to any one of claims 1 to 6, wherein: The circuit element comprises gallium nitride as a semiconductor layer, The transfer substrate is made of diamond.

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