Nitride semiconductor device

Abstract

A nitride semiconductor device includes an electron tunneling layer, an electron supply layer formed on the electron tunneling layer, an active layer formed on the electron supply layer and containing Al 1‑x Ga x N(0

Description

TECHNICAL FIELD

[0001] The present application relates to a nitride semiconductor device. BACKGROUND

[0002] For example, Patent Literature 1 discloses a HEMT including a support substrate, a buffer layer on the support substrate, an electron tunneling layer on the buffer layer, an electron supply layer on the electron tunneling layer, a gate recess formed in the electron supply layer and reaching the electron tunneling layer, an insulating film formed on a wall surface of the gate recess and the electron supply layer, a gate electrode buried in the insulating film, and a source electrode and a drain electrode formed in ohmic contact with the electron supply layer and electrically connected to a two-dimensional electron gas layer via the electron supply layer.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2014-207287 SUMMARY

[0006] Method for solving the problem

[0007] A nitride semiconductor device of one embodiment of the present application includes an electron tunneling layer, an electron supply layer formed over the electron tunneling layer, a gate layer including a material containing Al 1-x Ga x N (0 < X < 1) containing a first impurity, a gate electrode formed over the gate layer and in Schottky junction with the gate layer, and a source electrode and a drain electrode electrically connected to the electron supply layer. BRIEF DESCRIPTION OF DRAWINGS

[0008] [ Figure 1 ] Figure 1 is a schematic plan view of a nitride semiconductor device of one embodiment of the present application.

[0009] [ Figure 2 ] Figure 2 is a schematic plan view of the internal structure of the nitride semiconductor device of Figure 1 .

[0010] [ Figure 3 ] Figure 3 is a view of a III-III cross section of Figure 2 .

[0011] [ Figure 4 ] Figure 4 is a main part enlarged view of a portion enclosed by the double-dotted line IV of Figure 3 .

[0012] [Figure 5 ] Figure 5 is a graph for explaining Figure 4 a modification example of the gate structure.

[0013] [ Figure 6 ] Figure 6 is a graph for comparing Al composition ratios of the electron supply layer and the gate layer.

[0014] [ Figure 7 ] Figure 7 is a graph for explaining a distribution of Al composition ratios of the gate layer.

[0015] [ Figure 8 ] Figure 8 is a graph for explaining a distribution of Al composition ratios of the gate layer.

[0016] [ Figure 9 ] Figure 9 is a graph showing a relationship between a gate voltage and an insulation breakdown time (tBD) of Sample 1 and Sample 2.

[0017] [ Figure 10 ] Figure 10 is a graph showing a relationship between an electric field intensity and an insulation breakdown time (tBD) of Sample 1 and Sample 2. DETAILED DESCRIPTION

[0018] <Embodiment of the Present Disclosure>

[0019] First, an embodiment of the present disclosure will be explained.

[0020] A nitride semiconductor device of one embodiment of the present application includes an electron tunneling layer, an electron supply layer formed over the electron tunneling layer, a gate layer including an Al 1-x Ga x N (0 < X < 1) system material containing a first impurity, a gate electrode formed over the gate layer and in Schottky junction with the gate layer, and a source electrode and a drain electrode electrically connected to the electron supply layer.

[0021] A nitride semiconductor device of one embodiment of the present application can include an electron tunneling layer, an electron supply layer formed over the electron tunneling layer, a gate layer including a semi-insulating material of an Al 1-x Ga x N (0 < X < 1) system, a gate electrode formed over the gate layer and in Schottky junction with the gate layer, and a source electrode and a drain electrode electrically connected to the electron supply layer.

[0022] The nitride semiconductor device according to one embodiment of the present application can improve gate withstand voltage, and thus can provide a nitride semiconductor device with high reliability. Also, since the gate electrode is in Schottky junction with the gate layer, gate leakage current can be reduced.

[0023] In the nitride semiconductor device according to one embodiment of the present application, the gate electrode can include at least one of TiN, Ti, Al, W, Mo, and TaN.

[0024] In the nitride semiconductor device according to one embodiment of the present application, the first impurity can include at least one of Mg and Zn.

[0025] In the nitride semiconductor device according to one embodiment of the present application, the gate layer can have a thickness of 60 nm or more and have an Al composition ratio of 3 x 10 18 cm -3 The above-described first impurity has a concentration of 1 x 1019 / cm3or more.

[0026] In the nitride semiconductor device according to one embodiment of the present application, the gate layer can have a thickness of 100 nm or more.

[0027] In the nitride semiconductor device according to one embodiment of the present application, the electron tunneling layer can include a GaN-based material, the electron supply layer can include an Al 1-x Ga x N (0 < X < 1)-based material, and the gate layer can have an Al composition ratio smaller than that of the electron supply layer.

[0028] In the nitride semiconductor device according to one embodiment of the present application, the gate layer can include a first portion having a relatively small Al composition ratio and a second portion formed on the opposite side of the electron supply layer from the first portion and having a relatively large Al composition ratio than the first portion, and an average Al composition ratio of the first portion and the second portion can be smaller than that of the electron supply layer.

[0029] In the nitride semiconductor device according to one embodiment of the present application, the Al composition ratio of the gate layer can increase linearly or stepwise from the electron supply layer toward the gate electrode.

[0030] The nitride semiconductor device according to one embodiment of the present application can include a mesa structure portion having a wall surface inclined with respect to a surface of the electron supply layer and continuously spanning the gate layer and the gate electrode.

[0031] In the nitride semiconductor device according to one embodiment of the present application, the gate electrode can have a smaller thickness than the gate layer.

[0032] In the nitride semiconductor device of one embodiment of the present application, the gate electrode can be formed in the inner side region of the gate layer so as to form a step difference between the side surface of the gate layer and the side surface of the gate electrode.

[0033] In the nitride semiconductor device of one embodiment of the present application, the gate electrode can have a larger thickness than the gate layer.

[0034] <Detailed description of embodiments of the present disclosure>

[0035] Next, embodiments of the present disclosure are described in detail with reference to drawings.

[0036] Planar structure of nitride semiconductor device 1

[0037] Figure 1 is a schematic plan view of a nitride semiconductor device 1 of one embodiment of the present application. Figure 2 is a schematic plan view of the internal structure of the nitride semiconductor device 1 of Figure 1 .

[0038] As illustrated in Figure 1 , the nitride semiconductor device 1 can be a chip formed into a quadrangle in plan view. In this embodiment, the nitride semiconductor device 1 is formed into a square in plan view, and for example, successively has a first side 11, a second side 12, a third side 13, and a fourth side 14 in the clockwise direction.

[0039] The length LI of the first side 11 and the third side 13 of the nitride semiconductor device 1 can be, for example, 0.5 mm to 10 mm, and the length L2 of the second side 12 and the fourth side 14 can be, for example, 0.5 mm to 10 mm.

[0040] An active region 2 is formed in the substantially central portion of the nitride semiconductor device 1. As illustrated in Figure 2 , the active region 2 has a structure in which a group of a gate electrode 3 and source and drain electrodes 4 and 5 arranged so as to sandwich the gate electrode 3 from both sides is taken as one unit, and the units are arranged in parallel to each other in parallel.

[0041] More specifically, the source and drain electrodes 4 and 5 extend in the X direction. The gate electrode 3 includes a plurality of electrode portions 6 extending in the X direction in parallel to each other and two base portions 7 which connect corresponding end portions of the plurality of electrode portions 6 to each other, respectively.

[0042] In Figure 2In the example of FIG. 1, the source electrode 4 (S), the electrode portion 6 (G) of the gate electrode 3, and the drain electrode 5 (D) are periodically arranged in the Y direction in the order of DGSGDGS. Thus, the element structure is configured by sandwiching the electrode portion 6 (G) of the gate electrode 3 with the source electrode 4 (S) and the drain electrode 5 (D). The region of the surface of the semiconductor stacked structure 28 (described later) is composed of the active region 2 including the element structure and the non-active region 8 other than the active region 2. In the active region 2, the element structure is arranged in the order of SGS. Figure 2 In FIG. 1, the reference numeral 9 denotes an element isolation line as a boundary line between the active region 2 and the non-active region 8. The base portion 7 of the gate electrode 3 links corresponding end portions of the plurality of electrode portions 6 to each other in the non-active region 8.

[0043] In the present embodiment, the active region 2 is a rectangle in plan view when viewed in the direction along the first side 11 and the third side 13, and has a length substantially equal to the length LI of the first side 11.

[0044] As electrodes drawn from the source electrode 4, the gate electrode 3, and the drain electrode 5 of each unit of the active region 2, the source electrode film 10, the gate electrode film 15, and the drain electrode film 16 are arranged. As the source electrode film 10, the gate electrode film 15, and the drain electrode film 16, for example, a metal film such as an Al film can be applied. Note that the source electrode film 10, the gate electrode film 15, and the drain electrode film 16 can be referred to as a source metal, a gate metal, and a drain metal, respectively, based on the constituent material, or can be simply referred to as a source electrode, a gate electrode, and a drain electrode, respectively, based on the functional surface.

[0045] The source electrode film 10 is arranged on the first side 11 side with respect to the active region 2. In the present embodiment, the source electrode film 10 is formed in a rectangle in plan view having a width narrower than the active region 2.

[0046] In the region on the nitride semiconductor device 1, a region 17 composed of a step difference formed by the difference between the width of the active region 2 and the source electrode film 10 is formed. As shown in FIG. 1, the region 17 can be formed in the intersection of the first side 11 and the second side 12 of the nitride semiconductor device 1. Figure 1 As shown in FIG. 1, the region 17 can be formed in the intersection of the first side 11 and the second side 12 of the nitride semiconductor device 1.

[0047] The gate electrode film 15 is arranged in the region 17 (in the present embodiment, the intersection of the first side 11 and the second side 12 of the nitride semiconductor device 1) formed by the step difference between the active region 2 and the source electrode film 10, and is formed in a quadrangle in plan view.

[0048] The drain electrode film 16 is disposed between the active region 2 and the third side 13 of the nitride semiconductor device 1, and is formed into a rectangle with a width approximately equal to the length L1 of the first side 11 when viewed from a plane. That is, the drain electrode film 16 can also be formed into a rectangle that is longer along the direction of the first side 11 and the third side 13.

[0049] Furthermore, the source electrode film 10, the gate electrode film 15, and the drain electrode film 16 are covered by a surface insulating film 18. For example, SiN can be used as the surface insulating film 18. Openings 22, 23, and 24 are formed in the surface insulating film 18, exposing portions of the source electrode film 10, the gate electrode film 15, and the drain electrode film 16 as source pads 19, gate pads 20, and drain pads 21, respectively.

[0050] The source pad 19 is formed, for example, in a generally elliptical shape along the first side 11 near the first side 11 of the nitride semiconductor device 1. Figure 1 As shown, the generally elliptical source pad 19 can also be a shape comprising a pair of straight lines that are opposite each other along the first side 11 in the direction that intersects the first side 11 and a semicircle that connects the ends of the pair of sides to each other.

[0051] The gate pad 20 is arranged at a distance from the source pad 19 along the first side 11 of the semiconductor nitride device 1. That is, the source pad 19 and the gate pad 20 can be arranged side by side along the first side 11 of the semiconductor nitride device 1. In addition, the shape of the gate pad 20, like that of the source pad 19, can be a generally elliptical shape along the first side 11.

[0052] The drain pad 21 is formed, for example, in a generally elliptical shape along the third side 13 near the third side 13 of the nitride semiconductor device 1. Figure 1 As shown, the generally elliptical drain pad 21 can be a shape comprising a pair of straight lines opposing each other along the third side 13 in the direction intersecting the third side 13, and a semicircle connecting the ends of the pair of sides to each other. In this embodiment, the length of the pair of straight lines can be approximately equal to the length L1 of the first side 11 of the nitride semiconductor device 1. In this case, the drain pad 21 can be opposite both the source pad 19 and the gate pad 20 in the direction intersecting the first side 11.

[0053] It should be noted that the above example is just one example regarding the shape, configuration, and number of the source pad 19, gate pad 20, and drain pad 21, and can be appropriately changed according to the design.

[0054] Cross-sectional structure of nitride semiconductor device 1

[0055] Figure 3 It meansFigure 2 Diagram of section III-III. Figure 4 It is by Figure 3 Enlarged view of the main part enclosed by the double-dotted line IV. Figure 5 It is used for explanation Figure 4 A diagram showing a modified example of the gate structure.

[0056] The nitride semiconductor device 1 includes a substrate 27 having a first surface 25 and a second surface 26 opposite to the first surface 25, and a semiconductor stack-up structure 28 formed on the first surface 25 of the substrate 27.

[0057] As the substrate 27, insulating substrates such as sapphire substrates, semiconductor substrates such as Si substrates, SiC substrates, and GaN substrates can be used. In this embodiment, the substrate 27 is a Si substrate. Furthermore, the thickness of the substrate 27 can be, for example, 400 μm to 1000 μm. It should be noted that the first surface 25 and the second surface 26 of the substrate 27 can also be referred to as the surface and back surface of the substrate 27, respectively. Furthermore, the second surface 26 of the substrate 27 can also be an exposed surface where no electrodes or semiconductor laminate structures are formed.

[0058] The semiconductor stack structure 28 is a stack structure composed of multiple semiconductor layers with different compositions. In this embodiment, the semiconductor stack structure 28 sequentially includes a buffer layer 29, an electron transit layer 30, and an electron supply layer 31 from the side closest to the first surface 25 of the substrate 27. These layers 29 to 31 can also be formed by epitaxially growing raw materials on the first surface 25 of the substrate 27.

[0059] As the buffer layer 29, any buffer layer capable of mitigating the lattice mismatch between the electron transit layer 30 and the substrate 27 is acceptable, without particular limitation. The buffer layer 29 may also be a multilayer buffer layer formed by stacking multiple nitride semiconductor layers. In this embodiment, the buffer layer 29 includes a first buffer layer 32 composed of an AlN layer in contact with the first surface 25 of the substrate 27 and a second buffer layer 33 composed of an AlGaN layer stacked on the first buffer layer 32. The thickness of the first buffer layer 32 may be, for example, about 50 nm to 500 nm. The thickness of the second buffer layer 33 may be, for example, larger than that of the first buffer layer 32, about 50 nm to 2000 nm. The buffer layer 29 may be a single layer of AlN or a single layer of AlGaN.

[0060] As the electron transition layer 30, an undoped nitride semiconductor can be used, specifically, it can be made of undoped Al. 1-x Ga xA layer composed of an N(0 < X ≤ 1) system material. The so-called undoped nitride semiconductor layer, for example, refers to a semiconductor layer formed without intentionally doping impurities during the crystal growth of the electron transit layer 30. In addition to Al, Ga, and N that make up the electron transit layer 30, several other elements may also be inadvertently mixed in.

[0061] In addition, the thickness of the electron transit layer 30 is, for example, 0.3 μm or less, and may also be 0.01 μm or more. It should be noted that the electron transit layer 30 is a layer that forms the two-dimensional electron gas 34 described later and forms the channel of the nitride semiconductor device 1, and thus can also be called the channel layer.

[0062] As the electron supply layer 31, for example, a layer composed of Al with a composition ratio different from that of the electron transit layer 30 can be applied. 1-x Ga x A layer composed of an N(0 ≤ X < 1) system material. For example, the electron transit layer 30 can be a GaN layer and the electron supply layer 31 can be an AlGaN layer. In addition, for example, if the electron supply layer 31 is AlGaN, the thickness of the electron supply layer 31 can be 5 nm to 100 nm, and if the electron supply layer 31 is AlN, the thickness of the electron supply layer 31 can be 1 nm to 5 nm. It should be noted that the electron supply layer 31 can also be called the blocking layer.

[0063] In this way, the electron transit layer 30 and the electron supply layer 31 are composed of nitride semiconductors with different Al composition ratios, and a lattice mismatch occurs between them. Moreover, due to the polarization caused by this lattice mismatch, the two-dimensional electron gas 34 caused by this polarization expands at a position close to the interface between the electron transit layer 30 and the electron supply layer 31 (for example, at a position at a distance of several degrees of distance from the interface).

[0064] A gate layer 35 is formed on the semiconductor stack structure 28, and a gate electrode 3 is formed on the gate layer 35.

[0065] The gate layer 35 is selectively formed on a part of the surface 37 of the electron supply layer 31. The gate layer 35 is composed of Al 1- x Ga x N(0 < X < 1) system material. In this embodiment, the gate layer 35 contains at least one of Mg and Zn as an example of the first impurity of the present disclosure as an impurity. The Al 1-x Ga x N(0 < X < 1) system material of the gate layer 35 can also be a semi-insulating material. A semi-insulating material can be defined as when forming the gate layer 35, while doping the above impurities, Al 1-x Ga xN (0 < X < 1) system material is epitaxially grown without performing an annealing process for activating the impurity, whereby the impurity is in an inactive state 1-x Ga x N (0 < X < 1) system material.

[0066] In addition, as Figure 4 indicated, the thickness Tl of the gate layer 35 is, for example, 60 nm or more, preferably 60 nm to 165 nm, and further preferably 100 nm to 165 nm. In addition, the impurity concentration (total concentration of both Mg and Zn in the case of containing both) of the gate layer 35 is, for example, 3 x 10 18 cm -3 - 5 x 10 18 cm -3 - 5 x 10 20 cm -3 .

[0067] In the nitride semiconductor device 1, the positive polarization charge generated in the vicinity of the hetero interface of the electron supply layer 31 and the electron tunneling layer 30 is canceled by the spontaneous polarization generated in the gate layer 35, and as a result, the two-dimensional electron gas 34 selectively disappears in the region directly below the gate electrode 3. Thus, the two-dimensional electron gas 34 is truncated at the region directly below the gate electrode 3, and the normally-off operation of the nitride semiconductor device 1 is achieved.

[0068] The gate electrode 3 is in Schottky junction with the gate layer 35. As the material of the gate electrode 3, there is no particular limitation as long as it can be in Schottky junction with the gate layer 35. For example, with respect to the gate layer 35 composed of an AlGaN system material, the gate electrode 3 can be at least one of TiN, Ti, Al, W, Mo, and TaN.

[0069] In addition, as Figure 4 indicated, the thickness T2 of the gate electrode 3 is smaller than the thickness Tl of the gate layer 35, and is, for example, 100 nm or more, and preferably 50 nm to 150 nm.

[0070] In addition, in the present embodiment, as Figure 4 indicated, the stacked structure of the gate layer 35 and the gate electrode 3 forms a mesa structure portion 36. The mesa structure portion 36, as Figure 2 indicated in the gate electrode 3 (electrode portion 6) in FIG. 1, extends in a stripe shape with a space therebetween, and can also be referred to as a ridge structure.

[0071] The platform structure 36 has a wall surface 38 that is inclined relative to the surface 37 of the electron supply layer 31. The wall surface 38 continuously spans the gate layer 35 and the gate electrode 3. In other words, the side surface 39 of the gate layer 35 and the side surface 40 of the gate electrode 3 are continuous without any step difference in order to form a flat surface, thereby forming the wall surface 38. Thus, the platform structure 36, as Figure 4 As shown, when viewed in cross-section, it can be roughly an isosceles trapezoid with the upper surface 41 of the gate electrode 3 as the upper base and the lower surface 42 of the gate layer 35 as the lower base.

[0072] An insulating layer 43 is formed on the semiconductor stacked structure 28 to cover the gate electrode 3. For example, SiO2 can be used as the insulating layer 43. Furthermore, the thickness of the insulating layer 43 can be, for example, 50 nm to 300 nm.

[0073] Source contact holes 44 and drain contact holes 45 are formed on the insulating layer 43 to expose the electron supply layer 31. Source electrode 4 and drain electrode 5 are formed in the source contact hole 44 and drain contact hole 45, respectively.

[0074] The source electrode 4 is in ohmic contact with the electron supply layer 31. The source electrode 4 may, for example, have a lower layer (e.g., a Ti layer) in ohmic contact with the electron supply layer 31 and an upper layer (e.g., an Al layer) stacked on top of the lower layer. Additionally, the source electrode 4 has an extension 46 extending from the source contact hole 44 toward the drain electrode 5. The extension 46 is formed to cover the gate electrode 3, and has an end 47 between the gate electrode 3 and the drain electrode 5 in a direction along the surface 37 of the electron supply layer 31.

[0075] The drain electrode 5 is in ohmic contact with the electron supply layer 31. The drain electrode 5 may, for example, have a lower layer (e.g., a Ti layer) in ohmic contact with the electron supply layer 31 and an upper layer (e.g., an Al layer) stacked on the lower layer.

[0076] Variations of the gate structure

[0077] Next, refer to Figure 5 A modified example of the gate structure formed by the gate layer 35 and the gate electrode 3 is described.

[0078] exist Figure 4 In this configuration, the gate structure forms a mesa structure 36 that continuously spans the wall 38 of the gate layer 35 and the gate electrode 3. In contrast, the structure is formed by... Figure 5 The mesa structure 48 formed by the gate layer 35 and the gate electrode 3 has a wall surface 50 with a step difference 49 at the boundary between the gate layer 35 and the gate electrode 3. More specifically, the side surface 40 of the gate electrode 3 is formed at a position that is away from the side surface 39 of the gate layer 35 and moves inward toward the gate layer 35. Therefore, the gate electrode 3 is formed in the inner region of the gate layer 35.

[0079] In addition, the side surface 39 of the gate layer 35 and the side surface 40 of the gate electrode 3 are inclined with respect to the surface 37 of the electron supply layer 31, respectively. Further, the side surface 40 of the gate electrode 3 can include a flat surface 51 inclined with respect to the surface 37 of the electron supply layer 31 and a curved surface 52 continuous with the flat surface 51 and bulging toward the inner region of the gate layer 35. For example, the side surface 40 of the lower portion of the gate electrode 3 can be the curved surface 52. The curved surface 52 can also be continuous with the side surface 39 of the gate layer 35.

[0080] In addition, in the terrace structure portion 48, the thickness T2 of the gate electrode 3 can also be greater than the thickness Tl of the gate layer 35. In this case, the thickness Tl of the gate layer 35 can be 50 nm to 150 nm, and the thickness T2 of the gate electrode 3 can be 100 nm to 300 nm.

[0081] Al composition ratio of gate layer 35

[0082] Next, the Al composition ratio of the gate layer 35 will be described in detail with reference to Figures 6-8 to FIG. 6. Figure 6 is a graph for comparing the Al composition ratios of the electron supply layer 31 and the gate layer 35.

[0083] As described above, the electron supply layer 31 can be composed of Al 1-x Ga x N (0 < X < 1) material, and the gate layer 35 can be composed of Al 1-x Ga x N (0 < X < 1) material. Therefore, in the case where the electron supply layer 31 is composed of Al 1-x Ga x N (0 < X < 1) material, both the electron supply layer 31 and the gate layer 35 can be AlGaN layers.

[0084] In this case, the gate layer 35 preferably has an Al composition ratio (average Al composition ratio X4 described later) smaller than the Al composition ratio Xl of the electron supply layer 31. For example, the Al composition ratio Xl of the AlGaN electron supply layer 31 can be 15% to 30%, and the Al composition ratio X4 of the AlGaN gate layer 35 can be 5% to 10%. Thus, the generation of cracks in the gate layer 35 can be suppressed, and the flow of gate leakage current can be prevented.

[0085] The electron supply layer 31 grown from the GaN layer (electron tunnel layer 30) of the substrate with a lattice constant close to that of GaN is an AlGaN layer, but has a lattice constant close to that of GaN at its surface 37. Therefore, by reducing the Al composition ratio of the gate layer 35 to make the crystal structure of the gate layer 35 close to that of GaN, the difference in the lattice constant between the gate layer 35 and the electron supply layer 31 can be reduced. As a result, the strain caused by the difference in the lattice constant can be reduced, and thus the probability of cracks in the gate layer 35 can be lowered.

[0086] In addition, in the present embodiment, as shown in FIG. 1, the gate layer 35 includes a first portion 53 having a relatively small Al composition ratio X2, and a second portion 54 formed on the opposite side of the electron supply layer 31 from the first portion 53 and having a relatively large Al composition ratio X3 compared to the first portion 53. In this case, the average Al composition ratio ((X2+X3) / 2) of the first portion 53 and the second portion 54 can be smaller than the Al composition ratio XI of the electron supply layer 31. In addition, the thickness of the first portion 53 can also be smaller than the thickness of the second portion 54. For example, the thickness of the first portion 53 can be 5 nm to 30 nm, and the thickness of the second portion 54 can be 50 nm to 120 nm. Figure 6 By making the Al composition ratio X2 of the first portion 53 close to the electron supply layer 31 smaller than the Al composition ratio X3 of the second portion 54, the Schottky characteristics of the gate electrode 3 to the gate layer 35 can be stabilized. In addition, the gate layer 35 can be stably formed into a ridge-shaped structure. For example, in the case of selectively etching the gate layer 35, the etching is stopped based on the change in the etching rate. By forming the first portion 53, the etching rate of the first portion 53 and the electron supply layer 31 is greatly different, and thus more accurate etching stop can be performed.

[0087] The first portion 53 and the second portion 54 of the gate layer 35 can be formed, for example, by changing the amount of aluminum raw material gas (e.g., trimethylaluminum (TMAl)) supplied to the chamber of the epitaxial growth device in the epitaxial growth of the gate layer 35. Therefore, a clear boundary can not be formed between the first portion 53 and the second portion 54 of the gate layer 35. For example, in

[0088] in FIG. 4, the boundary portion 55 between the first portion 53 and the second portion 54 of the gate layer 35 is indicated by a broken line, but in fact, it can not be a clear straight line. For example, when performing composition analysis in the thickness direction of the gate layer 35, a certain thickness portion in which the Al composition ratio increases or decreases can be defined as a vague boundary portion. Figure 6 Next, regarding the distribution of the Al composition ratio in the gate layer 35, on the basis of

[0089] Figure 6 Figure 7 and​​Figure 8 A more detailed explanation will be given. Figure 7 and Figure 8 are diagrams for illustrating the distribution of the Al composition ratio of the gate layer 35. Note that in Figure 7 , the case where the gate layer 35 has a first portion 56, a second portion 57, a third portion 58, and a fourth portion 59, which are different in Al composition ratio, in order from the electron supply layer 31 is shown. That is, in the gate layer 35, as portions different in Al composition ratio, not limited to two portions, as shown in Figure 6 , three portions, four portions, or more can be provided.

[0090] In Figure 6 and Figure 7 , the distribution of the Al composition ratio of the gate layer 35 increases in steps from the electron supply layer 31 toward the gate electrode 3. By steps, it is meant, for example, that when the composition in the thickness direction of the gate layer 35 is analyzed, a plurality of portions having a certain range of Al composition ratio are formed. For example, in Figure 6 , a first portion 53 having an Al composition ratio of 0% to 3% and a second portion 54 having an Al composition ratio of 5% to 15% can be formed, and when these Al composition ratios are charted, a step difference of a certain width is provided.

[0091] On the other hand, in Figure 8 , as shown by the distribution curve 60, the distribution of the Al composition ratio of the gate layer 35 increases linearly from the electron supply layer 31 toward the gate electrode 3. By linearly, it is meant, for example, that when the composition in the thickness direction of the gate layer 35 is analyzed, the Al composition ratio increases continuously from the electron supply layer 31 toward the gate electrode 3. Note that in Figure 8 , for comparison, the distribution of the Al composition ratio that changes in steps in Figure 7 is shown by a dotted line.

[0092] Effects of the Nitride Semiconductor Device 1

[0093] Next, the effects of the nitride semiconductor device 1 according to the present embodiment will be described.

[0094] According to the nitride semiconductor device 1 described above, the gate layer 35 is composed of an Al 1- x Ga x N (0 < X < 1) material, and thus the gate withstand voltage can be improved. Further, since the gate electrode 3 is in Schottky junction with the gate layer 35, the gate leakage current can also be reduced. As a result, a nitride semiconductor device 1 with high reliability can be provided.

[0095] Regarding the improvement of the gate withstand voltage by the AlGaN gate layer 35, in Figure 9 and Figure 10 are shown. Figure 9 is a graph showing the relationship between the gate voltage and the insulation breakdown time (tBD) of Sample 1 and Sample 2. Figure 10 is a graph showing the relationship between the electric field intensity and the insulation breakdown time (tBD) of Sample 1 and Sample 2.

[0096] More specifically, a TDDB (Time Dependent Dielectric Breakdown) test was performed on the HEMT having the AlGaN (Mg-doped) and GaN (Mg-doped) gate layers 35, respectively, and it was compared which of the AlGaN gate layer 35 (Sample 1) and the GaN gate layer 35 (Sample 2) broke down in a short time. In addition, the thickness of the gate layer 35 was set to 80 nm, the Al composition ratio was set to 8%, and the concentration of Mg was set to 5 x 1019cm-2. 19 -3

[0097] As shown in Figure 9 , in Sample 2, as the gate voltage Vg was set to be higher at 7.5 V, 8.5 V, and 9.5 V, the time tBD until the breakdown of the gate layer 35 was shorter. In contrast, it was found that in Sample 1, as in Sample 2, the time tBD became shorter as the gate voltage Vg increased, but the time tBD until the breakdown was longer than that of Sample 2 at any gate voltage Vg.

[0098] In addition, Figure 10 is a graph of the X axis (horizontal axis) of the graph showing Figure 9 the electric field intensity of the gate layer 35. According to Figure 10 , it was found that the electric field intensity of the gate layer 35 of Sample 1 shifted to the high electric field intensity side compared to the electric field intensity of the gate layer 35 of Sample 2, and the gate layer 35 of Sample 1 was superior in terms of the withstand voltage. For example, when the gate voltage Vg = 7.5 V was applied, the electric field intensity of Sample 2 was about 7.2 x 1010V / cm, in contrast, the electric field intensity of Sample 1 was about 7.8 x 1010V / cm. 5 5

[0099] The above describes an embodiment of the present disclosure, but the present disclosure can be implemented in other ways and various design changes can be implemented within the scope of the matters described in the claims.

[0100] This application corresponds to Japanese Patent Application No. 2020-076664 filed with the Japan Patent Office on April 23, 2020, the entire disclosure of which is incorporated herein by reference. ​​​​

[0101] Symbol explanation

[0102] 1: nitride semiconductor device,

[0103] 3: gate electrode,

[0104] 4: source electrode,

[0105] 5: drain electrode,

[0106] 6: electrode portion,

[0107] 7: base portion,

[0108] 10: source electrode film,

[0109] 15: gate electrode film,

[0110] 16: drain electrode film,

[0111] 28: semiconductor layer stack,

[0112] 30: electron tunneling layer,

[0113] 31: electron supply layer,

[0114] 35: gate layer,

[0115] 36: mesa structure portion,

[0116] 37: (electron supply layer) surface,

[0117] 38: (mesa structure portion) wall surface,

[0118] 39: (gate layer) side surface,

[0119] 40: (gate electrode) side surface,

[0120] 48: mesa structure portion,

[0121] 49: step difference,

[0122] 50: (mesa structure portion) wall surface,

[0123] 51: (gate electrode) flat surface,

[0124] 52: (gate electrode) curved surface,

[0125] 53: (gate layer) first portion,

[0126] 54: (gate layer) second portion,

[0127] 55: boundary portion,

[0128] 56: (gate layer) first portion,

[0129] 57: (gate layer) second portion,

[0130] 58: (gate layer) third portion,

[0131] 59: (gate layer) fourth portion,

[0132] T1: thickness,

[0133] T2: thickness,

[0134] X1: Al composition ratio,

[0135] X2: Al composition ratio,

[0136] X3: Al composition ratio,

[0137] X4: average Al composition ratio.

Claims

1. A nitride semiconductor device comprising: an electron tunneling layer, an electron supply layer formed on the electron tunneling layer, a gate electrode formed on the gate layer and in Schottky junction with the gate layer, and a source electrode and a drain electrode electrically connected to the electron supply layer; the electron tunneling layer contains a GaN-based material, the gate layer has an Al composition ratio smaller than that of the electron supply layer.

2. A nitride semiconductor device comprising: an electron tunneling layer, an electron supply layer formed on the electron tunneling layer, a gate electrode formed on the gate layer and in Schottky junction with the gate layer, and a source electrode and a drain electrode electrically connected to the electron supply layer; an Al composition ratio of the gate layer increases linearly or stepwise from the electron supply layer toward the gate electrode.

3. A nitride semiconductor device comprising: an electron tunneling layer, an electron supply layer formed on the electron tunneling layer, a gate electrode formed on the gate layer and in Schottky junction with the gate layer, a source electrode and a drain electrode electrically connected to the electron supply layer, and a mesa structure portion having a wall surface that continuously spans the gate layer and the gate electrode and is inclined with respect to a surface of the electron supply layer. a gate layer formed on the electron supply layer and containing Al containing a first impurity 1-x Ga x N-based material, and 0 < X < 1, 4. A nitride semiconductor device comprising: an electron tunneling layer, an electron supply layer formed on the electron tunneling layer, a gate electrode formed on the gate layer and in Schottky junction with the gate layer, and a source electrode and a drain electrode electrically connected to the electron supply layer.

5. The nitride semiconductor device according to any one of claims 1 to 4, wherein the gate electrode contains at least one of TiN, Ti, Al, W, Mo, and TaN.

6. The nitride semiconductor device according to any one of claims 1 to 4, wherein the first impurity contains at least one of Mg and Zn. The electron supply layer contains Al 1-x Ga x N-based material and 0 < X < 1, 7. The nitride semiconductor device according to any one of claims 1 to 4, wherein 8. The nitride semiconductor device according to claim 7, wherein the gate layer has a thickness of 100 nm or more.

9. The nitride semiconductor device according to any one of claims 2 to 4, wherein the electron tunneling layer contains a GaN-based material, the gate layer has an Al composition ratio smaller than that of the electron supply layer.

10. The nitride semiconductor device according to claim 1, wherein the gate layer includes a first portion having a relatively small Al composition ratio, and a second portion formed on an opposite side of the electron supply layer from the first portion and having a relatively large Al composition ratio than the first portion, an average Al composition ratio of the first portion and the second portion is smaller than an Al composition ratio of the electron supply layer. a gate layer formed on the electron supply layer and containing Al containing a first impurity 1-x Ga x N-based material, and 0 < X < 1, 11. The nitride semiconductor device according to claim 9, wherein ​ ​ ​ ​ ​ a gate layer formed on the electron supply layer and containing Al containing a first impurity 1-x Ga x N-based material, and 0 < X < 1, ​ ​ ​ ​ ​ ​ a gate layer formed on the electron supply layer and containing Al containing a first impurity 1-x Ga x a semi-insulating material of the GaN system, and 0 < X < 1, ​ ​ ​ ​ ​ ​ ​ The gate layer has a thickness of 60 nm or more and a concentration of 3 x 10 18 cm -3 or more of the first impurity. ​ ​ ​ ​ The electron supply layer contains Al 1-x Ga x N-based material and 0 < X < 1, ​ ​ ​ ​ ​ The gate layer includes a first portion having a relatively small Al composition ratio, and a second portion having a relatively large Al composition ratio than the first portion, formed on the opposite side of the electron supply layer from the first portion, An average Al composition ratio of the first portion and the second portion is smaller than an Al composition ratio of the electron supply layer.

12. The nitride semiconductor device according to any one of claims 1, 3 or 4, wherein The Al composition ratio of the gate layer increases linearly or stepwise from the electron supply layer toward the gate electrode.

13. The nitride semiconductor device according to any one of claims 1, 2 or 4, wherein The nitride semiconductor device includes a mesa structure portion having a wall surface that continuously spans the gate layer and the gate electrode and is inclined with respect to a surface of the electron supply layer.

14. The nitride semiconductor device according to claim 3, wherein The gate electrode has a smaller thickness than the gate layer.

15. The nitride semiconductor device according to claim 13, wherein The gate electrode has a smaller thickness than the gate layer.

16. The nitride semiconductor device according to any one of claims 1 to 4, wherein The gate electrode is formed in an inner side region of the gate layer in a manner that a step difference is formed between a side surface of the gate layer and a side surface of the gate electrode.

17. The nitride semiconductor device according to claim 16, wherein The gate electrode has a larger thickness than the gate layer.

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