Integrated circuit testing device

Abstract

The present invention discloses a test device for an integrated circuit, comprising five parts: a driving motherboard, a main control board, a digital core board, an analog signal board, and a driving module. The driving motherboard comprises various interfaces, a secondary power generation module, a detection module, and a CPLD logic bonding module. The digital core board is used for online configuration of test codes. The analog signal board is used for providing analog signals required by the device. The driving module is used for driving and amplifying the output signals of the digital core board. The present invention can generate test vectors with a maximum frequency of 20 MHz, a minimum programming step length of 25 ns, a programming resolution of 25 ns, and a signal high-level voltage of up to 6 V, meeting the testing requirements of more devices and more functions. The present invention can generate analog signals with a maximum frequency of 1 MHz and a peak value of up to 20 V, meeting the testing requirements of more devices and more functions. The present invention can generate 256 test signals, meeting the testing requirements of ultra-large-scale integrated circuits. Utilizing a modular design, each functional module can be disassembled and replaced, facilitating maintenance and replacement.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a testing device for an integrated circuit. Background Art

[0002] When testing integrated circuits, specific test vectors must be applied to the device under test. By comparing the device's response with the theoretical value, the device's functionality or quality can be determined. The maximum test vector frequency that the integrated circuit test equipment can provide determines the type of device testing capabilities. Lower test vector signal frequencies result in larger programming steps and resolutions, making some high-speed devices impractical to test or incomplete in test functionality. The number of signal paths the device can provide determines the number of device pins it can test, and thus the scale of devices that can be tested.

[0003] A search revealed an integrated circuit test device with the publication number CN 109725245 A. One embodiment of the device includes a chip clock controller, a pulse debugging circuit, and a temporary storage circuit. The chip clock controller generates an output clock based on an input clock, wherein the output clock is used to test a circuit under test, and the circuit under test is included in the integrated circuit test device. The pulse debugging circuit generates a pulse record based on a pulse count of the output clock, indicating whether a test state associated with the output clock is normal. The temporary storage circuit stores and outputs the pulse record based on a stable clock.

[0004] However, the test device of the above invention can test a relatively small number of paths and cannot meet the requirements of large-scale integrated circuit testing.

[0005] In order to enable domestic testing equipment to test more devices and meet more testing function requirements, the present invention proposes an integrated circuit testing device that can be used to implement ultra-large-scale integrated circuit testing.

[0006] Currently, no effective solutions have been proposed for the problems in related technologies. Summary of the Invention

[0007] In response to the problems in the related art, the present invention proposes a testing device for integrated circuits, which includes five parts: a driving motherboard, a main control board, a digital core board, an analog signal board and a driving module;

[0008] The main control board is connected to a driving motherboard, a digital core board, and a driving module respectively;

[0009] The digital core board is also connected to a drive module;

[0010] Moreover, the driving motherboard, the driving module, and the analog signal board are respectively connected to the device to be detected, the driving module is connected with a digital core board, the digital core board is connected with a main control board, and the main control board is respectively connected to the driving motherboard and the analog signal board;

[0011] The driving motherboard includes a power interface, a control signal interface, a secondary power generation module, a detection module and a CPLD logic gluing module, the power interface and the control signal interface are respectively connected with a secondary power generation module, a detection module, and a CPLD logic gluing module, the main control board is used for process control of the whole system, the digital core board is used for online configuration test code, the analog signal board is used to provide the analog signal required for the device, and the driving module is used to drive the output signal of the digital core board to amplify;

[0012] Among them, the bus is connected through the interface of the main control board, the 10M network port of the main control board is connected to the 10M / 100M hub, and the bus is respectively connected with an analog signal board, a digital core board, and a driver motherboard. The analog signal board is connected to the docking seat through two definable analog connections, the digital core board is connected to the drive module, and the drive module is connected to the docking seat through 256 definable digital and five controllable DC signals. The drive motherboard is respectively connected to the drive module and the docking seat through five controllable DC signals, and the docking seat is respectively connected to the device under test N1 and the device under test N2 through 128 independently defined signals, and the device under test N1 and the device under test N2 are interconnected.

[0013] Furthermore, the secondary power generation module includes an amplifier U101, an amplifying resistor R106, an amplifying resistor R107, an amplifying resistor R108, a feedback resistor R109, a feedback resistor R110, a power tube V100, and an external primary power supply PS1_2. It also has a secondary power generation module, a detection module, and a CPLD logic bonding module. The driving motherboard is used to provide a power interface and a signal interface to the system and other functional modules.

[0014] Furthermore, the signal input to the secondary power generation module is V1_ctrl2, V1_ctrl2 is the control signal generated by the main control board through the DAC, V1_SMP is the secondary power sampling signal, V1_1 and V1 are the voltages across the sampling resistor, and VCC1 is the secondary power signal to be generated, wherein V1_SMP, V1_1 and V1 are used for the detection module. The circuit amplification formula is as follows:

[0015] (R106+R107+R108) / R106, that is, VCC1=(R106+R107+R108)*V1_ctrl2 / R106;

[0016] V1_SMP is taken as the secondary power supply sampling value. The secondary power supply generating module is used to provide a DC signal to the device under test, and the detection module is used to detect the voltage value and current value of the secondary power supply.

[0017] Among them, after the V1_ctrl2 signal is input, it passes through R105, R105 is connected in parallel with C103 and amplifier pin 3, C103 is connected to the analog ground AGND, amplifier pin 2 is connected to R106, one end of R106 is connected to the analog ground AGND, the output end of the amplifier is connected in parallel with R109 and R110, the amplifier output end is connected in parallel with the amplifier pin 2 with C105, one end of R110 is connected to the analog ground AGND, one end of R109 is connected to the V100 power tube, the V100 power tube is respectively connected with R100 and PS1_2, one end of R106 is connected to the amplifier pin 2 and R107 in parallel and one end of C104 in parallel, the other end of C104 is connected in parallel with the other end of R107, the other end of C104 and one end of R107 are connected in parallel with R108, the other end of R108 is connected in parallel with the other end of R100, the positive end of C106 is connected in parallel with one end of C107, C108, C109, and C110 respectively, the negative end of C106 is connected to the other ends of C108 and C109 and to the PGND power ground, the other end of C109 is connected to the other end of C110 and to the PGND power ground, and the parallel point circuit of R100 and R108 is connected in parallel with the positive end of C106.

[0018] Further, the main control board includes STM32 series chips, crystal oscillator, EEPROM, SRAM and network communication module, and the STM32 series chips are respectively connected with crystal oscillator, EEPROM, SRAM, network communication module, and the STM32 series chips are connected with the digital core board by address bus and data bus, forming micro control system, responsible for the process operation of whole system and parameter sending and receiving etc.

[0019] Furthermore, the digital core board includes an FPGA chip, a DDR3 chip and a power supply system. The FPGA chip is connected to an ADC, the ADC is connected to an offset circuit, and the offset circuit is connected to a drive circuit for realizing functions such as data input / output control and timing processing.

[0020] Furthermore, the analog signal board includes an FPGA chip, an ADC, an offset circuit, a driving circuit and a power supply system. The FPGA chip is connected to the ADC, the ADC is connected to the offset circuit, and the offset circuit is connected to the driving circuit for generating the analog signal required by the device under test.

[0021] Furthermore, the driving module includes a driving chip, a CPLD logic bonding module and a power supply system. The driving chip is connected to the CPLD logic bonding module. The FPGA chip of the digital core board and the driving chip are communicated with each other through digital signals. The driving chip is used to amplify the input digital signal.

[0022] According to another aspect of the present invention, a calculation method for detecting voltage of a detection module is provided, and the calculation process is as follows:

[0023] S101: V1_SMP is the sampling signal in the secondary power generation module, which is divided by resistors to generate a voltage signal VS1, where VS1 = V1_SMP * resistor R702 / (resistor R701 + resistor R702);

[0024] S201: VS1 passes through the follower circuit to generate VS_1. The obtained VS_1 has the same voltage value as VS1, that is, VS_1=VS1.

[0025] S301: U702 is a gate chip, which is controlled by the program to gate the voltage signals VS_1-VS_5 to be sampled to the output terminal 3;

[0026] S401: Assuming that the signal at pin 13, VS_1, is selected, the sampling signal VS_1 will be selected to pin 3. The output signal at pin 3 will be output to the right end of R719, DATA, after passing through the follower circuit composed of U704.

[0027] S501: The DATA data signal value is the sampling value, which is VS_1 in this assumption, that is, the DATA data signal = VS_1. Finally, the DATA data signal value will enter the main control board, enter the sampling program after ADC conversion, and obtain the sampling value through calculation.

[0028] Among them, V1_SMP input passes through resistor R701, which is connected in series with a voltage divider circuit. The voltage divider circuit includes a capacitor C701 and a resistor R702. The capacitor C701 and the resistor R702 are connected in parallel. One end of the voltage divider circuit is connected to the analog ground AGND;

[0029] Among them, the generated VS1 is connected through the amplifier pin 3, the output end of the amplifier is connected in parallel with the amplifier pin 2, the parallel circuit of the output end of the amplifier and the amplifier pin 2 is connected in series with the resistor R709, one end of the resistor R709 outputs VS_1, the pin 4 of the amplifier is connected to the capacitor C706, one end of the capacitor C706 is connected to the analog ground AGND, the pin 13 of the amplifier is connected to the capacitor C705, and one end of the capacitor C705 is connected to the analog ground AGND;

[0030] Among them, the A / B / C pins of the U702 / U703 selection chip are switched for switch selection. The A / B / C pins are connected to the 4051 chip and controlled by the 4051 chip. The VS1-VS5 of the relative position device in U702 are respectively connected to the analog switches X0-X4, and the analog switches X5-X7 are respectively connected to the 5, 2, and 4 pins of R716. The IS1-IS5 of the relative position device in U703 are respectively connected to the analog switches X0-X4, and the analog switches X5-X7 are respectively connected to the 5, 2, and 4 pins of R716. They are respectively connected to pins 5, 2, and 4 of R717, one end of R717 and R716 is connected to the analog ground AGND, the common end X of U702 and U703 is connected to R718, one end of R718 is connected to pin 3 of the amplifier, pin 6 of the amplifier is connected to R719 and pin 2 of the amplifier, C713 and V702 are connected in parallel to form a loop, one end of the loop is connected to the analog ground AGND, and the other end is connected in parallel with R719, the DATA data signal, and V701.

[0031] According to another aspect of the present invention, a calculation method for current detection of a detection module is provided, and the calculation process is as follows:

[0032] S102: After the current passes through the sampling resistor R100 in the secondary power generation module, a voltage difference is generated across the resistor. Here, assuming the current is I1, the voltage difference across R100 is V1_1-V1=I1*R100;

[0033] S202: The voltage difference (V1_1-V1) passes through the differential amplifier circuit formed by U102 to obtain IS1. Assuming the amplification factor is N, then IS1=N*(V1_1-V1);

[0034] S302: Using the strobe (U703) and follower circuit (U704) similar to the voltage sampling principle, the sampled IS1 is transferred to the DATA data signal, that is, DATA data signal = IS1 = N*(V1_1-V1);

[0035] S402: Finally, the DATA data signal value will enter the main control board, enter the sampling program after ADC conversion, and obtain the sampling value through calculation.

[0036] Among them, pin 2 of U102 is connected to V1_1, pin 2 is connected to V1, pin 8 is connected in series with R111, one end of the R111 is connected to C114, one end of the C114 is connected to the analog ground AGND, and then IS1 is output through the R111 and C114, pins 4, 6, and 7 are connected to the analog ground AGND, pin 5 is connected to C113 and R112, one end of the R112 is connected to the +5V voltage, and one end of the C113 is connected to the analog ground AGND.

[0037] According to another aspect of the present invention, a method for calculating the offset circuit of an analog signal board is provided, and the calculation process is as follows:

[0038] S103: OUT1 and OUT2 are analog differential signals. After passing through the amplifier circuit composed of U102A, a signal Vin2 is generated. The amplification factor is R108 / R109, that is, Vin2 = (R108 / R109) * (OUT1-OUT2);

[0039] S203: Similarly, U101A is also an amplifier circuit, which amplifies the input signal (2.048V-Vbias_1) by (R105 / R103) times, that is, Vin1=(R105 / R103)*(2.048V-Vbias_1);

[0040] S303: Finally, after passing through the adding circuit formed by U102B, SA=-(Vin1+Vin2) is obtained;

[0041] Among them, SA input circuit, C104 and R115 are connected in parallel, one end of R115 is connected to pin 7 of U102B amplifier, and pin 7 is connected in parallel with R114 and C103. The other end of R114 and C103 is connected to pin 6 of U102B amplifier, and is connected to one end of R106 and R107 through pin 6. The other end of R106 is connected to U101A 1 and 2 of U101A, R105 is connected in parallel to pin 1 and pin 2 of U101A, pin 2 is connected to R103 at the same time, pin 3 is connected to R101 and R102, the other end of R101 and pin 5 of U102B are connected to the analog ground AGND, the other end of R107 is connected to pin 1 of U102A, R108 is connected in parallel to pin 1 and pin 2 of U102A, pin 2 of U102A is connected to R109, the other end of R109 is connected to R111 and OUT2, pin 3 of U102A is connected to R110 and R113, the other end of R110 is connected to R112 and OUT1, and the other ends of R112 and R113 are connected to the analog ground AGND.

[0042] For the same analog signal, Vbias_1 is the offset variable, and the other values ​​are fixed values. Therefore, the offset of the analog signal can be adjusted by adjusting the value of Vbias_1.

[0043] The beneficial effects of the present invention are:

[0044] 1) The present invention can generate test vectors with a maximum frequency of 20 MHz, a minimum programming step of 25 ns, a programming resolution of 25 ns, and a signal high-level voltage of up to 6 V, meeting the testing requirements of more devices and more functions.

[0045] 2) The present invention can generate analog signals with a maximum frequency of 1 MHz and a peak value of up to 20 V, meeting the testing needs of more devices and more functions.

[0046] 3) The present invention can generate 256 test signals to meet the testing requirements of ultra-large-scale integrated circuits.

[0047] 4) The present invention utilizes modular design, and each functional module can be disassembled and replaced, making maintenance and replacement convenient. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0049] Figure 1 is a system flow chart of an integrated circuit testing device according to an embodiment of the present invention;

[0050] Figure 2 is a detection flow chart of an integrated circuit testing device according to an embodiment of the present invention;

[0051] Figure 3 This is a principle block diagram of a driving motherboard in a testing device for an integrated circuit according to an embodiment of the present invention;

[0052] Figure 4 This is a principle block diagram of a main control board in a test device for an integrated circuit according to an embodiment of the present invention;

[0053] Figure 5 This is a principle block diagram of a digital core board in a test device for an integrated circuit according to an embodiment of the present invention;

[0054] Figure 6 This is a principle block diagram of an analog signal board in a test device for an integrated circuit according to an embodiment of the present invention;

[0055] Figure 7 This is a principle block diagram of a driving module in a testing device for an integrated circuit according to an embodiment of the present invention;

[0056] Figure 8 This is a schematic diagram of a secondary power generation module in an integrated circuit testing device according to an embodiment of the present invention;

[0057] Figure 9 1 is a circuit diagram for generating a voltage signal VS1 in a test device for an integrated circuit according to an embodiment of the present invention;

[0058] Figure 10 is a follower circuit diagram in a test device for an integrated circuit according to an embodiment of the present invention;

[0059] Figure 11 is a circuit diagram of a current detection module in a test device for an integrated circuit according to an embodiment of the present invention;

[0060] Figure 12 is a circuit diagram of a current detection module in a test device for an integrated circuit according to an embodiment of the present invention;

[0061] Figure 13 is a circuit diagram of an analog signal board offset in a test device for an integrated circuit according to an embodiment of the present invention;

[0062] Figure 14 is a diagram of an analog signal board driving circuit in a test device for an integrated circuit according to an embodiment of the present invention;

[0063] Figure 15 This is a circuit diagram of a driving module in a testing device for an integrated circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0064] To further illustrate each embodiment, the present invention provides drawings, which are part of the disclosure of the present invention. They are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. By referring to these contents, ordinary technicians in this field should be able to understand other possible implementation methods and advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are generally used to represent similar components.

[0065] According to an embodiment of the present invention, a testing device for an integrated circuit is provided.

[0066] The present invention will now be further described with reference to the accompanying drawings and specific embodiments. Figure 2-8 As shown, the integrated circuit test device according to an embodiment of the present invention includes five parts: a driving motherboard, a main control board, a digital core board, an analog signal board and a driving module;

[0067] The main control board is connected to a driving motherboard, a digital core board, and a driving module respectively;

[0068] The digital core board is also connected to a drive module;

[0069] The driving motherboard, the driving module, and the analog signal board are respectively connected to the device to be detected, the driving module is connected with a digital core board, the digital core board is connected with a main control board, and the main control board is respectively connected to the driving motherboard and the analog signal board;

[0070] The driving motherboard includes various interfaces, a secondary power generation module, a detection module and a CPLD logic glue module. The power interface and the control signal interface are respectively connected to the secondary power generation module, the detection module and the CPLD logic glue module. The main control board is used for process control of the entire system, the digital core board is used for online configuration test code, the analog signal board is used to provide the analog signal required by the device, and the driving module is used to drive and amplify the output signal of the digital core board. After driving, the maximum voltage of the high level of the signal is +6V.

[0071] Among them, the bus is connected through the interface of the main control board, the 10M network port of the main control board is connected to the 10M / 100M hub, and the bus is respectively connected with an analog signal board, a digital core board, and a driver motherboard. The analog signal board is connected to the docking seat through two definable analog connections, the digital core board is connected to the drive module, and the drive module is connected to the docking seat through 256 definable digital and five controllable DC signals. The drive motherboard is respectively connected to the drive module and the docking seat through five controllable DC signals, and the docking seat is respectively connected to the device under test N1 and the device under test N2 through 128 independently defined signals, and the device under test N1 and the device under test N2 are interconnected.

[0072] Specifically, the secondary power generation module includes an amplifier U101, an amplifying resistor R106, an amplifying resistor R107, an amplifying resistor R108, a feedback resistor R109, a feedback resistor R110, a power tube V100, and an external primary power supply PS1_2. The driver motherboard is used to provide a power interface and a signal interface for the system and other functional modules, and also has a secondary power generation module, a detection module, and a CPLD logic bonding module.

[0073] Among them, V1_ctrl2 is the control signal generated by the main control board through the DAC, V1_SMP is the secondary power sampling signal, V1_1 and V1 are the voltages across the sampling resistor, and VCC1 is the secondary power signal that needs to be generated. Among them, V1_SMP, V1_1 and V1 are used to detect the module. The circuit amplification formula is as follows:

[0074] (R106+R107+R108) / R106, that is, VCC1=(R106+R107+R108)*V1_ctrl2 / R106;

[0075] In the circuit, the resistance of R108 is much smaller than that of R106 and R107, and the voltage values ​​of VCC1 and V1_SMP are close, so V1_SMP is taken as the secondary power supply sampling value;

[0076] Among them, after the V1_ctrl2 signal is input, it passes through R105, R105 is connected in parallel with C103 and amplifier pin 3, C103 is connected to the analog ground AGND, amplifier pin 2 is connected to R106, one end of R106 is connected to the analog ground AGND, the output end of the amplifier is connected in parallel with R109 and R110, the amplifier output end is connected in parallel with the amplifier pin 2 with C105, one end of R110 is connected to the analog ground AGND, one end of R109 is connected to the V100 power tube, the V100 power tube is respectively connected with R100 and PS1_2, one end of R106 is connected to the amplifier pin 2 and R107 in parallel and one end of C104 in parallel, the other end of C104 is connected in parallel with the other end of R107, the other end of C104 and one end of R107 are connected in parallel with R108, the other end of R108 is connected in parallel with the other end of R100, the positive end of C106 is connected in parallel with one end of C107, C108, C109, and C110 respectively, the negative end of C106 is connected to the other ends of C108 and C109 and to the PGND power ground, the other end of C109 is connected to the other end of C110 and to the PGND power ground, and the parallel point circuit of R100 and R108 is connected in parallel with the positive end of C106.

[0077] The secondary power generation module is used to provide a DC signal to the device under test, the detection module is used to detect the voltage and current values ​​of the secondary power supply, and the CPLD logic glue module is used for data buffering and AC between the main control board and the digital core board.

[0078] like Figure 9 、 Figure 10 、 Figure 12 As shown, the calculation process of the voltage detection of the detection module is as follows:

[0079] S101: V1_SMP is the sampling signal in the secondary power generation module, which is divided by resistors to generate a voltage signal VS1, where VS1 = V1_SMP * resistor R702 / (resistor R701 + resistor R702);

[0080] S201: VS1 passes through the follower circuit to generate VS_1. The obtained VS_1 has the same voltage value as VS1, that is, VS_1=VS1.

[0081] S301: If Figure 12 In the circuit, U702 is a gate chip, which controls the voltage signals VS_1-VS_5 to be sampled and gates them to the output terminal 3 through program control.

[0082] S401: Assuming that the signal at pin 13, VS_1, is selected, the sampling signal VS_1 will be selected to pin 3. The output signal at pin 3 will be output to the right end of R719 after passing through the follower circuit composed of U704, i.e., the DATA signal (please refer to Figure 12 and step S402);

[0083] S501: The DATA data signal value is the sampling value, which is VS_1 in this assumption, that is, DATA data signal = VS_1. Finally, the DATA data signal value enters the main control board, is converted by the ADC, and then enters the sampling program, and the sampling value is obtained through calculation.

[0084] Among them, V1_SMP input passes through resistor R701, which is connected in series with a voltage divider circuit. The voltage divider circuit includes a capacitor C701 and a resistor R702. The capacitor C701 and the resistor R702 are connected in parallel. One end of the voltage divider circuit is connected to the analog ground AGND;

[0085] Among them, the generated VS1 is connected through the amplifier pin 3, the output end of the amplifier is connected in parallel with the amplifier pin 2, the parallel circuit of the output end of the amplifier and the amplifier pin 2 is connected in series with the resistor R709, one end of the resistor R709 outputs VS_1, the pin 4 of the amplifier is connected to the capacitor C706, one end of the capacitor C706 is connected to the analog ground AGND, the pin 13 of the amplifier is connected to the capacitor C705, and one end of the capacitor C705 is connected to the analog ground AGND;

[0086] Among them, the A / B / C pins of the U702 / U703 selection chip are switched for switch selection. The A / B / C pins are connected to the 4051 chip and controlled by the 4051 chip. The VS1-VS5 of the relative position device in U702 are respectively connected to the analog switches X0-X4, and the analog switches X5-X7 are respectively connected to the 5, 2, and 4 pins of R716. The IS1-IS5 of the relative position device in U703 are respectively connected to the analog switches X0-X4, and the analog switches X5-X7 are respectively connected to the 5, 2, and 4 pins of R716. They are respectively connected to pins 5, 2, and 4 of R717, one end of R717 and R716 is connected to the analog ground AGND, the common end X of U702 and U703 is connected to R718, one end of R718 is connected to pin 3 of the amplifier, pin 6 of the amplifier is connected to R719 and pin 2 of the amplifier, C713 and V702 are connected in parallel to form a loop, one end of the loop is connected to the analog ground AGND, and the other end is connected in parallel with R719, the DATA data signal, and V701.

[0087] like Figure 11-12 As shown, the calculation process of the current detection of the detection module is as follows:

[0088] S102: After the current passes through the sampling resistor R100 in the secondary power generation module, a voltage difference is generated across the resistor. Here, assuming the current is I1, the voltage difference across R100 is V1_1-V1=I1*R100;

[0089] S202: The voltage difference (V1_1-V1) passes through the differential amplifier circuit formed by U102 to obtain IS1. Assuming the amplification factor is N, then IS1=N*(V1_1-V1);

[0090] S302: If Figure 12 , using the strobe (U703) and follower circuit (U704) similar to the voltage sampling principle, the sampled IS1 is transferred to the DATA data signal, that is, DATA data signal = IS1 = N*(V1_1-V1);

[0091] S402: Finally, the DATA data signal value will enter the main control board, enter the sampling program after ADC conversion, and obtain the sampling value through calculation.

[0092] Among them, pin 2 of U102 is connected to V1_1, pin 2 is connected to V1, pin 8 is connected in series with R111, one end of the R111 is connected to C114, one end of the C114 is connected to the analog ground AGND, and then IS1 is output through the R111 and C114, pins 4, 6, and 7 are connected to the analog ground AGND, pin 5 is connected to C113 and R112, one end of the R112 is connected to the +5V voltage, and one end of the C113 is connected to the analog ground AGND.

[0093] The main control board includes STM32 series chips, crystal oscillator, EEPROM, SRAM and network communication module, the STM32 series chips are respectively connected with crystal oscillator, EEPROM, SRAM, network communication module, the STM32 series chips are connected with the digital core board by address bus and data bus, form a micro control system, responsible for the process operation and parameter sending and receiving of the whole system, etc., communicate with other functional modules by address bus and data bus.

[0094] The digital core board includes an FPGA chip, a DDR3 chip and a power supply system. The DDR3 chips are DDR3_1 and DDR3_2 respectively. The FPGA chip is connected to the STM32 series chip through an address bus and a data bus. The FPGA chip is connected to DDR3_1 and DDR3_2 respectively (DDR3_1 and DDR3_2 are both DDR3 memory chips, _1 and _2 are used to distinguish which one is which. The two chips have the same functions. Using two DDR3 chips only has a larger storage capacity). The FPGA chip uses the ARTIX7 series chip of XILINX company to realize functions such as data input / output control and timing processing. The DDR3 chip is used for data storage. The output of the digital core board is a digital signal.

[0095] The analog signal board includes an FPGA chip, an ADC, an offset circuit, a drive circuit and a power supply system. The FPGA chip is connected to the ADC, the ADC is connected to the offset circuit, and the offset circuit is connected to the drive circuit to generate the analog signal required by the device under test.

[0096] like Figure 13 As shown, the calculation process of the offset circuit of the analog signal board is as follows:

[0097] S103: OUT1 and OUT2 are analog differential signals. After passing through the amplifier circuit composed of U102A, a signal Vin2 is generated. The amplification factor is R108 / R109, that is, Vin2 = (R108 / R109) * (OUT1-OUT2);

[0098] S203: Similarly, U101A is also an amplifier circuit, which amplifies the input signal (2.048V-Vbias_1) by (R105 / R103) times, that is, Vin1=(R105 / R103)*(2.048V-Vbias_1);

[0099] S303: Finally, after passing through the adding circuit formed by U102B, SA=-(Vin1+Vin2) is obtained;

[0100] Among them, for the same analog signal, Vbias_1 is the offset variable, and the other values ​​are fixed values. Therefore, the offset of the analog signal can be adjusted by adjusting the value of Vbias_1;

[0101] Among them, SA input circuit, C104 and R115 are connected in parallel, one end of R115 is connected to pin 7 of U102B amplifier, and pin 7 is connected in parallel with R114 and C103. The other end of R114 and C103 is connected to pin 6 of U102B amplifier, and is connected to one end of R106 and R107 through pin 6. The other end of R106 is connected to U101A 1 and 2 of U101A, R105 is connected in parallel to pin 1 and pin 2 of U101A, pin 2 is connected to R103 at the same time, pin 3 is connected to R101 and R102, the other end of R101 and pin 5 of U102B are connected to the analog ground AGND, the other end of R107 is connected to pin 1 of U102A, R108 is connected in parallel to pin 1 and pin 2 of U102A, pin 2 of U102A is connected to R109, the other end of R109 is connected to R111 and OUT2, pin 3 of U102A is connected to R110 and R113, the other end of R110 is connected to R112 and OUT1, and the other ends of R112 and R113 are connected to the analog ground AGND.

[0102] like Figure 14 As shown, the calculation process of the driving circuit of the analog signal board is as follows:

[0103] S104: The main body is the driving circuit composed of D200, where SA is the analog signal input;

[0104] S204: After the driver chip D200 drives the analog signal AS1;

[0105] S304: AS1 passes through fuse F1 and obtains output signal AS1_1;

[0106] S404: In addition, the circuit can also block the output of the SA signal through the CLOSE1 signal;

[0107] Among them, the AS1_1 input circuit passes through F1, one end of the F1 is connected to R809 and D200 pin 7 and C807, the other end of the C807 is connected to D200 pin 5, pins 4 and 6 of the D200 are connected to 18V voltage, pin 3 of the D200 is connected to the CLOSE1 signal, pin 2 of the D200 is connected to SA, the other end of R809 is connected to R12, pin 1 of the D200 is connected to the other end of R12, the other end of R12 is connected to R807, and the other end of the R807 is connected to the analog ground AGND.

[0108] The driving module is composed of 256 small driving modules, each of which drives and amplifies the digital signal through a driving chip. The driving module includes a driving chip, a CPLD logic glue module and a power supply system. The driving chip is connected with a CPLD logic glue module. The FPGA chip of the digital core board is connected to the driving chip through digital signals. The driving chip is used to amplify the input digital signal.

[0109] like Figure 15 As shown, the calculation process of the driving module is as follows:

[0110] S105: X101 is the driver chip, IN1 is the input signal, and OUT1 is the output signal;

[0111] S205: IN1 is driven and amplified by the driver chip X101 to obtain the output signal OUT1;

[0112] S305: The circuit can control the input / output conversion through the DIR1 signal;

[0113] S405: When DIR1 is at a low level, IN1 is an output signal and OUT1 is an input signal.

[0114] The detection device provided by the present invention has a 256-channel signal output capability, which can test ultra-large-scale integrated circuit devices. At the same time, it can generate test vectors with a maximum frequency of 20MHz, a minimum programming step of 25ns, a programming resolution of 25ns, and a signal high-level voltage of up to 6V, which can meet the testing needs of more devices and more functions. In addition, it also has a 2-channel analog signal output capability, and the maximum output signal frequency is 1MHz, which can meet the needs of more test functions.

[0115] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A testing device for an integrated circuit, characterized in that: Including driver motherboard, main control board, digital core board, analog signal board and driver module; The main control board is connected to a driving motherboard, a digital core board, and an analog signal board respectively; The digital core board is also connected to a drive module; Moreover, the driving motherboard, the driving module, and the analog signal board are respectively connected to the device to be detected, the driving module is connected with a digital core board, the digital core board is connected with a main control board, and the main control board is respectively connected to the driving motherboard and the analog signal board; The driving motherboard includes a power supply interface, a control signal interface, a secondary power supply generating module, a detection module and a CPLD logic gluing module. The power supply interface and the control signal interface are respectively connected to the secondary power supply generating module, the detection module and the CPLD logic gluing module. Wherein, the bus is connected through the interface of the main control board, and the bus is respectively connected with an analog signal board, a digital core board, and a drive motherboard, the digital core board is connected to the drive module, the drive motherboard is respectively connected to the drive module and the docking seat, the analog signal board and the drive module are respectively connected to the docking seat, and the docking seat is respectively installed with a device under test N1 and a device under test N2, and the device under test N1 is interconnected with the device under test N2; According to an integrated circuit test device, a calculation method for detecting module voltage is provided, as shown in FIG12 . The calculation process is as follows: S101: V1_SMP is the sampling signal in the secondary power generation module. The sampling signal is divided by resistors to generate a voltage signal VS1. S201: The voltage signal VS1 passes through a follower circuit to generate a voltage signal VS_1. The obtained voltage signal VS_1 has the same voltage value as the voltage signal VS1. S301: The gating chip U702 is controlled by the program to gating the voltage signals VS_1-VS_5 to be sampled to the output terminal 3; S401: Assuming that the signal of pin 13 of U702, namely VS_1, is selected, the sampling signal VS_1 will be selected to pin 3. The output signal of pin 3 will be output to the right end of R719, namely DATA signal, after passing through the follower circuit composed of U704. S501: The DATA data signal value is the sampling value, which is VS_1 in this assumption, that is, the DATA data signal = VS_1. Finally, the DATA data signal value will enter the main control board, enter the sampling program after ADC conversion, and obtain the sampling value through calculation; The sampling signal V1_SMP passes through the resistor R701, which is connected in series with a voltage divider circuit. The voltage divider circuit includes a capacitor C701 and a resistor R702. The capacitor C701 and the resistor R702 are connected in parallel. One end of the voltage divider circuit is connected to the analog ground AGND.

2. The integrated circuit testing device according to claim 1, wherein: The secondary power generation module includes an amplifier U101, an amplifying resistor R106, an amplifying resistor R107, an amplifying resistor R108, a feedback resistor R109, a feedback resistor R110, a power tube V100, and an external primary power supply PS1_2. It also has a secondary power generation module, a detection module, and a CPLD logic bonding module. The signal input to the secondary power generation module is V1_ctrl2, and VCC1 is the secondary power signal to be generated. Among them, after the V1_ctrl2 signal is input, it passes through the amplifying resistor R105, the amplifying resistor R105 is connected in parallel with the capacitor C103 and the amplifier pin 3, the capacitor C103 is connected to the analog ground AGND, the amplifier pin 2 is connected to the amplifying resistor R106, one end of the amplifying resistor R106 is connected to the analog ground AGND, the output end of the amplifier is provided with an amplifying resistor R109 and an amplifying resistor R110 in parallel, the amplifier output end is connected in parallel with the amplifier pin 2 and is provided with a capacitor C105, one end of the amplifying resistor R110 is connected to the analog ground AGND, one end of the amplifying resistor R109 is connected to the power tube V100, the power tube V100 is respectively connected with the amplifying resistor R100 and the primary power input signal PS1_2, one end of the amplifying resistor R106 is connected to the amplifier pin 2 and the amplifying resistor R107 and one end of the capacitor C104 is connected in parallel, the other end of the capacitor C104 is connected in parallel with the other end of the amplifying resistor R107, the other end of the capacitor C104 and one end of the amplifying resistor R107 are connected in parallel with the amplifying resistor R108, the other end of the amplifying resistor R108 is connected in parallel with the other end of the amplifying resistor R100, the positive terminal of the capacitor C106 is respectively connected in parallel with one end of the capacitor C107, the capacitor C108, the capacitor C109, and the capacitor C110, the negative terminal of the capacitor C106 is connected to the other ends of the capacitors C108 and C109 and to the PGND power ground line, the other end of the capacitor C109 is connected to the other end of the capacitor C110 and to the PGND power ground line, and the parallel point circuit of the amplifying resistor R100 and the amplifying resistor R108 is connected in parallel with the positive terminal of the capacitor C106; The circuit amplification formula is as follows: (R106+R107+R108) / R106, that is, VCC1=(R106+R107+R108)*V1_ctrl2 / R106; Take V1_SMP as the secondary power supply sampling value.

3. The integrated circuit testing device according to claim 2, wherein: The main control board includes an STM32 series chip, a crystal oscillator, a memory EEPROM / SRAM and a network communication module. The STM32 series chip is respectively connected with a crystal oscillator, EEPROM, SRAM, a network communication module, and the STM32 series chip is connected to the digital core board through an address bus and a data bus.

4. The integrated circuit testing device according to claim 3, wherein: The digital core board includes an FPGA chip, a DDR3 chip and a power supply system. The DDR3 chip includes DDR3_1 and DDR3_2. The FPGA chip is connected to the STM32 series chip through an address bus and a data bus. The FPGA chip is connected to DDR3_1 and DDR3_2 respectively.

5. The integrated circuit testing device according to claim 4, characterized in that: The analog signal board includes an FPGA chip, an ADC, an offset circuit, a driving circuit and a power supply system. The FPGA chip is connected to the ADC, the ADC is connected to the offset circuit, and the offset circuit is connected to the driving circuit.

6. The integrated circuit testing device according to claim 5, characterized in that: The driving module includes a driving chip, a CPLD logic glue module and a power supply system. The driving chip is connected with the CPLD logic glue module. The FPGA chip of the digital core board and the driving chip are communicated with each other through digital signals.

7. The integrated circuit test device according to claim 6, further comprising a method for calculating current detection of a detection module, wherein the calculation process is as follows: S102: After the current passes through the sampling resistor R100 in the secondary power generation module, a voltage difference is generated across the resistor. Here, assuming the current is I1, the voltage difference across R100 is V1_1-V1=I1*R100; S202: The voltage difference (V1_1-V1) passes through the differential amplifier circuit formed by U102 to obtain IS1. Assuming the amplification factor is N, then IS1=N*(V1_1-V1); S302: As shown in FIG12 , the gate U703 and follower circuit U704, which are similar to the voltage sampling principle, are used to transfer the sampled IS1 to the DATA data signal, i.e., DATA data signal = IS1 = N*(V1_1-V1); S402: Finally, the DATA data signal value will enter the main control board, enter the sampling program after ADC conversion, and obtain the sampling value through calculation.

8. The integrated circuit test device according to claim 7, further comprising a method for calculating the offset circuit of an analog signal board, wherein the calculation process is as follows: S103: OUT1 and OUT2 are analog differential signals. After passing through the amplifier circuit composed of U102A, a signal Vin2 is generated. The amplification factor is R108 / R109, that is, Vin2 = (R108 / R109) * (OUT1-OUT2); S203: Amplify the input signal (2.048V-Vbias_1) by (R105 / R103) times, that is, Vin1=(R105 / R103)*(2.048V-Vbias_1); S303: After passing through the adding circuit formed by U102B, SA=-(Vin1+Vin2) is obtained; in, For the same analog signal, Vbias_1 is the offset variable.

9. The integrated circuit testing device according to claim 8, characterized in that: in, Pin 2 of U102 is connected to V1_1, pin 2 is connected to V1, pin 8 is connected in series with R111, one end of R111 is connected to C114, one end of C114 is connected to analog ground AGND, and then IS1 is output through R111 and C114. Pins 4, 6, and 7 are connected to analog ground AGND, pin 5 is connected to C113 and R112, one end of R112 is connected to +5V voltage, and one end of C113 is connected to analog ground AGND; Among them, SA input circuit, C104 and R115 are connected in parallel, one end of R115 is connected to pin 7 of U102B amplifier, and pin 7 is connected in parallel with R114 and C103. The other end of R114 and C103 is connected to pin 6 of U102B amplifier, and is connected to one end of R106 and R107 through pin 6. The other end of R106 is connected to U101A 1 and 2 of U101A, R105 is connected in parallel to pin 1 and pin 2 of U101A, pin 2 is connected to R103 at the same time, pin 3 is connected to R101 and R102, the other end of R101 and pin 5 of U102B are connected to the analog ground AGND, the other end of R107 is connected to pin 1 of U102A, R108 is connected in parallel to pin 1 and pin 2 of U102A, pin 2 of U102A is connected to R109, the other end of R109 is connected to R111 and OUT2, pin 3 of U102A is connected to R110 and R113, the other end of R110 is connected to R112 and OUT1, and the other ends of R112 and R113 are connected to the analog ground AGND.

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