Concurrent page cache resource access in multi-plane memory devices

Abstract

This application is directed to concurrent page cache resource access in multi-plane memory devices. A memory device includes a first memory array, a second memory array, and a page cache circuit coupled to the first memory array and the second memory array. The page cache circuit includes at least one set of concurrent resources and at least one shared resource, where the at least one set of concurrent resources is accessible by the first memory array and the second memory array asynchronously and concurrently, and where the at least one shared resource is accessible by the first memory array and the second memory array in a time-multiplexed manner.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to a memory subsystem, and more specifically, to concurrent page cache resource access in a multi-plane memory device within a memory subsystem. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Typically, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this application relates to a memory device comprising: a first memory array; a second memory array; and a page cache circuit coupled to the first memory array and the second memory array, wherein the page cache circuit includes at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources can be accessed asynchronously and concurrently by the first memory array and the second memory array, and wherein the at least one shared resource can be accessed by the first memory array and the second memory array in a time-division multiplexing manner.

[0004] In another aspect, this application relates to a method comprising: receiving at a memory device a request to perform a first memory access operation on a first memory array of the memory device and a second memory access operation on a second memory array; concurrently executing a first portion of the first memory access operation and a first portion of the second memory access operation using a set of concurrent resources of page cache circuitry coupled to the first memory array and the second memory array; selecting a second portion of the first memory access operation to be executed using at least one shared resource of the page cache circuitry using an arbitration scheme; executing the second portion of the first memory access operation using the at least one shared resource of the page cache circuitry; and, upon completion of the second portion of the first memory access operation, executing the second portion of the second memory access operation using the at least one shared resource of the page cache circuitry.

[0005] In another aspect, this application relates to a memory device comprising: a plurality of memory arrays; and a page cache circuit coupled to the plurality of memory arrays, wherein the page cache circuit includes at least a set of concurrent resources configured to perform operations on the plurality of memory arrays concurrently, and at least one shared resource configured to perform operations on the plurality of memory arrays continuously in time. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1 An instance computing system including a memory subsystem is described according to some embodiments of this disclosure.

[0008] Figure 2 This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to an embodiment.

[0009] Figure 3 This is a block diagram illustrating a multiplane memory device configured for concurrent page cache resource access according to some embodiments of the present disclosure.

[0010] Figure 4 This is a block diagram illustrating concurrent page cache resource access in a multi-plane memory device according to some embodiments of the present disclosure.

[0011] Figure 5 This is a timing diagram illustrating concurrent page cache resource access in a multi-plane memory device according to some embodiments of the present disclosure.

[0012] Figure 6 This is a block diagram illustrating concurrent page cache resource access in a multi-plane memory device according to some embodiments of the present disclosure.

[0013] Figure 7 This is a block diagram illustrating concurrent page cache resource access in a multi-plane memory device according to some embodiments of the present disclosure.

[0014] Figure 8 This is a block diagram illustrating concurrent page cache resource access in a multi-plane memory device according to some embodiments of the present disclosure.

[0015] Figure 9 This is a block diagram illustrating concurrent page cache resource access in a multi-plane memory device according to some embodiments of the present disclosure.

[0016] Figure 10 This is a flowchart illustrating an example method of providing concurrent page cache resource access in a multi-plane memory device according to some embodiments of the present disclosure.

[0017] Figure 11 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0018] This disclosure relates to concurrent page cache resource access in a multi-plane memory device within a memory subsystem. The memory subsystem may be a storage device, a memory module, or a hybrid of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Typically, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0019] The memory subsystem may include high-density non-volatile memory devices, where data is expected to be retained when no power is supplied to the memory device. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., "NAND" devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells ("cells"). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states related to the number of bits stored. Logic states may be represented by binary values ​​(e.g., "0" and "1", or combinations of such values).

[0020] Memory devices can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are etched onto a silicon wafer in arrays of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in a memory device, which are used with one or more bit lines to generate the address of each memory cell. The intersection of a bit line and a word line constitutes the address of the memory cell. Hereinafter, a block refers to a cell of a memory device used to store data and may comprise a group of memory cells, a group of word lines, a word line, or a single memory cell. One or more blocks may be combined to form a plane of a memory device to allow concurrent operation on each plane. A memory device may include circuitry that performs concurrent memory page access to two or more memory planes. For example, a memory device may include multiple access line driver circuits and power supply circuitry that can be shared by the planes of the memory device to facilitate concurrent access to pages in two or more memory planes containing different page types. For ease of description, these circuits may be collectively referred to as independent plane driver circuitry.

[0021] In some multiplane memory devices, there is typically a one-to-one correspondence between the memory array associated with each plane and other related circuitry (e.g., independent plane driver circuitry, word line paths, bit line paths, and page caches (e.g., page buffers) containing bit line biasing circuitry, sense amplifiers, and multiple registers). Independent plane driver circuitry allows parallel and concurrent memory access operations to be performed on the corresponding memory array for each plane of the multiplane memory device. However, in the case of a one-to-one correspondence, such as when each plane contains a separate page cache, a large area is consumed by the separate page cache and associated bit line path circuitry. Typically, each page cache may contain multiple registers, such as cache registers and one or more data registers, to support various memory instance operations. For example, when performing multi-bit programming operations (e.g., three-level cell (TLC) or four-level cell (QLC) programming operations), multiple registers are used to temporarily store data. However, for single-level programming operations (e.g., single-level cell (SLC) programming operations) or any read operation, only a single register is used. Therefore, for many operations, certain portions of the page cache are unused and unnecessarily copied for each plane, in which case such portions can be shared by two or more planes of a multi-plane memory device.

[0022] This disclosure addresses the aforementioned and other deficiencies by providing concurrent page cache resource access in a multi-plane memory device within a memory subsystem. In one embodiment, the memory device includes multiple memory arrays (e.g., a first memory array and a second memory array) and a shared page cache circuitry shared by the multiple memory arrays. The page cache circuitry includes multiple resources and, depending on the embodiment, may include at least one set of concurrent resources and at least one shared resource. The set of concurrent resources can be accessed asynchronously and concurrently by the multiple memory arrays, while the at least one shared resource can be accessed by the multiple memory arrays in a time-division multiplexing manner. The page cache circuitry is designed flexibly, allowing more or fewer resources to be designed as concurrent or shared resources. Depending on which resources in the page cache circuitry are concurrent resources (i.e., there are duplicate instances of a given resource corresponding to each of the multiple memory arrays) and which are shared resources (i.e., there is a single instance of a given resource shared by the multiple memory arrays), certain operations or portions of operations can be performed concurrently (i.e., at least partially overlapping in time) on the multiple memory arrays.

[0023] The advantages of this approach include, but are not limited to, improved performance of the memory subsystem. Sharing the resources of a single page cache circuit across multiple memory arrays in a memory device reduces the number of page cache circuits in the memory device, which similarly reduces the size, cost, and complexity of the memory device. Even while providing these savings, the method described herein also provides increased multi-plane read parallelism, increased multi-plane programming parallelism for SLC programming operations, asynchronous page access across multiple memory arrays, and general latency improvements attributable to reduced bit line lengths across multiple memory arrays.

[0024] Figure 1 An example computing system 100 including a memory subsystem 110 is described according to some embodiments of this disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0025] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital storage (SD) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transportation), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercial device), or such computing device containing memory and processing devices.

[0027] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intermediate components), whether wired or wireless, and includes, for example, electrical, optical, magnetic, and other connections.

[0028] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120, for example, uses memory subsystem 110 to write data to and read data from memory subsystem 110.

[0029] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Bus Attached (SATA) interfaces, PCIe interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM socket interfaces supporting DDR), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize a high-speed NVM (NVMe) interface, an Open NAND Flash Interface (ONFI) interface, or some other interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data and other signals between the memory subsystem 110 and the host system 120. Figure 1 The memory subsystem 110 is described as an example. Typically, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0030] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and in-situ write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can combine stackable cross-grid data access arrays to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash memory-based memories, crosspoint non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without pre-erasing them. For example, NAND-type flash memory includes two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0033] Although non-volatile memory components, such as 3D cross-dot arrays of non-volatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include, for example, hardware of one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 may be a processing device configured to execute instructions stored in local memory 119, for example, the processing device comprising one or more processors (processor 117). In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0036] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] Typically, the memory subsystem controller 115 receives commands or operations from the host system 120 and translates these commands or operations into instructions or appropriate commands to enable desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry translates commands received from the host system into command instructions to access the memory device 130 and translates responses associated with the memory device 130 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0039] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that includes raw memory device 130 having on-die control logic (e.g., local media controller 135) and a controller for media management (e.g., memory subsystem controller 115) within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] In one embodiment, memory subsystem 110 includes memory interface component 113. Memory interface component 113 handles interactions between memory subsystem controller 115 and memory devices (e.g., memory device 130) of memory subsystem 110. For example, memory interface component 113 may send memory access commands, such as programming commands, read commands, or other commands, to memory device 130 corresponding to requests received from host system 120. Additionally, memory interface component 113 may receive data from memory device 130, such as data retrieved in response to confirmation that a read command or programming command has been successfully executed. In some embodiments, memory subsystem controller 115 includes at least a portion of memory interface 113. For example, memory subsystem controller 115 may include processor 117 (e.g., processing means) configured to execute instructions stored in local memory 119 to perform the operations described herein. In some embodiments, memory interface component 113 is part of host system 110, an application program, or an operating system.

[0041] In one embodiment, memory device 130 includes a concurrent page buffer (PB) resource access circuitry system 150. In one embodiment, circuitry system 150 provides concurrent page buffer (i.e., page cache) resource access to multiple planes of memory device 130. In one embodiment, each plane includes a separate memory array. Circuitry system 150 may include shared page cache circuitry shared by the separate memory arrays. The page cache circuitry includes multiple resources and, depending on the embodiment, may include at least one set of concurrent resources and at least one shared resource. The set of concurrent resources may be accessed asynchronously and concurrently by the multiple memory arrays, while the at least one shared resource may be accessed by the multiple memory arrays in a time-division multiplexing manner. The design of the page cache circuitry is flexible, allowing more or fewer resources to be designed as concurrent or shared resources. Depending on which resources in the page cache circuitry are concurrent resources (i.e., there are duplicate instances of a given resource corresponding to each of the multiple memory arrays) and which are shared resources (i.e., there is a single instance of a given resource shared by the multiple memory arrays), certain operations or portions of operations can be performed concurrently (i.e., at least partially overlapping in time) on multiple memory arrays. Depending on the embodiment, a single page cache circuitry may exist that is shared by two or more memory arrays (e.g., 2 memory arrays, 4 memory arrays, 8 memory arrays, etc.). In another embodiment, a set of multi-page cache circuitry may exist that is shared by multiple memory arrays in a fully configurable manner. The number of memory arrays may be equal to or greater than the number of page cache circuitry. For example, in one embodiment, two page cache circuitry may exist that are shared by a set of four memory arrays, such that any memory array can access and utilize the resources of either page cache circuitry according to an associated arbitration scheme. Other embodiments are also possible. Further details regarding the operation of the concurrent page buffer (PB) resource access circuitry system 150 are described below.

[0042] Figure 2 A simplified block diagram of a first device in the form of a memory device 130, according to an embodiment, is provided, the first device being associated with a memory subsystem (e.g., a memory device 130). Figure 1 The memory subsystem controller 115 communicates with the second device in the form of the memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical appliances, vehicles, wireless devices, mobile phones, and so on. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device.

[0043] Memory device 130 includes a memory cell array 250 logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access lines (e.g., word lines), while memory cells in logical columns are typically selectively connected to the same data lines (e.g., bit lines). A single access line may be associated with more than one memory cell logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in memory cell array 250 ( Figure 2 (Not shown in the text) It can be programmed to one of at least two target data states.

[0044] Row decoding circuitry 208 and column decoding circuitry 210 are provided to decode address signals. Address signals are received and decoded to access memory cell array 250. Memory device 130 also includes input / output (I / O) control circuitry 212 to manage inputs of commands, addresses, and data to memory device 130 and outputs of data and status information from memory device 130. Address register 214 communicates with I / O control circuitry 212, row decoding circuitry 208, and column decoding circuitry 210 to latch address signals before decoding. Command register 224 communicates with I / O control circuitry 212 and local media controller 135 to latch incoming commands.

[0045] A controller (e.g., a local media controller 135 within memory device 130) responds to commands to control access to memory cell array 250 and generates status information about external memory subsystem controller 115. Specifically, the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on memory cell array 250. The local media controller 135 communicates with row decoding circuitry 208 and column decoding circuitry 210 to control them in response to addresses.

[0046] The local media controller 135 also communicates with a page cache 240, which includes a cache register 242 and a data register 244. The cache register 242, as directed by the local media controller 135, latches incoming or outgoing data to temporarily store data while the memory cell array 250 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from the cache register 242 to the data register 244 for transmission to the memory cell array 250; then, new data can be latched from the I / O control circuitry system 212 into the cache register 242. During read operations, data can be transferred from the cache register 242 to the I / O control circuitry system 212 for output to the memory subsystem controller 115; then, new data can be transferred from the data register 244 back to the cache register 242. The cache register 242 and / or the data register 244 may form part of the page cache 240 of the memory device 130. Page cache 240 may further include a sensing device. Figure 2 (Not shown) to sense the data status of memory cells in memory cell array 250, for example, by sensing the status of data lines connected to the memory cells. Status register 222 can communicate with I / O control circuitry system 212 and local memory controller 135 to latch status information for output to memory subsystem controller 115. In one embodiment, at least a portion of the resources of page cache 240 are shared between two or more planes or two or more portions of a single plane within memory device 130.

[0047] Memory device 130 receives control signals from local media controller 135 via control link 232 at memory subsystem controller 115. For example, control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protection signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received further via control link 232. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 234 and outputs data to memory subsystem controller 115 via I / O bus 234.

[0048] For example, commands can be received at the input / output (I / O) control circuitry 212 via I / O pins [7:0] of the I / O bus 234 and then written to the command register 224. Addresses can be received at the input / output (I / O) control circuitry 212 via I / O pins [7:0] of the I / O bus 234 and then written to the address register 214. Data can be received at the input / output (I / O) control circuitry 212 via I / O pins [7:0] for 8-bit devices or I / O pins [15:0] for 16-bit devices and then written to the cache register 242. The data can then be written to the data register 244 to program the memory cell array 250.

[0049] In this embodiment, cache register 242 may be omitted, and data may be written directly to data register 244. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that provide electrical connections to memory device 130 via external devices (e.g., memory subsystem controller 115).

[0050] Those skilled in the art will understand that additional circuitry and signals can be provided, and Figure 2 The memory device 130 has been simplified. It should be recognized that it may not be necessary to include a reference... Figure 2 The various block components described are functionally isolated to distinguish components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device can be adapted to perform... Figure 2 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 2 The functionality of a single block component. Additionally, while specific I / O pins are described according to common conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0051] Figure 3This is a block diagram illustrating a multi-plane memory device 130 configured for concurrent page cache resource access according to some embodiments of the present disclosure. Memory planes 372(0) to 372(3) can each be divided into data blocks, wherein two or more different relative data blocks from memory planes 372(0) to 372(3) can be accessed concurrently during a memory access operation. For example, during a memory access operation, two or more of the following can be accessed concurrently: data block 382 of memory plane 372(0), data block 383 of memory plane 372(1), data block 384 of memory plane 372(2), and data block 385 of memory plane 372(3).

[0052] Memory device 130 includes a memory array 250, which is divided into memory planes 372(0) to 372(3), each containing a corresponding number of memory cells. The multi-plane memory device 130 may further include a local media controller 135 coupled to the memory array 250. Memory cells may be non-volatile memory cells (e.g., NAND flash memory cells), or generally may be any type of memory cell. In one embodiment, each of memory planes 372(0) to 372(3) contains a memory array of corresponding memory cells. In one embodiment, each of memory planes 372(0) to 372(3) may contain a memory array of two or more independent memory cells.

[0053] In one embodiment, memory planes 372(0) to 372(3) of multiple subgroups may each be coupled to a corresponding page cache 240(0) to 240(1). For example, memory planes 372(0) to 372(3) may be coupled to page cache 240(0) and memory planes 372(0) to 372(1) may be coupled to page cache 240(1). Therefore, the resources of page caches 240(0) to 240(1) may be accessed concurrently by multiple memory planes 372(0) to 372(3). Each page cache 240(0) to 240(1) may be configured to provide data to or receive data from a corresponding set of memory planes 372(0) to 372(3). Page caches 240(0) to 240(1) can be controlled by the local media controller 135, and page caches 240(0) to 240(1) can form a concurrent page buffer (PB) resource access circuitry system 150 together or separately. Data received from the corresponding memory planes 372(0) to 372(3) can be latched separately at page caches 240(0) to 240(1) on a time-division multiplexed basis, retrieved by the local media controller 135, and provided to the memory subsystem controller 115, for example, via the ONFI interface.

[0054] Each of the memory planes 372(0) to 372(3) may be further coupled to a corresponding access driver circuit 374(0) to 374(3), such as an access line driver circuit. The driver circuits 374(0) to 374(3) may be configured to regulate pages of the corresponding blocks of the associated memory planes 372(0) to 372(3) for memory access operations, such as programming data (i.e., writing data), reading data, or erasing data. Each of the driver circuits 374(0) to 374(3) may be coupled to a corresponding global access line associated with the corresponding memory plane 372(0) to 372(3). During a memory access operation associated with a page within a block, each of the global access lines may be selectively coupled to a corresponding local access line within the block of the plane. The driver circuits 374(0) to 374(3) may be controlled based on signals from the local media controller 135. Each of the driver circuits 374(0) to 374(3) may include or be coupled to a corresponding power supply circuit and may provide a voltage to a corresponding access line based on a voltage provided by the corresponding power supply circuit. The voltage provided by the power supply circuit may be based on a signal received from the local media controller 135.

[0055] The local media controller 135 can control driver circuits 374(0) to 374(3) and page caches 240(0) to 240(1) to concurrently perform memory access operations associated with each of a set of memory command and address pairs (e.g., received from memory subsystem controller 115). For example, the local media controller 135 can control driver circuits 374(0) to 374(3) and page caches 240(0) to 240(1) to perform concurrent memory access operations. The local media controller 135 may include power control circuitry, which serially configures two or more of the driver circuits 374(0) to 374(3) for concurrent memory access operations; and access control circuitry 375 configured to control two or more of the buffers 240(0) to 240(1) to sense and latch data from the respective memory planes 372(0) to 372(3), or to program data into the respective memory planes 372(0) to 372(3) to perform concurrent memory access operations.

[0056] In operation, the local media controller 135 may receive a set of memory command and address pairs via an ONFI bus, each pair arriving in parallel or serially. In some instances, the set of memory command and address pairs may each be associated with a different corresponding memory plane 372(0) to 372(3) of the memory array 250. The local media controller 135 may be configured to perform concurrent memory access operations (e.g., read operations or programming operations) on the different memory planes 372(0) to 372(3) of the memory array 250 in response to the set of memory command and address pairs. For example, the power control circuitry of the local media controller 135 may be serially configured for concurrent memory access operations based on the corresponding page type (e.g., UP, MP, LP, XP, SLC / MLC / TLC / QLC pages) for driver circuitry 374(0) to 374(3) associated with the set of memory command and address pairs. After the access line driver circuits 374(0) to 374(3) have been configured, the access control circuitry of the local media controller 135 may concurrently control the page caches 240(0) to 240(1) to access (e.g., retrieve or write data) the corresponding pages of each of the two or more memory planes 372(0) to 372(3) associated with the set of memory command and address pairs during concurrent memory access operations. For example, the access control circuitry may concurrently (e.g., in parallel and / or simultaneously) control the page caches 240(0) to 240(1) to charge / discharge bit lines, sense data from the two or more memory planes 372(0) to 372(3), and / or latch data.

[0057] Based on signals received from the local media controller 135, driver circuits 374(0) to 374(3) coupled to memory planes 372(0) to 372(3) associated with the memory command and address command pairs of the group can select memory or memory cell blocks from the associated memory planes 372(0) to 372(3) for memory operations (e.g., read operations, programming operations, and / or erase operations). Driver circuits 374(0) to 374(3) can drive different corresponding global access lines associated with the respective memory planes 372(0) to 372(3). As an example, driver circuit 374(0) can drive a first voltage on a first global access line associated with memory plane 372(0), driver circuit 374(1) can drive a second voltage on a third global access line associated with memory plane 372(1), driver circuit 374(2) can drive a third voltage on a seventh global access line associated with memory plane 372(2), and so on, and can drive other voltages on each of the remaining global access lines. In some instances, pass voltages can be provided on all access lines except for those associated with pages of memory planes 372(0) to 372(3) to be accessed. Local media controller 135 and driver circuits 374(0) to 374(3) can allow concurrent access to different corresponding pages and page caches 240(0) to 240(1) within different corresponding memory cell blocks. For example, a first page of a first block of a first memory plane can be accessed concurrently with a second page of a second block of a second memory plane, regardless of page type.

[0058] Page caches 240(0) to 240(1) can provide data to or receive data from local media controller 135 in response to signals from local media controller 135 and corresponding memory planes 372(0) to 372(3) during memory access operations. Local media controller 135 can provide the received data to memory subsystem controller 115.

[0059] It should be understood that the memory device 130 may include more or fewer than four memory planes, driver circuitry, and page caches. It will also be understood that the corresponding global access lines may include 8, 16, 32, 64, 128, etc. When different corresponding pages have different page types, the local media controller 135 and driver circuitry 374(0) to 374(3) may concurrently access different corresponding pages within different corresponding blocks of different memory planes.

[0060] Figure 4This is a block diagram illustrating concurrent page cache resource access in a multi-plane memory device 130 according to some embodiments of the present disclosure. As illustrated, the memory device 130 includes at least two separate memory arrays 450 and 452. In other embodiments, any number of separate memory arrays may exist. In one embodiment, memory arrays 450 and 452 may each be associated with a separate plane (e.g., plane 0 and plane 1). In another embodiment, memory arrays 450 and 452 may each be a separate memory array associated with a single plane. Each of memory arrays 450 and 452 may contain an array of memory cells formed at the intersection of word lines and bit lines. In one embodiment, the memory cells are grouped into blocks, which may be further divided into sub-blocks, wherein, for example, a given word line is shared across multiple sub-blocks. In one embodiment, each sub-block corresponds to a separate plane in the memory array. The group of memory cells associated with a word line within a sub-block is called a physical page. Each physical page in one of the sub-blocks may contain multiple page types. For example, a physical page formed by a single-level cell (SLC) has a single page type called a lower logical page (LP). Multilevel cell (MLC) physical page types may include LP and upper logical page (UP), TLC physical page types include LP, UP, and super logical page (XP), and QLC physical page types include LP, UP, XP, and top logical page (TP). For example, a physical page formed by a memory cell of the QLC memory type may have a total of four logical pages, where each logical page may store data different from the data stored in other logical pages associated with that physical page. Depending on the programming scheme used, each logical page of the memory cell may be programmed in a separate programming channel, or multiple logical pages may be programmed together. For example, in a QLC physical page, LP may be programmed in one pass, and UP, XP, and TP may be programmed in a second pass. Other programming schemes are possible.

[0061] In one embodiment, each of memory arrays 450 and 452 has an associated corresponding word line (WL) path 460 and 462. The corresponding word line paths 460 and 462 may include associated signal drivers and other circuitry to interact with the word lines of the associated memory arrays 450 and 452. In one embodiment, there is a shared independent plane driver circuitry 410 and a shared page cache 240. The independent plane driver circuitry 410 may include circuitry for performing concurrent memory page accesses on two or more memory planes of memory arrays (e.g., memory arrays 450 and 452). The page cache 240 is a buffer for temporarily storing data read from or written to the memory arrays 450 and 452, and may include concurrent bit line (BL) bias circuitry 420 and 422, a shared sense amplifier 430, a cache register 242, and one or more data registers 244 to 246. For read operations, data is read from memory arrays 450 or 452 into one of data registers 244 to 246, and then into cache register 242. Memory interface 113 can then read the data from cache register 242. For programming operations, memory interface 113 writes data to cache register 242, then passes it to one of data registers 244 to 246, and finally programs it into one or both of memory arrays 450 or 452. For example, if concurrent BL bias circuits 420 and 422 contain data storage elements (e.g., latches), data from shared data registers 244 to 246 can be temporarily held before being written to the corresponding one of memory arrays 450 or 452 to increase the parallelism of programming operations. If the programming operation involves multiple pages (e.g., UP, XP, and TP), each page can have a dedicated data register to hold the corresponding page data.

[0062] Because in this embodiment, page cache 240 includes separate bit line biasing circuits 420 and 422, the bit lines of the respective memory arrays 450 and 452 can be biased concurrently. For example, as in Figure 5 As illustrated, the biasing operations 502 and 504 on the word lines and bit lines of two separate planes (e.g., plane 0 and plane 1) can be performed concurrently (i.e., at least partially overlapping in time) at time t0. In one embodiment, bit line biasing circuit 420 can apply a voltage signal to one or more bit lines of memory array 450, while bit line biasing circuit 422 can apply a voltage signal to one or more bit lines of memory array 452. Therefore, different memory access operations (e.g., programming operations, read operations) can be performed asynchronously on memory arrays 450 and 452. Thus, bit line biasing circuits 420 and 422 can be considered as concurrent resources of page cache 240.

[0063] Since only a single instance of the sense amplifier 430, cache register 242, and data registers 244 to 246 exists in page cache 240 in this embodiment, these can be considered shared resources. Access to the shared resources can be provided on a time-division multiplexing basis via control logic in memory device 130 (e.g., independent plane driver circuitry 410, local media controller 135). For example, the control logic may implement a prioritization scheme relating to how access to the shared resources in page cache 240 is permitted. In one embodiment, access is permitted on a first-come, first-served basis, wherein access is permitted in response to a first request, and subsequent requests are deferred until the processing of the first request is complete. In another embodiment, the processing logic may implement some other protocol (e.g., priority based on associated memory array or request type, based on request history, etc.). For example, as in Figure 5 As explained, once bias operations 502 and 504 are completed, the sensing and associated refinement 506 of plane 0 can be performed at time t1 using shared resources such as amplifier 430, cache register 242, and data registers 244 to 246. During the time for performing the sensing and associated refinement 506 of plane 0, the operation of plane 1 is blocked 508, suspended, or otherwise delayed. Once the sensing and associated refinement 506 of plane 0 is completed, the sensing and associated refinement 510 of plane 1 can be performed at time t2 using shared resources. However, at the same time t2, the bias operation 512 for plane 0 can be performed by concurrent resources (e.g., bit line bias circuit 420) for subsequent operations. Once the sensing and associated refinement 510 is completed, at time t3, the bias operation 514 for plane 1 can be performed by concurrent resources (e.g., bit line bias circuit 422) for subsequent operations. Once the bias operation 512 is complete, shared resources can be used to perform sensing of plane 0 and associated refinement 516 at time t4, etc.

[0064] Refer again Figure 4 Concurrent resources (e.g., bit line bias circuits 420 and 422) can operate asynchronously to perform associated operations on their respective associated memory arrays, while shared resources (e.g., sense amplifier 430, cache register 242, and data registers 244 to 246) are time-multiplexed with arbitration to perform associated operations. Figure 4 The performance benefits of the design implementation described herein include, but are not limited to, increased parallelism of multi-plane reads and general latency improvements attributable to reduced bit line lengths in memory arrays 450 and 452.

[0065] Figure 6 This is a block diagram illustrating concurrent page cache resource access in a multi-plane memory device 130 according to some embodiments of the present disclosure. (As stated above regarding...) Figure 4As described and illustrated, memory device 130 includes at least two separate memory arrays 450 and 452. In other embodiments, any number of separate memory arrays may be present. In one embodiment, memory arrays 450 and 452 may each be associated with a separate plane (e.g., plane 0 and plane 1) and may each have associated corresponding word line (WL) paths 460 and 462. In one embodiment, a shared page cache 240 is present, which includes concurrent bit line (BL) bias circuitry 420 and 422, a shared sense amplifier 430, a cache register 242, and one or more data registers 244 to 246. However, in this embodiment, instead of a shared independent plane driver circuitry, separate independent plane driver circuitry is present and associated with each memory array 450 and 452. For example, independent plane driver circuitry 610 is associated with memory array 450, and independent plane driver circuitry 612 is associated with memory array 452. Each of independent plane driver circuits 610 and 612 may include circuitry for performing concurrent memory page accesses on the respective associated memory array. These concurrent resources (e.g., independent planar driver circuits 610 and 612, and bit line bias circuits 420 and 422) can operate asynchronously to perform associated operations on their respective associated memory arrays, while shared resources (e.g., sense amplifier 430, cache register 242, and data registers 244 to 246) are time-multiplexed with arbitration to perform associated operations. Figure 6 The performance advantages of the design implementation described herein include, but are not limited to, increased parallelism of multi-plane reads, asynchronous page access for each of memory arrays 450 and 452, and general latency improvements attributable to reduced bit line lengths in memory arrays 450 and 452.

[0066] Figure 7 This is a block diagram illustrating concurrent page cache resource access in a multi-plane memory device 130 according to some embodiments of the present disclosure. (As stated above regarding...) Figure 4As described and illustrated, memory device 130 includes at least two separate memory arrays 450 and 452. In other embodiments, any number of separate memory arrays may be present. In one embodiment, memory arrays 450 and 452 may each be associated with a separate plane (e.g., plane 0 and plane 1) and may each have associated corresponding word line (WL) paths 460 and 462 and independent plane driver circuitry 610 and 612. In one embodiment, a shared page cache 240 is present, which includes concurrent bit line (BL) bias circuitry 420 and 422, concurrent sense amplifiers 730 and 732, and a shared cache register 242 and one or more data registers 244 to 246. For example, sense amplifier 730 is associated with memory array 450 and sense amplifier 732 is associated with memory array 452. Concurrent sense amplifiers 730 and 732 can be used to perform asynchronous and concurrent sensing operations on the respective memory arrays. However, storing any sensed data still involves time-division multiplexing of cache register 242 and data registers 244 to 246. Figure 7 The performance benefits of the design implementation described herein include, but are not limited to, increased multiplane read parallelism, increased multiplane programming parallelism of SLC programming operations, asynchronous page access for each of memory arrays 450 and 452, and general latency improvements attributable to reduced bit line lengths in memory arrays 450 and 452.

[0067] Figure 8 This is a block diagram illustrating concurrent page cache resource access in a multi-plane memory device 130 according to some embodiments of the present disclosure. (As stated above regarding...) Figure 4As described and illustrated, memory device 130 includes at least two separate memory arrays 450 and 452. In other embodiments, any number of separate memory arrays may exist. In one embodiment, memory arrays 450 and 452 may each be associated with a separate plane (e.g., plane 0 and plane 1) and may each have associated corresponding word line (WL) paths 460 and 462 and independent plane driver circuitry 610 and 612. In one embodiment, a shared page cache 240 is present, which includes concurrent bit line (BL) bias circuitry 420 and 422, concurrent sense amplifiers 730 and 732, concurrent cache registers 842a and 842b, and one or more shared data registers 244 to 246. For example, cache register 842a is associated with memory array 450 and cache register 842b is associated with memory array 452. Concurrent cache registers 842a and 842b can be used to perform asynchronous and concurrent memory operations on the respective memory arrays. For example, any read operation or SLC programming operation can be performed completely asynchronously and concurrently on memory arrays 450 and 452, because such operations utilize only a single latch or other data storage element in page cache 240. Figure 8 The performance benefits of the design implementation described herein include, but are not limited to, increased multiplane read parallelism, increased multiplane programming parallelism of SLC programming operations, asynchronous page access for each of memory arrays 450 and 452, and general latency improvements attributable to reduced bit line lengths in memory arrays 450 and 452.

[0068] Figure 9 This is a block diagram illustrating concurrent page cache resource access in a multi-plane memory device 130 according to some embodiments of the present disclosure. (As stated above regarding...) Figure 4 As described and illustrated, memory device 130 includes at least two separate memory arrays 450 and 452. In other embodiments, any number of separate memory arrays may exist. In one embodiment, memory arrays 450 and 452 may each be associated with a separate plane (e.g., plane 0 and plane 1) and may each have associated corresponding word line (WL) paths 460 and 462 and independent plane driver circuitry 610 and 612. In one embodiment, a shared page cache 240 is present, which includes concurrent bit line (BL) bias circuitry 420 and 422, concurrent sense amplifiers 730 and 732, concurrent cache registers 842a and 842b, and one or more shared data registers 244 to 946. In this embodiment, comparable Figure 8The embodiment described herein (which includes PDCn) has one less data register (i.e., PDCn-1). Since a fixed maximum total number of latches is required in page cache 240, adding a cache register (e.g., concurrent cache register 842b) means that one data register can be optionally removed. This removal saves area in page cache 240, reducing cost and complexity.

[0069] Figure 10 This is a flowchart illustrating an example method of providing concurrent page cache resource access in a multi-plane memory device according to some embodiments of the present disclosure. Method 1000 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 1000 is executed by page cache 240 of concurrent page buffer (PB) resource access circuitry 150. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0070] In operation 1005, a request is received. For example, memory device 130 may receive one or more memory access commands / requests to perform corresponding memory access operations. In one embodiment, memory device 130 receives a first request to perform a first memory access operation on a first memory array, such as memory array 450, and a second request to perform a second memory access operation on a second memory array, such as memory array 452. The request may include a corresponding address identifying the corresponding memory array. Depending on the embodiment, the memory access operation may include a read operation, a programmable operation, an erase operation, or some other type of operation. In one embodiment, the request is received from a requester, such as memory subsystem controller 115 or memory interface 113 of host system 120.

[0071] In operation 1010, a request is processed. For example, memory device 130 may perform first and second memory access operations. In one embodiment, memory device 130 uses a set of concurrent resources of page cache circuitry (e.g., page cache 240) coupled to the first memory array and the second memory array to concurrently perform a first portion of the first memory access operation and a first portion of the second memory access operation. As described above, the concurrent resources of page cache 240 may vary depending on the specific implementation. For example, concurrent resources may include a first bit line bias circuitry 420 associated with the first memory array 450 and a second bit line bias circuitry 422 associated with the second memory array 452. In such embodiments, concurrently performing the first portion of the first memory access operation and the first portion of the second memory access operation includes causing bias voltages to be applied to the respective bit lines of the first memory array 450 and the second memory array 452 using the first bit line bias circuitry 420 and the second bit line bias circuitry 422. In other embodiments where the page cache 240 includes other concurrent resources, the first portion of the first and second memory access operations may include other operations and / or procedures.

[0072] In operation 1015, a selection is made. For example, memory device 130 may use an arbitration scheme to select a second portion of one of the first or second memory access operations to be performed using at least one shared resource of page cache 240. Depending on the embodiment, the arbitration scheme may include allocating at least one shared resource based on the request to perform the memory access operation received first in time or based on the priority level associated with the first and second memory access operations. For example, certain types of memory access operations (e.g., read operations) may have a higher priority than others (e.g., programming operations), or a memory access operation for a memory array that was most recently executed may have a lower priority than a memory access operation for another memory array.

[0073] In operation 1020, an operation is performed. For example, page cache 240 may use shared resources to perform a second portion of the first memory access operation. As described above, the shared resources of page cache 240 may vary depending on the specific implementation. For example, the shared resources may include sense amplifier 430, cache register 242, and one or more data registers 244 to 246. In such embodiments, performing the second portion of the first memory access operation includes using sense amplifier 430 to sense voltages from corresponding word lines of the first memory array 450 and storing the corresponding values ​​in cache register 242 or at least one of one or more data registers 244 to 246. In other embodiments where page cache 240 includes other shared resources, the second portion of the first memory access operation may include other operations and / or procedures.

[0074] In operation 1025, the operation is executed. For example, when the second part of the first memory access operation is completed, the page cache 240 may use at least one shared resource to execute the second part of the second memory access operation. Therefore, the shared resources of the page cache 240 are configured to execute the second parts of the first and second memory access operations sequentially in time.

[0075] Figure 11 An example machine illustrating computer system 1100 is described, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein is executable. In some embodiments, computer system 1100 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 may be used to perform controller operations. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0076] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be performed by the machine. Furthermore, while a single machine is described, the term "machine" should also be considered as encompassing any collection of machines that individually or jointly execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0077] Example computer system 1100 includes processing devices 1102 that communicate with each other via bus 1130, main memory 1104 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 1106 (e.g., flash memory, static random access memory (SRAM), etc.), and data storage system 1118.

[0078] Processing device 1102 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing combinations of instruction sets. Processing device 1102 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 1102 is configured to execute instructions 1126 for performing the operations and steps discussed herein. Computer system 1100 may further include a network interface device 1108 for communication via network 1120.

[0079] Data storage system 1118 may include machine-readable storage medium 1124 (also referred to as computer-readable medium, such as non-transitory computer-readable medium) storing one or more sets of instructions 1126 or software embodying any one or more of the methods or functions described herein. Instructions 1126 may also reside wholly or at least partially within main memory 1104 and / or processing device 1102 during execution of the instructions by computer system 1100, both of which also constitute machine-readable storage media. Machine-readable storage medium 1124, data storage system 1118, and / or main memory 1104 may correspond to... Figure 1 The memory subsystem 110.

[0080] Although machine-readable storage medium 1124 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered as including a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as including any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including (but not limited to) solid-state memory, optical media, and magnetic media.

[0081] Some parts of the foregoing detailed description have been presented in terms of the symbolic representation of algorithms and data bit operations within computer memory. These algorithms are described and represented in a manner used by those skilled in the art of data processing to communicate the nature of their work to others skilled in the art. Algorithms are hereby and generally considered to be a self-consistent sequence of operations that leads to a desired result. Operations are those that require physical manipulation of physical quantities. Typically, but not necessarily, these quantities may take the form of electrical or magnetic signals that can be stored, combined, compared, or otherwise manipulated. Referring to these signals as bits, values, elements, symbols, characters, items, numbers, etc., has sometimes proven convenient (primarily for reasons of commonality).

[0082] However, it should be remembered that all these terms and similar terms are associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure can refer to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0083] This disclosure also relates to an apparatus for performing the operations described herein. Such an apparatus may be specifically constructed for a particular purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0084] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the program based on the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will be described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0085] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processing according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

[0086] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the embodiments of the present disclosure without departing from the broader spirit and scope set forth in the appended claims. Therefore, the description and drawings should be considered illustrative rather than restrictive.

Claims

1. A memory device comprising: a first memory array; a second memory array; and a page cache circuit comprising bit line bias circuitry, a sense amplifier, and a plurality of registers, wherein the page cache circuit is coupled to the first memory array and the second memory array, wherein the page cache circuit comprises at least one set of concurrent resources and at least one shared resource, wherein the at least one set of concurrent resources is concurrently accessible by the first memory array and the second memory array to perform memory access operations of the same type or different types, respectively, and wherein the at least one shared resource comprises the sense amplifier and the sense amplifier is time-multiplexed accessible by the first memory array and the second memory array.

2. The memory device of claim 1, wherein the at least one set of concurrent resources comprises a first bit line bias circuit associated with the first memory array and a second bit line bias circuit associated with the second memory array.

3. The memory device of claim 2, wherein the at least one shared resource comprises the sense amplifier, a cache register, and one or more data registers.

4. The memory device of claim 1, wherein the at least one set of concurrent resources comprises a first bit line bias circuit associated with the first memory array and a second bit line bias circuit associated with the second memory array, and a first sense amplifier associated with the first memory array and a second sense amplifier associated with the second memory array.

5. The memory device of claim 4, wherein the at least one shared resource comprises a cache register and one or more data registers.

6. The memory device of claim 1, wherein the at least one set of concurrent resources comprises a first bit line bias circuit associated with the first memory array and a second bit line bias circuit associated with the second memory array, a first sense amplifier associated with the first memory array and a second sense amplifier associated with the second memory array, and a first cache register associated with the first memory array and a second cache register associated with the second memory array.

7. The memory device of claim 6, wherein the at least one shared resource comprises one or more data registers.

8. The memory device of claim 1, wherein the first memory array and the second memory array are disposed on a single memory plane of the memory device.

9. The memory device of claim 1, wherein the first memory array and the second memory array are disposed on separate memory planes of the memory device.

10. A method comprising: receiving, at a memory device, a request to perform a first memory access operation on a first memory array of the memory device and a second memory access operation on a second memory array; concurrently using a set of concurrent resources of page cache circuitry coupled to the first memory array and the second memory array to concurrently perform a first portion of the first memory access operation and a first portion of the second memory access operation; using an arbitration scheme to select a second portion of the first memory access operation to perform using at least one shared resource of the page cache circuitry; performing the second portion of the first memory access operation using the at least one shared resource of the page cache circuitry; and upon completion of the second portion of the first memory access operation, performing a second portion of the second memory access operation using the at least one shared resource of the page cache circuitry.

11. The method of claim 10, wherein the at least one set of concurrent resources comprises a first bit line bias circuit associated with the first memory array and a second bit line bias circuit associated with the second memory array, and wherein concurrently performing the first portion of the first memory access operation and the first portion of the second memory access operation comprises causing a bias voltage to be applied to respective bit lines of the first memory array and the second memory array using the first bit line bias circuit and the second bit line bias circuit.

12. The method of claim 11, wherein the at least one shared resource comprises a sense amplifier, a cache register, and one or more data registers, and wherein performing the second portion of the first memory access operation comprises using the sense amplifier to sense a voltage from a corresponding word line of the first memory array and store a corresponding value in at least one of the cache register or the one or more data registers.

13. The method of claim 10, wherein the at least one set of concurrent resources comprises a first bit line bias circuit associated with the first memory array and a second bit line bias circuit associated with the second memory array, and a first sense amplifier associated with the first memory array and a second sense amplifier associated with the second memory array.

14. The method of claim 13, wherein the at least one shared resource comprises a cache register and one or more data registers.

15. The method of claim 10, wherein the at least one set of concurrent resources comprises a first bit line bias circuit associated with the first memory array and a second bit line bias circuit associated with the second memory array, a first sense amplifier associated with the first memory array and a second sense amplifier associated with the second memory array, and a first cache register associated with the first memory array and a second cache register associated with the second memory array.

16. The method of claim 15, wherein the at least one shared resource comprises one or more data registers.

17. The method of claim 10, wherein the arbitration scheme comprises allocating the at least one shared resource based on a request to perform a memory access operation being received first in time.

18. The method of claim 10, wherein the arbitration scheme comprises allocating the at least one shared resource based on a priority level associated with the first and second memory access operations.

19. The method of claim 10, wherein page cache circuitry is configured to select an order of the operations to be performed consecutively by the at least one shared resource according to an associated arbitration scheme.

20. A memory device comprising: a plurality of memory arrays; and page cache circuitry comprising bit line bias circuitry, a sense amplifier, and a plurality of registers, wherein the page cache circuitry is coupled to the plurality of memory arrays, wherein the page cache circuitry comprises at least one set of concurrent resources configured to perform operations on the plurality of memory arrays concurrently, and at least one shared resource configured to perform operations on the plurality of memory arrays consecutively in time, the at least one shared resource comprising the sense amplifier, wherein the sense amplifier is accessible by the plurality of memory arrays in a time-multiplexed manner.

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