Fast Linear Programming Method for High-Level Synthesis

Abstract

The high-level synthesis fast linear programming method provided by the present invention comprises the following steps: constructing a compressed tree library, which includes a number of compressed trees for describing the input and output of a hardware circuit and the area cost; generating integer linear programming constraints based on the compressed tree library, and constructing an integer linear programming model according to the integer linear programming constraints; solving the integer linear programming model, and generating a compressed tree network description according to the solution result; integrating according to the compressed tree network description to obtain a target hardware circuit description; the method improves the speed of the synthesized circuit and the clock frequency without sacrificing the area by cascading and binding general parallel counters, and can achieve fast linear programming; it can be widely applied to the field of circuit simulation technology.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit simulation, and in particular to a fast linear programming method for high-level synthesis. Background Art

[0002] High-level Synthesis (HLS) refers to the process of automatically converting a logical structure described in a high-level language into a circuit model described in a low-level abstraction language. HLS tools are efficient and fast, which can reduce the design time of hardware engineers and enable software engineers to complete hardware design.

[0003] However, in the related technical solutions, the early compression tree based on carry-save adders and single-column parallel counters performs well in ASIC design, but it cannot well adapt to Field Programmable Gate Array (FPGA), and there may be obvious defects such as slow circuit response speed and low clock frequency. Summary of the Invention

[0004] In view of this, in order to at least partially solve one of the above technical problems or defects, an object of an embodiment of the present invention is to provide a fast algorithm implementation method for a high-level synthesis tool based on integer linear programming and compression tree construction.

[0005] On the one hand, the technical solution of the present application provides a fast linear programming method for high-level synthesis, including the following steps:

[0006] Construct a compression tree library, where the compression tree library includes several compression tree models, and the compression tree models are used to describe the input and output of the hardware circuit and the area cost;

[0007] Based on the compression tree library, generate integer linear programming constraints, and construct an integer linear programming model according to the integer linear programming constraints;

[0008] Solve the integer linear programming model, and generate a compression tree network description according to the solution result;

[0009] Integrate according to the compression tree network description to obtain a target hardware circuit description.

[0010] In a feasible embodiment of the solution of the present application, the step of constructing the compression tree library includes:

[0011] Construct an adder dot graph according to the multi-operand addition in the fast carry chain;

[0012] Determine the output of the compression tree model according to the output points described in the adder dot plot, and determine the input of the compression tree model according to the input points described in the adder dot plot;

[0013] Determine the area cost according to the compression tree value, the output bit width of the compression tree model, and the area efficiency of the compression tree model; the compression tree value is calculated according to the number of input bits of the compression tree model.

[0014] In a feasible embodiment of the solution of this application, the step of generating integer linear programming constraints based on the compression tree library and constructing an integer linear programming model according to the integer linear programming constraints includes:

[0015] Sum all the compression tree models according to the first constraint condition; the first constraint condition is:

[0016] P s，k，i = E s，k，i + F s，k，i + G s，k，i + H s，k，i + R s，k，i + M s，l，i + M s，m，i + M s，h，i

[0017] wherein, the compression tree model includes a dedicated compression tree and a non-dedicated compression tree, i ∈ [0, i max - 1], s ∈ [0, S max - 1]; P s，k，i is the number of the compression tree model type k located in column i in stage s; E s，k，i is the number of the non-dedicated compression tree type k located in column i in stage s; F s，k，i is the number of the dedicated compression tree type k mapped to binding located in column i in stage s; G s，k，i is the number of the compression tree model type k mapped to binding located in column i in stage s; H s，k，i is the number of the dedicated compression tree type k used for cascading located in column i in stage s; R s，k，i is the number of all the compression tree model types k used for cascading in column i in stage s; M s，l，i is the least significant component of the row adder located in column i in stage s; M s，m，i is the middle significant component of the row adder located in column i in stage s; M s，h，i is the most significant component of the row adder located in column i in stage s; i max is the maximum number of columns of the compression tree model; S max is the maximum number of stages of the compression tree model.

[0018] In a feasible embodiment of the solution of the present application, the step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints further includes:

[0019] In the non-output stage, determine the input of the compressed tree model according to the second constraint condition; the second constraint condition is:

[0020]

[0021] where i ∈ [0, i max -1], s ∈ [0, S max -1]; K e is the total number of compressed tree model types, i k is the number of input columns of the compressed tree model type k, I k，i is the number of inputs of the compressed tree model type k located in column i, N s，i is the number of input bits of the stage s located in column i, has the same definition as i and also represents the column number.

[0022] In a feasible embodiment of the solution of the present application, the step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints further includes:

[0023] Determine the number of output bits of the compressed tree model according to the third constraint condition; the third constraint condition is:

[0024]

[0025] where i ∈ [0, i max -1], s ∈ [0, S max -1]; K e is the total number of compressed tree model types; o k is the number of output columns of the compressed tree model type k; Q k，i is the number of outputs of the compressed tree model type k located in column i; N s，i is the number of input bits of the stage s located in column i.

[0026] In a feasible embodiment of the solution of the present application, the step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints further includes:

[0027] Connect the row adder according to the fourth constraint condition; the fourth constraint condition is:

[0028] M s，h，i+1 M s，m，i+1 = Ms，m，i M s，l，i

[0029] where \(i\in[0, i max -1]\), \(s\in[0, S max -1]

[0030] In a feasible embodiment of the solution of this application, the step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints further includes:

[0031] Restricting the number of bits of the integer linear programming model in the output stage according to the fifth constraint condition, where the fifth constraint condition is:

[0032]

[0033] where \(i\in[0, i max \), \(N s，i is the input number of bits at column \(i\) in stage \(s\); \(\gamma\) is an integer determined by the last adder.

[0034] In a feasible embodiment of the solution of this application, the step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints further includes:

[0035] Determining the cascading relationship of the compressed tree model according to the sixth constraint condition; the sixth constraint condition is:

[0036]

[0037] where \(i\in[0, i max \), \(s\in[1, S max -2]\), \(K3\) represents the number of types of dedicated compressed trees for cascading, \(K4\) is the number of all compressed tree model types for cascading; \(o k is the number of output columns of the compressed tree model type \(k\).

[0038] In a feasible embodiment of the solution of this application, the step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints further includes:

[0039] Determining the compressed tree models in each cascading stage in the integer linear programming model according to the seventh constraint condition; the seventh constraint condition is:

[0040]

[0041] where \(i\in[0, i max \), \(s\in[1, Smax -2], K3 represents the number of dedicated compression tree types for cascading, and K4 represents the number of all compression tree model types for cascading; o k is the number of output columns of the compression tree model type k.

[0042] In a feasible embodiment of the solution of this application, the step of generating integer linear programming constraints based on the compression tree library and constructing an integer linear programming model according to the integer linear programming constraints further includes:

[0043] Binding resources to the compression tree model according to the eighth constraint condition, and the eighth constraint condition is:

[0044]

[0045] Determining the objective function of the integer linear programming model by minimizing hardware resources, and the objective function is:

[0046]

[0047] where K1 is the number of dedicated compression tree types for binding in the first mapping; K2 is the number of all compression tree model types for binding in the second mapping; K e is the total number of compression tree model types; A k is the area of the equivalent LUT6 of the compression tree model type k.

[0048] The advantages and beneficial effects of the present invention will be partially given in the following description, and others can be obtained through the specific implementation manners of the present invention:

[0049] The technical solution of this application provides a fast linear programming solution for high-level synthesis, and proposes a compression tree construction method based on integer linear programming. First, a compression tree library is constructed, then integer linear programming constraints are generated based on the compression tree library, and an integer linear programming model is constructed according to the integer linear programming constraints. The compression tree network description is obtained by solving through this model, so as to realize the description of the target hardware circuit; the method improves the speed of the synthesized circuit without sacrificing area and increases the clock frequency through the cascading and binding of general parallel counters, can achieve fast linear programming, and can be widely applied in the application scenarios of designing FPGA fast algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0051] Figure 1 This is the flowchart of the steps of the high-level synthesis fast linear programming method provided in the technical solution of this application;

[0052] Figure 2 This is the schematic diagram of the six-input LUT structure with a fast carry chain in the technical solution of this application;

[0053] Figure 3 This is the schematic diagram of abstracting multi-operand addition into a dot graph in the technical solution of this application;

[0054] Figure 4 This is the dot graph of the compression tree in the technical solution of this application;

[0055] Figure 5 This is the mapping schematic diagram of this compression tree and the hardware circuit;

[0056] Reference signs: 501, Full Adder; 502, Half Adder; 503, Multiplexer; 504, Xor Gate. Detailed implementation manners

[0057] The embodiments of the present invention will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation to the present invention. For the step numbers in the following embodiments, they are only set for the convenience of description and explanation, and no limitation is imposed on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0058] Based on the current related technical solutions, on the basis of integrating the general parallel counter architecture on the FPGA, a compression tree can be constructed to solve the technical defects such as slow circuit response speed and low clock frequency brought by the carry-saving adder and single-column parallel counter in the related technical solutions. Therefore, the technical solution of this application proposes an integer linear programming method for constructing a compression tree based on a general parallel counter on the FPGA; the method of the embodiment supports the cascade and binding between general parallel counters, so as to improve the speed of the synthesized circuit and the clock frequency without sacrificing the area, and realize a fast algorithm.

[0059] In the first aspect, as Figure 1 shown, the technical solution of this application provides a high-level synthesis fast linear programming method; the method includes steps S100 - S400:

[0060] S100. Construct a compressed tree library, which includes several compressed trees for describing the input / output and area cost of a hardware circuit;

[0061] Specifically in the embodiment, the compressed tree library is the basis for constructing the compressed tree and has a great impact on the performance of the compressed tree. Among them, each type of compressed tree (model) is represented by its input, output, and area cost. In the embodiment, a special type of compressed tree is created for GPCs because of their potential for cascading or binding. For example, when GPC(6:3) is cascaded to other GPCs, it can be implemented by using two LUT6s with carry logic. If used for compressed tree binding, because the logic is disjoint, an additional LUT6 is required, and three LUT6s are used.

[0062] S200. Based on the compressed tree library, generate integer linear programming constraints, and construct an integer linear programming model according to the integer linear programming constraints;

[0063] S300. Solve the integer linear programming model, and generate a compressed tree network description according to the solution result;

[0064] S400. Integrate according to the compressed tree network description to obtain a target hardware circuit description;

[0065] Exemplarily, as Figure 2 shown, Figure 2 the six-input LUT with a fast carry chain shown in. A slice is the basic reconfigurable unit of a Xilinx FPGA, which contains 4 six-input LUTs (LUT6s), 8 registers, multiplexers, and a 4-bit carry chain; each LUT6 can be configured to implement a single six-input function, two five-input functions with shared inputs, or a six-input function and a five-input function with shared inputs and shared values. Among them, the carry chain is a dedicated architecture for implementing fast addition or subtraction and can be cascaded to form a larger functional unit. Therefore, the core work of this embodiment is to construct an integer linear programming model for the carry chain based on the application of a fast algorithm. By solving this integer linear programming model, a compressed tree network description of the target hardware circuit is obtained, and a target hardware circuit description is integrated based on the input / output in the compressed tree network description.

[0066] In some feasible embodiments, step S100 of constructing the compressed tree library in the method may include steps S101 - S103;

[0067] S101. Construct an adder dot diagram according to the multi-operand addition in the fast carry chain;

[0068] S102. Determine the output of the compression tree according to the output points described in the adder dot plot, and determine the input of the compression tree according to the input points described in the adder dot plot;

[0069] S103. Determine the area cost according to the compression tree value, the output bit width of the compression tree, and the area efficiency of the compression tree; the compression tree value is calculated according to the number of input bits of the compression tree.

[0070] Exemplarily, as Figure 3 shown, in the embodiment, for better analysis and calculation, multi-operand addition can be abstracted into a dot plot; Figure 3 shows a dot plot containing four four-bit adders. Each dot represents a binary bit of each operand, which can be 0 or 1. A group of dots in a column has the same binary weight value, and the binary weight values are sorted from low on the right to high on the left. Figure 3 The dots above the straight line in describe the inputs to be added, and the dots below the straight line represent the outputs.

[0071] Furthermore, in the embodiment, as Figure 4 shown, a compression tree can be described as [m k-1 , m k-2 ,......, m0; n], where m i is represented by i as the number of input bits in the i-th column, and n represents the bit width of the output. The value M of the compression tree and the output bit width n are calculated by the following formulas:

[0072]

[0073] n = log2(M max + 1) (2)

[0074] The area efficiency of the compression tree is calculated by E, and the value of E is defined as the number of removed bits λ divided by the number of lookup tables LUTs L:

[0075]

[0076] Therefore, each compression tree in step S100 in the embodiment can be represented by three parameters M, n, and E in terms of input, output, and area cost. As Figure 4 shown, Figure 4 depicts the dot plots of GPC(6, 0, 7, 5), (1, 5, 3), and (6, 3). The function of the compression tree can also be represented by a dot plot. A (6, 0, 7; 5) GPC has 6 input bits in column 2, 7 input bits in column 0, and 5 output bits. When all input bits are set to 1, the (6, 0, 7; 5) GPC obtains its maximum value M max = 6 × 2 7 + 7 × 20 = 31 and the output bit width n = log2(31 + 1)= 5. In addition, its hardware cost is 4 six-input LUTs, and the bits removed are 8, measured by the difference between the input bits and the output bits. Therefore, the efficiency of the (6, 0, 7; 5) GPC is E = 8 / 4 = 2.

[0077] In some feasible embodiments, in step S200 of the embodiment, the variables and meanings of the constructed integer linear programming model are shown in Table 1:

[0078] Table 1

[0079] Variable Meaning <![CDATA[S max > Maximum number of stages of the compression tree <![CDATA[i max > Maximum number of columns of the compression tree <![CDATA[I k，i > Number of inputs of compression tree type k in column i <![CDATA[Q k，i > Number of outputs of compression tree type k in column i <![CDATA[P s，k，i > Number of compression trees of type k in column i at stage s <![CDATA[E s，k，i > Number of non-dedicated compression trees of type k in column i at stage s <![CDATA[N s，i > Number of input bits in column i at stage s <![CDATA[K e > Total number of compression types <![CDATA[ι k > Number of input columns of compression tree type k <![CDATA[o k > Number of output columns of compression tree type k γ Integer determined by the last adder <![CDATA[M s，l，i > Least significant component of the row adder in column i at stage s <![CDATA[M s，m，i > Middle significant component of the row adder in column i at stage s <![CDATA[M s，h，i > Most significant component of the row adder in column i at stage s <![CDATA[K1]]> Number of dedicated compression tree types for binding <![CDATA[K2]]> Number of all compression tree types for binding <![CDATA[F s，k，i > Number of dedicated compression tree types of type k mapped to binding in column i at stage s <![CDATA[G s，k，i > Number of all compression tree types of type k mapped to binding in column i at stage s <![CDATA[K3]]> Number of dedicated compression tree types for cascading <![CDATA[K4]]> Number of all compression tree types for cascading <![CDATA[H s，k，i > Number of dedicated compression tree types of type k for cascading in column i at stage s <![CDATA[R s，k，i > Number of all compression tree types of type k for cascading in column i at stage s <![CDATA[A k > Area of the equivalent LUT6 of compression tree type k

[0080] In some feasible embodiments, based on the compressed tree library, generating integer linear programming constraints and constructing an integer linear programming model according to the integer linear programming constraints may include step S201: Summing all compressed trees according to the first constraint condition.

[0081] Specifically, in the embodiment, all compressed trees are summed according to constraint condition 1, including general parallel counters and row adders at each stage of each column. Among them, constraint condition 1 is expressed as:

[0082] P s，k，i = E s，k，i + F s，k，i + G s，k，i + H s，k，i + R s，k，i + M s，l，i + M s，m，i + M s，h，i

[0083] Among them, i ∈ [0, i max - 1], s ∈ [0, S max - 1].

[0084] In some feasible embodiments, based on the compressed tree library, generating integer linear programming constraints and constructing an integer linear programming model according to the integer linear programming constraints may include step S202: Determining the input of the compressed tree according to the second constraint condition in the non-output stage.

[0085] Specifically, in the embodiment, according to constraint condition 2, it is ensured that all bits at each stage of each column are used as the input of the compressed tree except in the output stage. Constraint condition 2 is expressed as:

[0086]

[0087] Among them, i ∈ [0, i max - 1], s ∈ [0, S max - 1], has the same definition as i and also represents the number of columns. The value range of is from 0 to i. k .

[0088] In some feasible embodiments, the step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints may include step S203: determining the output bit number of the compressed tree according to the third constraint condition.

[0089] Specifically in the embodiment, the embodiment calculates the output bit number generated by the compressed tree according to constraint condition 3. Constraint condition 3 is expressed as:

[0090]

[0091] where i ∈ [0, i max -1], s ∈ [0, S max -1].

[0092] In some feasible embodiments, the step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints may include step S204: connecting the row adders according to the fourth constraint condition.

[0093] Specifically, the embodiment ensures the correct connection of the row adders according to constraint condition 4. Constraint condition 4 is expressed as:

[0094] M s，h，i+1 M s，m，i+1 = M s，m，i M s，l，i

[0095] where i ∈ [0, i max -1], s ∈ [0, S max -1].

[0096] In some feasible embodiments, the step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints may include step S205: restricting the bit number of the integer linear programming model in the output stage according to the fifth constraint condition.

[0097] Specifically, the embodiment restricts the bit number in the output stage according to constraint condition 5. Constraint condition 5 is expressed as:

[0098]

[0099] where i ∈ [0, i max .

[0100] In some feasible embodiments, the step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints may include step S206: determining the cascading relationship of the compressed trees according to the sixth constraint condition.

[0101] Specifically, the embodiment ensures that a compressed tree can only be cascaded once according to constraint condition 6. Constraint condition 6 is expressed as:

[0102]

[0103] where i ∈ [0, i mmax , s ∈ [1, S max -2].

[0104] In some feasible embodiments, the step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints may include step S207: determining the compressed trees in each cascading stage in the integer linear programming model according to the seventh constraint condition.

[0105] Specifically, the embodiment ensures that the prerequisite for cascading is the existence of a suitable compressed tree in the next stage according to constraint condition 7. Constraint condition 7 is expressed as:

[0106]

[0107] where i ∈ [0, i mmax , s ∈ [1, S max -2].

[0108] In some feasible embodiments, the step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints may include step S208: performing resource binding on the compressed trees according to the eighth constraint condition.

[0109] Specifically, the embodiment ensures the correct use of specific compressed trees for resource binding according to constraint condition 8. Constraint condition 8 is expressed as:

[0110]

[0111] In some feasible embodiments, the step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints may include step S209: determining the objective function of the integer linear programming model by minimizing the hardware resources.

[0112] Specifically, the objective function in the embodiment is to minimize the hardware resources; the objective function is:

[0113]

[0114] In some other feasible embodiments, the open-source solving tool lpsolve is used to solve the integer linear programming model in step S300; the high-level synthesis tool SHANG based on the difference constraint system is used to obtain the hardware circuit description.

[0115] As Figure 5 shown, the schematic diagrams and gate-level mappings of GPC(7;3), (6, 0, 7, 5), (1, 3, 5, 4), and (2, 1, 1, 7, 5) in the Xilinx FPGA are shown. In this embodiment, a, bn, cn, and dn respectively represent the GPC inputs related to columns 0, 1, 2, and 3, and Zn represents the GPC output. Taking the Xilinx Virtex6 device as an example in this embodiment, the GPC mapping proposed by the technical solution of the present application can also be applied to other similar Xilinx FPGAs.

[0116] In some feasible implementation manners, the system verilog code of the circuit description of the compression tree generated by the SHANG high-level synthesis tool equivalently describes the structure of the compression tree.

[0117] In summary, the technical solution of the present application can be widely applied to FPGA fast algorithms containing a large number of multiplications and additions.

[0118] Exemplarily, fast multipliers play an important role in the application of many fast algorithms. Experiments were carried out using fast multipliers to more comprehensively test the compression tree implementation method proposed by the present invention. During the experiment, the bit width n of the multiplier was the same as that of the multiplicand, where n varied from 10 to 24. The proposed compression tree and the two-input adder tree were used to sum the same partial products generated by the Booth algorithm.

[0119] As shown in Table 2, the implementation results of fast multiplication are shown. Among them, the multiplier constructed using the combination of the Booth algorithm and the proposed compression tree is represented by "Booth+prop.ILP". ILP and those constructed using the combination of the Booth algorithm and the two-input adder tree are represented by "Booth+Adder tree". It can be seen that using the proposed compression tree can significantly reduce the average number of slices by 27.86%. Compared with using the adder tree, the average maximum clock frequency increases slightly (0.14%). That is to say, under the same area limit, better speed performance can be obtained using the fast algorithm implementation method of a high-level synthesis tool of the present invention.

[0120] Table 2

[0121]

[0122] From the above specific implementation process, it can be summarized that the technical solution provided by the present invention has the following advantages or advantages compared with the prior art:

[0123] The method improves the speed of the synthesized circuit and increases the clock frequency without sacrificing area by cascading and binding general parallel counters, enabling fast linear programming and being widely applicable to application scenarios for designing FPGA fast algorithms.

[0124] In some alternative embodiments, the functions / operations mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the functions / operations involved, two consecutive blocks shown may actually be executed substantially simultaneously or the blocks can sometimes be executed in the reverse order. In addition, the embodiments presented and described in the flowcharts of the present invention are provided by way of example for the purpose of providing a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logical flows presented herein. Alternative embodiments are contemplated where the order of various operations is changed and where sub-operations described as part of a larger operation are executed independently.

[0125] Furthermore, although the present invention has been described in the context of functional modules, it should be understood that, unless otherwise stated to the contrary, one or more of the functions and / or features may be integrated in a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It is also understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present invention. Rather, given the attributes, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the modules will be understood within the ordinary skills of an engineer. Therefore, those skilled in the art can implement the present invention as set forth in the claims without undue experimentation. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0126] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered a sequenced list of executable instructions for implementing logical functions, which can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device.

[0127] In the description of this specification, the descriptions referring to terms such as "one embodiment", "some embodiments", "examples", "specific examples", or "some examples", etc., mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0128] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the claims and their equivalents.

[0129] The above has specifically described the preferred embodiments of the present invention, but the present invention is not limited to the above embodiments. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A fast linear programming method for high-level synthesis, characterized in that, including the following steps: Construct a compressed tree library, which includes several compressed tree models for describing the input and output of a hardware circuit and its area cost; Generate integer linear programming constraints based on the compressed tree library, and construct an integer linear programming model according to the integer linear programming constraints; Solve the integer linear programming model, and generate a compressed tree network description according to the solution result; Integrate according to the compressed tree network description to obtain a target hardware circuit description; The step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints includes: Summing all the compressed tree models according to the first constraint condition; the first constraint condition is: P s，k，i = E s，k，i + F s，k，i + G s，k，i + H s，k，i + R s，k，i + M s，l，i + M s，m，i + M s，h，i Among them, the compression tree model includes a dedicated compression tree and a non-dedicated compression tree, i ∈ [0, i max -1], s ∈ [0, S max -1]; P s,k,i is the number of the compression tree model type k in column i in stage s; E s,k,i is the number of the non-dedicated compression tree type k in column i in stage s; F s,k,i is the number of the dedicated compression tree type k mapped to binding in column i in stage s; G s,k,i is the number of the compression tree model type k mapped to binding in column i in stage s; H s,k,i is the number of the dedicated compression tree type k for cascading in column i in stage s; R s,k,i is the number of all compression tree model type k for cascading in column i in stage s; M s,l,i is the least significant component of the row adder in column i in stage s; M s,m,i is the middle significant component of the row adder in column i in stage s; M s,h,i is the most significant component of the row adder in column i in stage s; i max is the maximum number of columns of the compression tree model; S max is the maximum number of stages of the compression tree model.

2. The fast linear programming method for high-level synthesis according to claim 1, wherein The step of constructing the compressed tree library includes: Construct an adder dot diagram according to the multi-operand addition in the fast carry chain; Determine the output of the compressed tree model according to the output points described in the adder dot diagram, and determine the input of the compressed tree model according to the input points described in the adder dot diagram; Determine the area cost according to the compressed tree value, the output bit width of the compressed tree model, and the area efficiency of the compressed tree model; the compressed tree value is calculated according to the input bit number of the compressed tree model.

3. The fast linear programming method for high-level synthesis according to claim 1, characterized in that The step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints further includes: In the non-output stage, determine the input of the compressed tree model according to the second constraint condition; the second constraint condition is: where \(i\in[0, i max - 1]\), \(s\in[0, S max - 1]\); \(K e is the total number of types of the compression tree model, \(i k is the number of input columns of the compression tree model type \(k\), \(I k,i is the number of inputs of the compression tree model type \(k\) located in column \(i\), \(N s,i is the number of input bits located in column \(i\) at stage \(s\).

4. The fast linear programming method for high-level synthesis according to claim 1, characterized in that The step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints further includes: Determine the output bit number of the compressed tree model according to the third constraint condition; the third constraint condition is: where \(i\in[0, i max - 1]\), \(s\in[0, S max - 1]\); \(K e is the total number of compression tree model types; \(o k is the number of output columns of compression tree model type \(k\); \(Q k,i is the number of outputs of compression tree model type \(k\) located in column \(i\); \(N s,i is the number of input bits located in column \(i\) at stage \(s\).

5. The fast linear programming method for high-level synthesis according to claim 1, characterized in that The step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints further includes: Connect the row adders according to the fourth constraint condition; the fourth constraint condition is: M s，h，i+1 M s，m，i+1 = M s，m，i M s，l，i where \(i\in[0, i max - 1]\), \(s\in[0, S max - 1]\).

6. The fast linear programming method for high-level synthesis according to claim 1, characterized in that The step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints further includes: Limit the bit number of the integer linear programming model in the output stage according to the fifth constraint condition; the fifth constraint condition is: where \(i\in[0, i max \), is the input bit located in column \(i\) of stage \(S max \); \(\gamma\) is an integer determined by the last adder.

7. The fast linear programming method for high-level synthesis according to claim 1, characterized in that The step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints further includes: Determine the cascade relationship of the compressed tree models according to the sixth constraint condition; the sixth constraint condition is: where \(i\in[0, i max , s\in[1, S max -2]\), \(K3\) represents the number of dedicated compression tree types for cascading, \(K4\) is the number of all compression tree model types for cascading; o k is the number of output columns of the compression tree model type \(k\).

8. The fast linear programming method for high-level synthesis according to claim 1, characterized in that The step of generating integer linear programming constraints based on the compressed tree library and constructing an integer linear programming model according to the integer linear programming constraints further includes: Determine the compressed tree models in each cascade stage in the integer linear programming model according to the seventh constraint condition; the seventh constraint condition is: where \(i\in[0, i max , s\in[1, S max -2]\), \(K3\) represents the number of dedicated compression tree types for cascading, and \(K4\) represents the number of all compression tree model types for cascading; \(o k is the number of output columns of the compression tree model type \(k\).

9. The fast linear programming method for high-level synthesis according to claim 1, characterized in that The step of generating integer linear programming constraints based on the compressed treebank and constructing an integer linear programming model according to the integer linear programming constraints further includes: Binding resources to the compressed tree model according to an eighth constraint condition; the eighth constraint condition is: Determining an objective function of the integer linear programming model by minimizing hardware resources, and the objective function is: Among them, K1 is the number of dedicated compression tree types used for binding in the first mapping; K2 is the number of all compression tree model types used for binding in the second mapping; K e is the total number of compression tree model types; A k is the area of the equivalent LUT6 of the compression tree model type k.

Images